1 /* 2 * Copyright (c) 2020-2021, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef PLATFORM_DEF_H 8 #define PLATFORM_DEF_H 9 10 #include <lib/utils_def.h> 11 #include <lib/xlat_tables/xlat_tables_defs.h> 12 #include <plat/arm/board/common/board_css_def.h> 13 #include <plat/arm/board/common/v2m_def.h> 14 #include <plat/arm/common/arm_def.h> 15 #include <plat/arm/common/arm_spm_def.h> 16 #include <plat/arm/css/common/css_def.h> 17 #include <plat/arm/soc/common/soc_css_def.h> 18 #include <plat/common/common_def.h> 19 20 #define PLATFORM_CORE_COUNT 8 21 22 #define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00080000 /* 512 KB */ 23 24 /* 25 * The top 16MB of ARM_DRAM1 is configured as secure access only using the TZC, 26 * its base is ARM_AP_TZC_DRAM1_BASE. 27 * 28 * Reserve 32MB below ARM_AP_TZC_DRAM1_BASE for: 29 * - BL32_BASE when SPD_spmd is enabled 30 * - Region to load Trusted OS 31 */ 32 #define TC_TZC_DRAM1_BASE (ARM_AP_TZC_DRAM1_BASE - \ 33 TC_TZC_DRAM1_SIZE) 34 #define TC_TZC_DRAM1_SIZE UL(0x02000000) /* 32 MB */ 35 #define TC_TZC_DRAM1_END (TC_TZC_DRAM1_BASE + \ 36 TC_TZC_DRAM1_SIZE - 1) 37 38 #define TC_NS_DRAM1_BASE ARM_DRAM1_BASE 39 #define TC_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ 40 ARM_TZC_DRAM1_SIZE - \ 41 TC_TZC_DRAM1_SIZE) 42 #define TC_NS_DRAM1_END (TC_NS_DRAM1_BASE + \ 43 TC_NS_DRAM1_SIZE - 1) 44 45 /* 46 * Mappings for TC DRAM1 (non-secure) and TC TZC DRAM1 (secure) 47 */ 48 #define TC_MAP_NS_DRAM1 MAP_REGION_FLAT( \ 49 TC_NS_DRAM1_BASE, \ 50 TC_NS_DRAM1_SIZE, \ 51 MT_MEMORY | MT_RW | MT_NS) 52 53 54 #define TC_MAP_TZC_DRAM1 MAP_REGION_FLAT( \ 55 TC_TZC_DRAM1_BASE, \ 56 TC_TZC_DRAM1_SIZE, \ 57 MT_MEMORY | MT_RW | MT_SECURE) 58 /* 59 * Max size of SPMC is 2MB for tc. With SPMD enabled this value corresponds to 60 * max size of BL32 image. 61 */ 62 #if defined(SPD_spmd) 63 #define PLAT_ARM_SPMC_BASE TC_TZC_DRAM1_BASE 64 #define PLAT_ARM_SPMC_SIZE UL(0x200000) /* 2 MB */ 65 #endif 66 67 /* 68 * PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the 69 * plat_arm_mmap array defined for each BL stage. 70 */ 71 #if defined(IMAGE_BL31) 72 # if SPM_MM 73 # define PLAT_ARM_MMAP_ENTRIES 9 74 # define MAX_XLAT_TABLES 7 75 # define PLAT_SP_IMAGE_MMAP_REGIONS 7 76 # define PLAT_SP_IMAGE_MAX_XLAT_TABLES 10 77 # else 78 # define PLAT_ARM_MMAP_ENTRIES 8 79 # define MAX_XLAT_TABLES 8 80 # endif 81 #elif defined(IMAGE_BL32) 82 # define PLAT_ARM_MMAP_ENTRIES 8 83 # define MAX_XLAT_TABLES 5 84 #elif !USE_ROMLIB 85 # define PLAT_ARM_MMAP_ENTRIES 11 86 # define MAX_XLAT_TABLES 7 87 #else 88 # define PLAT_ARM_MMAP_ENTRIES 12 89 # define MAX_XLAT_TABLES 6 90 #endif 91 92 /* 93 * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size 94 * plus a little space for growth. 95 */ 96 #define PLAT_ARM_MAX_BL1_RW_SIZE 0xC000 97 98 /* 99 * PLAT_ARM_MAX_ROMLIB_RW_SIZE is define to use a full page 100 */ 101 102 #if USE_ROMLIB 103 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0x1000 104 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0xe000 105 #else 106 #define PLAT_ARM_MAX_ROMLIB_RW_SIZE 0 107 #define PLAT_ARM_MAX_ROMLIB_RO_SIZE 0 108 #endif 109 110 /* 111 * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a 112 * little space for growth. 113 */ 114 #if TRUSTED_BOARD_BOOT 115 # define PLAT_ARM_MAX_BL2_SIZE 0x20000 116 #else 117 # define PLAT_ARM_MAX_BL2_SIZE 0x14000 118 #endif 119 120 /* 121 * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is 122 * calculated using the current BL31 PROGBITS debug size plus the sizes of 123 * BL2 and BL1-RW 124 */ 125 #define PLAT_ARM_MAX_BL31_SIZE 0x3B000 126 127 /* 128 * Size of cacheable stacks 129 */ 130 #if defined(IMAGE_BL1) 131 # if TRUSTED_BOARD_BOOT 132 # define PLATFORM_STACK_SIZE 0x1000 133 # else 134 # define PLATFORM_STACK_SIZE 0x440 135 # endif 136 #elif defined(IMAGE_BL2) 137 # if TRUSTED_BOARD_BOOT 138 # define PLATFORM_STACK_SIZE 0x1000 139 # else 140 # define PLATFORM_STACK_SIZE 0x400 141 # endif 142 #elif defined(IMAGE_BL2U) 143 # define PLATFORM_STACK_SIZE 0x400 144 #elif defined(IMAGE_BL31) 145 # if SPM_MM 146 # define PLATFORM_STACK_SIZE 0x500 147 # else 148 # define PLATFORM_STACK_SIZE 0x400 149 # endif 150 #elif defined(IMAGE_BL32) 151 # define PLATFORM_STACK_SIZE 0x440 152 #endif 153 154 155 #define TC_DEVICE_BASE 0x21000000 156 #define TC_DEVICE_SIZE 0x5f000000 157 158 // TC_MAP_DEVICE covers different peripherals 159 // available to the platform 160 #define TC_MAP_DEVICE MAP_REGION_FLAT( \ 161 TC_DEVICE_BASE, \ 162 TC_DEVICE_SIZE, \ 163 MT_DEVICE | MT_RW | MT_SECURE) 164 165 166 #define TC_FLASH0_RO MAP_REGION_FLAT(V2M_FLASH0_BASE,\ 167 V2M_FLASH0_SIZE, \ 168 MT_DEVICE | MT_RO | MT_SECURE) 169 170 #define PLAT_ARM_NSTIMER_FRAME_ID 0 171 172 #define PLAT_ARM_TRUSTED_ROM_BASE 0x0 173 #define PLAT_ARM_TRUSTED_ROM_SIZE 0x00080000 /* 512KB */ 174 175 #define PLAT_ARM_NSRAM_BASE 0x06000000 176 #define PLAT_ARM_NSRAM_SIZE 0x00080000 /* 512KB */ 177 178 #define PLAT_ARM_DRAM2_BASE ULL(0x8080000000) 179 #define PLAT_ARM_DRAM2_SIZE ULL(0x180000000) 180 181 #define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_IRQ_PROPS(grp) 182 #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) 183 184 #define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \ 185 PLAT_SP_IMAGE_NS_BUF_SIZE) 186 187 /******************************************************************************* 188 * Memprotect definitions 189 ******************************************************************************/ 190 /* PSCI memory protect definitions: 191 * This variable is stored in a non-secure flash because some ARM reference 192 * platforms do not have secure NVRAM. Real systems that provided MEM_PROTECT 193 * support must use a secure NVRAM to store the PSCI MEM_PROTECT definitions. 194 */ 195 #define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \ 196 V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE) 197 198 /*Secure Watchdog Constants */ 199 #define SBSA_SECURE_WDOG_BASE UL(0x2A480000) 200 #define SBSA_SECURE_WDOG_TIMEOUT UL(100) 201 202 #define PLAT_ARM_SCMI_CHANNEL_COUNT 1 203 204 #define PLAT_ARM_CLUSTER_COUNT U(1) 205 #define PLAT_MAX_CPUS_PER_CLUSTER U(8) 206 #define PLAT_MAX_PE_PER_CPU U(1) 207 208 #define PLAT_CSS_MHU_BASE UL(0x45400000) 209 #define PLAT_MHUV2_BASE PLAT_CSS_MHU_BASE 210 211 #define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2 212 #define PLAT_MAX_PWR_LVL ARM_PWR_LVL1 213 214 /* 215 * Physical and virtual address space limits for MMU in AARCH64 216 */ 217 #define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 36) 218 #define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 36) 219 220 /* GIC related constants */ 221 #define PLAT_ARM_GICD_BASE UL(0x30000000) 222 #define PLAT_ARM_GICC_BASE UL(0x2C000000) 223 #define PLAT_ARM_GICR_BASE UL(0x30080000) 224 225 /* 226 * PLAT_CSS_MAX_SCP_BL2_SIZE is calculated using the current 227 * SCP_BL2 size plus a little space for growth. 228 */ 229 #define PLAT_CSS_MAX_SCP_BL2_SIZE 0x20000 230 231 /* 232 * PLAT_CSS_MAX_SCP_BL2U_SIZE is calculated using the current 233 * SCP_BL2U size plus a little space for growth. 234 */ 235 #define PLAT_CSS_MAX_SCP_BL2U_SIZE 0x20000 236 237 /* TZC Related Constants */ 238 #define PLAT_ARM_TZC_BASE UL(0x25000000) 239 #define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0) 240 241 #define TZC400_OFFSET UL(0x1000000) 242 #define TZC400_COUNT 4 243 244 #define TZC400_BASE(n) (PLAT_ARM_TZC_BASE + \ 245 (n * TZC400_OFFSET)) 246 247 #define TZC_NSAID_DEFAULT U(0) 248 249 #define PLAT_ARM_TZC_NS_DEV_ACCESS \ 250 (TZC_REGION_ACCESS_RDWR(TZC_NSAID_DEFAULT)) 251 252 /* 253 * The first region below, TC_TZC_DRAM1_BASE (0xfd000000) to 254 * ARM_SCP_TZC_DRAM1_END (0xffffffff) will mark the last 48 MB of DRAM as 255 * secure. The second region gives non secure access to rest of DRAM. 256 */ 257 #define TC_TZC_REGIONS_DEF \ 258 {TC_TZC_DRAM1_BASE, ARM_SCP_TZC_DRAM1_END, \ 259 TZC_REGION_S_RDWR, PLAT_ARM_TZC_NS_DEV_ACCESS}, \ 260 {TC_NS_DRAM1_BASE, TC_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \ 261 PLAT_ARM_TZC_NS_DEV_ACCESS} 262 263 /* virtual address used by dynamic mem_protect for chunk_base */ 264 #define PLAT_ARM_MEM_PROTEC_VA_FRAME UL(0xc0000000) 265 266 #endif /* PLATFORM_DEF_H */ 267