1 /*
2  * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
3  * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 #ifndef TEGRA_DEF_H
9 #define TEGRA_DEF_H
10 
11 #include <lib/utils_def.h>
12 
13 /*******************************************************************************
14  * Platform BL31 specific defines.
15  ******************************************************************************/
16 #define BL31_SIZE			U(0x40000)
17 
18 /*******************************************************************************
19  * Power down state IDs
20  ******************************************************************************/
21 #define PSTATE_ID_CORE_POWERDN		U(7)
22 #define PSTATE_ID_CLUSTER_IDLE		U(16)
23 #define PSTATE_ID_SOC_POWERDN		U(27)
24 
25 /*******************************************************************************
26  * This value is used by the PSCI implementation during the `SYSTEM_SUSPEND`
27  * call as the `state-id` field in the 'power state' parameter.
28  ******************************************************************************/
29 #define PLAT_SYS_SUSPEND_STATE_ID	PSTATE_ID_SOC_POWERDN
30 
31 /*******************************************************************************
32  * Platform power states (used by PSCI framework)
33  *
34  * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID
35  * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID
36  ******************************************************************************/
37 #define PLAT_MAX_RET_STATE		U(1)
38 #define PLAT_MAX_OFF_STATE		(PSTATE_ID_SOC_POWERDN + U(1))
39 
40 /*******************************************************************************
41  * Chip specific page table and MMU setup constants
42  ******************************************************************************/
43 #define PLAT_PHY_ADDR_SPACE_SIZE	(ULL(1) << 35)
44 #define PLAT_VIRT_ADDR_SPACE_SIZE	(ULL(1) << 35)
45 
46 /*******************************************************************************
47  * SC7 entry firmware's header size
48  ******************************************************************************/
49 #define SC7ENTRY_FW_HEADER_SIZE_BYTES	U(0x400)
50 
51 /*******************************************************************************
52  * Counter-timer physical secure timer PPI
53  ******************************************************************************/
54 #define TEGRA210_TIMER1_IRQ		32
55 
56 /*******************************************************************************
57  * iRAM memory constants
58  ******************************************************************************/
59 #define TEGRA_IRAM_BASE			U(0x40000000)
60 #define TEGRA_IRAM_A_SIZE		U(0x10000) /* 64KB */
61 #define TEGRA_IRAM_SIZE			U(40000) /* 256KB */
62 
63 /*******************************************************************************
64  * GIC memory map
65  ******************************************************************************/
66 #define TEGRA_GICD_BASE			U(0x50041000)
67 #define TEGRA_GICC_BASE			U(0x50042000)
68 
69 /*******************************************************************************
70  * Secure IRQ definitions
71  ******************************************************************************/
72 #define TEGRA210_WDT_CPU_LEGACY_FIQ		U(28)
73 
74 /*******************************************************************************
75  * Tegra Memory Select Switch Controller constants
76  ******************************************************************************/
77 #define TEGRA_MSELECT_BASE		U(0x50060000)
78 
79 #define MSELECT_CONFIG			U(0x0)
80 #define ENABLE_WRAP_INCR_MASTER2_BIT	(U(1) << U(29))
81 #define ENABLE_WRAP_INCR_MASTER1_BIT	(U(1) << U(28))
82 #define ENABLE_WRAP_INCR_MASTER0_BIT	(U(1) << U(27))
83 #define UNSUPPORTED_TX_ERR_MASTER2_BIT	(U(1) << U(25))
84 #define UNSUPPORTED_TX_ERR_MASTER1_BIT	(U(1) << U(24))
85 #define ENABLE_UNSUP_TX_ERRORS		(UNSUPPORTED_TX_ERR_MASTER2_BIT | \
86 					 UNSUPPORTED_TX_ERR_MASTER1_BIT)
87 #define ENABLE_WRAP_TO_INCR_BURSTS	(ENABLE_WRAP_INCR_MASTER2_BIT | \
88 					 ENABLE_WRAP_INCR_MASTER1_BIT | \
89 					 ENABLE_WRAP_INCR_MASTER0_BIT)
90 
91 /*******************************************************************************
92  * Tegra Resource Semaphore constants
93  ******************************************************************************/
94 #define TEGRA_RES_SEMA_BASE		0x60001000UL
95 #define  STA_OFFSET			0UL
96 #define  SET_OFFSET			4UL
97 #define  CLR_OFFSET			8UL
98 
99 /*******************************************************************************
100  * Tegra Primary Interrupt Controller constants
101  ******************************************************************************/
102 #define TEGRA_PRI_ICTLR_BASE		0x60004000UL
103 #define  CPU_IEP_FIR_SET		0x18UL
104 
105 /*******************************************************************************
106  * Tegra micro-seconds timer constants
107  ******************************************************************************/
108 #define TEGRA_TMRUS_BASE		U(0x60005010)
109 #define TEGRA_TMRUS_SIZE		U(0x1000)
110 
111 /*******************************************************************************
112  * Tegra Clock and Reset Controller constants
113  ******************************************************************************/
114 #define TEGRA_CAR_RESET_BASE		U(0x60006000)
115 #define TEGRA_BOND_OUT_H		U(0x74)
116 #define  APB_DMA_LOCK_BIT		(U(1) << 2)
117 #define  AHB_DMA_LOCK_BIT		(U(1) << 1)
118 #define TEGRA_BOND_OUT_U		U(0x78)
119 #define  IRAM_D_LOCK_BIT		(U(1) << 23)
120 #define  IRAM_C_LOCK_BIT		(U(1) << 22)
121 #define  IRAM_B_LOCK_BIT		(U(1) << 21)
122 #define TEGRA_GPU_RESET_REG_OFFSET	U(0x28C)
123 #define TEGRA_GPU_RESET_GPU_SET_OFFSET	U(0x290)
124 #define  GPU_RESET_BIT			(U(1) << 24)
125 #define  GPU_SET_BIT			(U(1) << 24)
126 #define TEGRA_RST_DEV_SET_Y		U(0x2a8)
127 #define  NVENC_RESET_BIT		(U(1) << 27)
128 #define  TSECB_RESET_BIT		(U(1) << 14)
129 #define  APE_RESET_BIT			(U(1) << 6)
130 #define  NVJPG_RESET_BIT		(U(1) << 3)
131 #define  NVDEC_RESET_BIT		(U(1) << 2)
132 #define TEGRA_RST_DEV_SET_L		U(0x300)
133 #define  HOST1X_RESET_BIT		(U(1) << 28)
134 #define  ISP_RESET_BIT			(U(1) << 23)
135 #define  USBD_RESET_BIT			(U(1) << 22)
136 #define  VI_RESET_BIT			(U(1) << 20)
137 #define  SDMMC4_RESET_BIT		(U(1) << 15)
138 #define  SDMMC1_RESET_BIT		(U(1) << 14)
139 #define  SDMMC2_RESET_BIT		(U(1) << 9)
140 #define TEGRA_RST_DEV_SET_H		U(0x308)
141 #define  USB2_RESET_BIT			(U(1) << 26)
142 #define  APBDMA_RESET_BIT		(U(1) << 2)
143 #define  AHBDMA_RESET_BIT		(U(1) << 1)
144 #define TEGRA_RST_DEV_SET_U		U(0x310)
145 #define  XUSB_DEV_RESET_BIT		(U(1) << 31)
146 #define  XUSB_HOST_RESET_BIT		(U(1) << 25)
147 #define  TSEC_RESET_BIT			(U(1) << 19)
148 #define  PCIE_RESET_BIT			(U(1) << 6)
149 #define  SDMMC3_RESET_BIT		(U(1) << 5)
150 #define TEGRA_RST_DEVICES_V		U(0x358)
151 #define TEGRA_RST_DEVICES_W		U(0x35C)
152 #define  ENTROPY_CLK_ENB_BIT		(U(1) << 21)
153 #define TEGRA_CLK_OUT_ENB_V		U(0x360)
154 #define  SE_CLK_ENB_BIT			(U(1) << 31)
155 #define TEGRA_CLK_OUT_ENB_W		U(0x364)
156 #define  ENTROPY_RESET_BIT 		(U(1) << 21)
157 #define TEGRA_CLK_RST_CTL_CLK_SRC_SE	U(0x42C)
158 #define  SE_CLK_SRC_MASK		(U(7) << 29)
159 #define  SE_CLK_SRC_CLK_M		(U(6) << 29)
160 #define TEGRA_RST_DEV_SET_V		U(0x430)
161 #define  SE_RESET_BIT			(U(1) << 31)
162 #define  HDA_RESET_BIT			(U(1) << 29)
163 #define  SATA_RESET_BIT			(U(1) << 28)
164 #define TEGRA_RST_DEV_CLR_V		U(0x434)
165 #define TEGRA_CLK_ENB_V			U(0x440)
166 
167 /*******************************************************************************
168  * Tegra Flow Controller constants
169  ******************************************************************************/
170 #define TEGRA_FLOWCTRL_BASE		U(0x60007000)
171 
172 /*******************************************************************************
173  * Tegra AHB arbitration controller
174  ******************************************************************************/
175 #define TEGRA_AHB_ARB_BASE		0x6000C000UL
176 
177 /*******************************************************************************
178  * Tegra Secure Boot Controller constants
179  ******************************************************************************/
180 #define TEGRA_SB_BASE			U(0x6000C200)
181 
182 /*******************************************************************************
183  * Tegra Exception Vectors constants
184  ******************************************************************************/
185 #define TEGRA_EVP_BASE			U(0x6000F000)
186 
187 /*******************************************************************************
188  * Tegra Miscellaneous register constants
189  ******************************************************************************/
190 #define TEGRA_MISC_BASE			U(0x70000000)
191 #define  HARDWARE_REVISION_OFFSET	U(0x804)
192 #define  APB_SLAVE_SECURITY_ENABLE	U(0xC00)
193 #define  PMC_SECURITY_EN_BIT		(U(1) << 13)
194 #define  PINMUX_AUX_DVFS_PWM		U(0x3184)
195 #define  PINMUX_PWM_TRISTATE		(U(1) << 4)
196 
197 /*******************************************************************************
198  * Tegra UART controller base addresses
199  ******************************************************************************/
200 #define TEGRA_UARTA_BASE		U(0x70006000)
201 #define TEGRA_UARTB_BASE		U(0x70006040)
202 #define TEGRA_UARTC_BASE		U(0x70006200)
203 #define TEGRA_UARTD_BASE		U(0x70006300)
204 #define TEGRA_UARTE_BASE		U(0x70006400)
205 
206 /*******************************************************************************
207  * Tegra Fuse Controller related constants
208  ******************************************************************************/
209 #define TEGRA_FUSE_BASE			0x7000F800UL
210 #define FUSE_BOOT_SECURITY_INFO		0x268UL
211 #define FUSE_ATOMIC_SAVE_CARVEOUT_EN	(0x1U << 7)
212 #define FUSE_JTAG_SECUREID_VALID	(0x104UL)
213 #define ECID_VALID			(0x1UL)
214 
215 
216 /*******************************************************************************
217  * Tegra Power Mgmt Controller constants
218  ******************************************************************************/
219 #define TEGRA_PMC_BASE			U(0x7000E400)
220 #define TEGRA_PMC_SIZE			U(0xC00) /* 3k */
221 
222 /*******************************************************************************
223  * Tegra Atomics constants
224  ******************************************************************************/
225 #define TEGRA_ATOMICS_BASE		0x70016000UL
226 #define  TRIGGER0_REG_OFFSET		0UL
227 #define  TRIGGER_WIDTH_SHIFT		4UL
228 #define  TRIGGER_ID_SHIFT		16UL
229 #define  RESULT0_REG_OFFSET		0xC00UL
230 
231 /*******************************************************************************
232  * Tegra Memory Controller constants
233  ******************************************************************************/
234 #define TEGRA_MC_BASE			U(0x70019000)
235 
236 /* Memory Controller Interrupt Status */
237 #define MC_INTSTATUS			0x00U
238 
239 /* TZDRAM carveout configuration registers */
240 #define MC_SECURITY_CFG0_0		U(0x70)
241 #define MC_SECURITY_CFG1_0		U(0x74)
242 #define MC_SECURITY_CFG3_0		U(0x9BC)
243 
244 /* Video Memory carveout configuration registers */
245 #define MC_VIDEO_PROTECT_BASE_HI	U(0x978)
246 #define MC_VIDEO_PROTECT_BASE_LO	U(0x648)
247 #define MC_VIDEO_PROTECT_SIZE_MB	U(0x64c)
248 #define MC_VIDEO_PROTECT_REG_CTRL	U(0x650)
249 #define MC_VIDEO_PROTECT_WRITE_ACCESS_ENABLED	U(3)
250 
251 /* SMMU configuration registers*/
252 #define MC_SMMU_PPCS_ASID_0		0x270U
253 #define  PPCS_SMMU_ENABLE		(0x1U << 31)
254 
255 /*******************************************************************************
256  * Tegra CLDVFS constants
257  ******************************************************************************/
258 #define TEGRA_CL_DVFS_BASE		U(0x70110000)
259 #define DVFS_DFLL_CTRL			U(0x00)
260 #define  ENABLE_OPEN_LOOP		U(1)
261 #define  ENABLE_CLOSED_LOOP		U(2)
262 #define DVFS_DFLL_OUTPUT_CFG		U(0x20)
263 #define  DFLL_OUTPUT_CFG_I2C_EN_BIT	(U(1) << 30)
264 #define  DFLL_OUTPUT_CFG_CLK_EN_BIT	(U(1) << 6)
265 
266 /*******************************************************************************
267  * Tegra SE constants
268  ******************************************************************************/
269 #define TEGRA_SE1_BASE			U(0x70012000)
270 #define TEGRA_SE2_BASE			U(0x70412000)
271 #define TEGRA_PKA1_BASE			U(0x70420000)
272 #define TEGRA_SE2_RANGE_SIZE		U(0x2000)
273 #define SE_TZRAM_SECURITY		U(0x4)
274 
275 /*******************************************************************************
276  * Tegra TZRAM constants
277  ******************************************************************************/
278 #define TEGRA_TZRAM_BASE		U(0x7C010000)
279 #define TEGRA_TZRAM_SIZE		U(0x10000)
280 
281 /*******************************************************************************
282  * Tegra TZRAM carveout constants
283  ******************************************************************************/
284 #define TEGRA_TZRAM_CARVEOUT_BASE	U(0x7C04C000)
285 #define TEGRA_TZRAM_CARVEOUT_SIZE	U(0x4000)
286 
287 /*******************************************************************************
288  * Tegra DRAM memory base address
289  ******************************************************************************/
290 #define TEGRA_DRAM_BASE			ULL(0x80000000)
291 #define TEGRA_DRAM_END			ULL(0x27FFFFFFF)
292 
293 #endif /* TEGRA_DEF_H */
294