1 /* 2 * linux/mfd/tps65218.h 3 * 4 * Functions to access TPS65219 power management chip. 5 * 6 * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/ 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 13 * kind, whether expressed or implied; without even the implied warranty 14 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License version 2 for more details. 16 */ 17 18 #ifndef __LINUX_MFD_TPS65218_H 19 #define __LINUX_MFD_TPS65218_H 20 21 #include <linux/i2c.h> 22 #include <linux/regulator/driver.h> 23 #include <linux/regulator/machine.h> 24 #include <linux/bitops.h> 25 26 /* TPS chip id list */ 27 #define TPS65218 0xF0 28 29 /* I2C ID for TPS65218 part */ 30 #define TPS65218_I2C_ID 0x24 31 32 /* All register addresses */ 33 #define TPS65218_REG_CHIPID 0x00 34 #define TPS65218_REG_INT1 0x01 35 #define TPS65218_REG_INT2 0x02 36 #define TPS65218_REG_INT_MASK1 0x03 37 #define TPS65218_REG_INT_MASK2 0x04 38 #define TPS65218_REG_STATUS 0x05 39 #define TPS65218_REG_CONTROL 0x06 40 #define TPS65218_REG_FLAG 0x07 41 42 #define TPS65218_REG_PASSWORD 0x10 43 #define TPS65218_REG_ENABLE1 0x11 44 #define TPS65218_REG_ENABLE2 0x12 45 #define TPS65218_REG_CONFIG1 0x13 46 #define TPS65218_REG_CONFIG2 0x14 47 #define TPS65218_REG_CONFIG3 0x15 48 #define TPS65218_REG_CONTROL_DCDC1 0x16 49 #define TPS65218_REG_CONTROL_DCDC2 0x17 50 #define TPS65218_REG_CONTROL_DCDC3 0x18 51 #define TPS65218_REG_CONTROL_DCDC4 0x19 52 #define TPS65218_REG_CONTRL_SLEW_RATE 0x1A 53 #define TPS65218_REG_CONTROL_LDO1 0x1B 54 #define TPS65218_REG_SEQ1 0x20 55 #define TPS65218_REG_SEQ2 0x21 56 #define TPS65218_REG_SEQ3 0x22 57 #define TPS65218_REG_SEQ4 0x23 58 #define TPS65218_REG_SEQ5 0x24 59 #define TPS65218_REG_SEQ6 0x25 60 #define TPS65218_REG_SEQ7 0x26 61 62 /* Register field definitions */ 63 #define TPS65218_CHIPID_CHIP_MASK 0xF8 64 #define TPS65218_CHIPID_REV_MASK 0x07 65 66 #define TPS65218_REV_1_0 0x0 67 #define TPS65218_REV_1_1 0x1 68 #define TPS65218_REV_2_0 0x2 69 #define TPS65218_REV_2_1 0x3 70 71 #define TPS65218_INT1_VPRG BIT(5) 72 #define TPS65218_INT1_AC BIT(4) 73 #define TPS65218_INT1_PB BIT(3) 74 #define TPS65218_INT1_HOT BIT(2) 75 #define TPS65218_INT1_CC_AQC BIT(1) 76 #define TPS65218_INT1_PRGC BIT(0) 77 78 #define TPS65218_INT2_LS3_F BIT(5) 79 #define TPS65218_INT2_LS2_F BIT(4) 80 #define TPS65218_INT2_LS1_F BIT(3) 81 #define TPS65218_INT2_LS3_I BIT(2) 82 #define TPS65218_INT2_LS2_I BIT(1) 83 #define TPS65218_INT2_LS1_I BIT(0) 84 85 #define TPS65218_INT_MASK1_VPRG BIT(5) 86 #define TPS65218_INT_MASK1_AC BIT(4) 87 #define TPS65218_INT_MASK1_PB BIT(3) 88 #define TPS65218_INT_MASK1_HOT BIT(2) 89 #define TPS65218_INT_MASK1_CC_AQC BIT(1) 90 #define TPS65218_INT_MASK1_PRGC BIT(0) 91 92 #define TPS65218_INT_MASK2_LS3_F BIT(5) 93 #define TPS65218_INT_MASK2_LS2_F BIT(4) 94 #define TPS65218_INT_MASK2_LS1_F BIT(3) 95 #define TPS65218_INT_MASK2_LS3_I BIT(2) 96 #define TPS65218_INT_MASK2_LS2_I BIT(1) 97 #define TPS65218_INT_MASK2_LS1_I BIT(0) 98 99 #define TPS65218_STATUS_FSEAL BIT(7) 100 #define TPS65218_STATUS_EE BIT(6) 101 #define TPS65218_STATUS_AC_STATE BIT(5) 102 #define TPS65218_STATUS_PB_STATE BIT(4) 103 #define TPS65218_STATUS_STATE_MASK 0xC 104 #define TPS65218_STATUS_CC_STAT 0x3 105 106 #define TPS65218_CONTROL_OFFNPFO BIT(1) 107 #define TPS65218_CONTROL_CC_AQ BIT(0) 108 109 #define TPS65218_FLAG_GPO3_FLG BIT(7) 110 #define TPS65218_FLAG_GPO2_FLG BIT(6) 111 #define TPS65218_FLAG_GPO1_FLG BIT(5) 112 #define TPS65218_FLAG_LDO1_FLG BIT(4) 113 #define TPS65218_FLAG_DC4_FLG BIT(3) 114 #define TPS65218_FLAG_DC3_FLG BIT(2) 115 #define TPS65218_FLAG_DC2_FLG BIT(1) 116 #define TPS65218_FLAG_DC1_FLG BIT(0) 117 118 #define TPS65218_ENABLE1_DC6_EN BIT(5) 119 #define TPS65218_ENABLE1_DC5_EN BIT(4) 120 #define TPS65218_ENABLE1_DC4_EN BIT(3) 121 #define TPS65218_ENABLE1_DC3_EN BIT(2) 122 #define TPS65218_ENABLE1_DC2_EN BIT(1) 123 #define TPS65218_ENABLE1_DC1_EN BIT(0) 124 125 #define TPS65218_ENABLE2_GPIO3 BIT(6) 126 #define TPS65218_ENABLE2_GPIO2 BIT(5) 127 #define TPS65218_ENABLE2_GPIO1 BIT(4) 128 #define TPS65218_ENABLE2_LS3_EN BIT(3) 129 #define TPS65218_ENABLE2_LS2_EN BIT(2) 130 #define TPS65218_ENABLE2_LS1_EN BIT(1) 131 #define TPS65218_ENABLE2_LDO1_EN BIT(0) 132 133 134 #define TPS65218_CONFIG1_TRST BIT(7) 135 #define TPS65218_CONFIG1_GPO2_BUF BIT(6) 136 #define TPS65218_CONFIG1_IO1_SEL BIT(5) 137 #define TPS65218_CONFIG1_PGDLY_MASK 0x18 138 #define TPS65218_CONFIG1_STRICT BIT(2) 139 #define TPS65218_CONFIG1_UVLO_MASK 0x3 140 #define TPS65218_CONFIG1_UVLO_2750000 0x0 141 #define TPS65218_CONFIG1_UVLO_2950000 0x1 142 #define TPS65218_CONFIG1_UVLO_3250000 0x2 143 #define TPS65218_CONFIG1_UVLO_3350000 0x3 144 145 #define TPS65218_CONFIG2_DC12_RST BIT(7) 146 #define TPS65218_CONFIG2_UVLOHYS BIT(6) 147 #define TPS65218_CONFIG2_LS3ILIM_MASK 0xC 148 #define TPS65218_CONFIG2_LS2ILIM_MASK 0x3 149 150 #define TPS65218_CONFIG3_LS3NPFO BIT(5) 151 #define TPS65218_CONFIG3_LS2NPFO BIT(4) 152 #define TPS65218_CONFIG3_LS1NPFO BIT(3) 153 #define TPS65218_CONFIG3_LS3DCHRG BIT(2) 154 #define TPS65218_CONFIG3_LS2DCHRG BIT(1) 155 #define TPS65218_CONFIG3_LS1DCHRG BIT(0) 156 157 #define TPS65218_CONTROL_DCDC1_PFM BIT(7) 158 #define TPS65218_CONTROL_DCDC1_MASK 0x7F 159 160 #define TPS65218_CONTROL_DCDC2_PFM BIT(7) 161 #define TPS65218_CONTROL_DCDC2_MASK 0x3F 162 163 #define TPS65218_CONTROL_DCDC3_PFM BIT(7) 164 #define TPS65218_CONTROL_DCDC3_MASK 0x3F 165 166 #define TPS65218_CONTROL_DCDC4_PFM BIT(7) 167 #define TPS65218_CONTROL_DCDC4_MASK 0x3F 168 169 #define TPS65218_SLEW_RATE_GO BIT(7) 170 #define TPS65218_SLEW_RATE_GODSBL BIT(6) 171 #define TPS65218_SLEW_RATE_SLEW_MASK 0x7 172 173 #define TPS65218_CONTROL_LDO1_MASK 0x3F 174 175 #define TPS65218_SEQ1_DLY8 BIT(7) 176 #define TPS65218_SEQ1_DLY7 BIT(6) 177 #define TPS65218_SEQ1_DLY6 BIT(5) 178 #define TPS65218_SEQ1_DLY5 BIT(4) 179 #define TPS65218_SEQ1_DLY4 BIT(3) 180 #define TPS65218_SEQ1_DLY3 BIT(2) 181 #define TPS65218_SEQ1_DLY2 BIT(1) 182 #define TPS65218_SEQ1_DLY1 BIT(0) 183 184 #define TPS65218_SEQ2_DLYFCTR BIT(7) 185 #define TPS65218_SEQ2_DLY9 BIT(0) 186 187 #define TPS65218_SEQ3_DC2_SEQ_MASK 0xF0 188 #define TPS65218_SEQ3_DC1_SEQ_MASK 0xF 189 190 #define TPS65218_SEQ4_DC4_SEQ_MASK 0xF0 191 #define TPS65218_SEQ4_DC3_SEQ_MASK 0xF 192 193 #define TPS65218_SEQ5_DC6_SEQ_MASK 0xF0 194 #define TPS65218_SEQ5_DC5_SEQ_MASK 0xF 195 196 #define TPS65218_SEQ6_LS1_SEQ_MASK 0xF0 197 #define TPS65218_SEQ6_LDO1_SEQ_MASK 0xF 198 199 #define TPS65218_SEQ7_GPO3_SEQ_MASK 0xF0 200 #define TPS65218_SEQ7_GPO1_SEQ_MASK 0xF 201 #define TPS65218_PROTECT_NONE 0 202 #define TPS65218_PROTECT_L1 1 203 204 enum tps65218_regulator_id { 205 /* DCDC's */ 206 TPS65218_DCDC_1, 207 TPS65218_DCDC_2, 208 TPS65218_DCDC_3, 209 TPS65218_DCDC_4, 210 TPS65218_DCDC_5, 211 TPS65218_DCDC_6, 212 /* LDOs */ 213 TPS65218_LDO_1, 214 /* LS's */ 215 TPS65218_LS_2, 216 TPS65218_LS_3, 217 }; 218 219 #define TPS65218_MAX_REG_ID TPS65218_LDO_1 220 221 /* Number of step-down converters available */ 222 #define TPS65218_NUM_DCDC 6 223 /* Number of LDO voltage regulators available */ 224 #define TPS65218_NUM_LDO 1 225 /* Number of total LS current regulators available */ 226 #define TPS65218_NUM_LS 2 227 /* Number of total regulators available */ 228 #define TPS65218_NUM_REGULATOR (TPS65218_NUM_DCDC + TPS65218_NUM_LDO \ 229 + TPS65218_NUM_LS) 230 231 /* Define the TPS65218 IRQ numbers */ 232 enum tps65218_irqs { 233 /* INT1 registers */ 234 TPS65218_PRGC_IRQ, 235 TPS65218_CC_AQC_IRQ, 236 TPS65218_HOT_IRQ, 237 TPS65218_PB_IRQ, 238 TPS65218_AC_IRQ, 239 TPS65218_VPRG_IRQ, 240 TPS65218_INVALID1_IRQ, 241 TPS65218_INVALID2_IRQ, 242 /* INT2 registers */ 243 TPS65218_LS1_I_IRQ, 244 TPS65218_LS2_I_IRQ, 245 TPS65218_LS3_I_IRQ, 246 TPS65218_LS1_F_IRQ, 247 TPS65218_LS2_F_IRQ, 248 TPS65218_LS3_F_IRQ, 249 TPS65218_INVALID3_IRQ, 250 TPS65218_INVALID4_IRQ, 251 }; 252 253 /** 254 * struct tps65218 - tps65218 sub-driver chip access routines 255 * 256 * Device data may be used to access the TPS65218 chip 257 */ 258 259 struct tps65218 { 260 struct device *dev; 261 unsigned int id; 262 u8 rev; 263 264 struct mutex tps_lock; /* lock guarding the data structure */ 265 /* IRQ Data */ 266 int irq; 267 u32 irq_mask; 268 struct regmap_irq_chip_data *irq_data; 269 struct regulator_desc desc[TPS65218_NUM_REGULATOR]; 270 struct regmap *regmap; 271 u8 *strobes; 272 }; 273 274 int tps65218_reg_write(struct tps65218 *tps, unsigned int reg, 275 unsigned int val, unsigned int level); 276 int tps65218_set_bits(struct tps65218 *tps, unsigned int reg, 277 unsigned int mask, unsigned int val, unsigned int level); 278 int tps65218_clear_bits(struct tps65218 *tps, unsigned int reg, 279 unsigned int mask, unsigned int level); 280 281 #endif /* __LINUX_MFD_TPS65218_H */ 282