1 /*
2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <stdint.h>
8 #include <string.h>
9
10 #include <platform_def.h>
11
12 #include <common/debug.h>
13 #include <lib/mmio.h>
14
15 #include <ddr_rk3368.h>
16 #include <pmu.h>
17 #include <rk3368_def.h>
18 #include <soc.h>
19
20 /* GRF_SOC_STATUS0 */
21 #define DPLL_LOCK (0x1 << 2)
22
23 /* GRF_DDRC0_CON0 */
24 #define GRF_DDR_16BIT_EN (((0x1 << 3) << 16) | (0x1 << 3))
25 #define GRF_DDR_32BIT_EN (((0x1 << 3) << 16) | (0x0 << 3))
26 #define GRF_MOBILE_DDR_EN (((0x1 << 4) << 16) | (0x1 << 4))
27 #define GRF_MOBILE_DDR_DISB (((0x1 << 4) << 16) | (0x0 << 4))
28 #define GRF_DDR3_EN (((0x1 << 2) << 16) | (0x1 << 2))
29 #define GRF_LPDDR2_3_EN (((0x1 << 2) << 16) | (0x0 << 2))
30
31 /* PMUGRF_SOC_CON0 */
32 #define ddrphy_bufferen_io_en(n) ((0x1 << (9 + 16)) | (n << 9))
33 #define ddrphy_bufferen_core_en(n) ((0x1 << (8 + 16)) | (n << 8))
34
35 struct PCTRL_TIMING_TAG {
36 uint32_t ddrfreq;
37 uint32_t TOGCNT1U;
38 uint32_t TINIT;
39 uint32_t TRSTH;
40 uint32_t TOGCNT100N;
41 uint32_t TREFI;
42 uint32_t TMRD;
43 uint32_t TRFC;
44 uint32_t TRP;
45 uint32_t TRTW;
46 uint32_t TAL;
47 uint32_t TCL;
48 uint32_t TCWL;
49 uint32_t TRAS;
50 uint32_t TRC;
51 uint32_t TRCD;
52 uint32_t TRRD;
53 uint32_t TRTP;
54 uint32_t TWR;
55 uint32_t TWTR;
56 uint32_t TEXSR;
57 uint32_t TXP;
58 uint32_t TXPDLL;
59 uint32_t TZQCS;
60 uint32_t TZQCSI;
61 uint32_t TDQS;
62 uint32_t TCKSRE;
63 uint32_t TCKSRX;
64 uint32_t TCKE;
65 uint32_t TMOD;
66 uint32_t TRSTL;
67 uint32_t TZQCL;
68 uint32_t TMRR;
69 uint32_t TCKESR;
70 uint32_t TDPD;
71 uint32_t TREFI_MEM_DDR3;
72 };
73
74 struct MSCH_SAVE_REG_TAG {
75 uint32_t ddrconf;
76 uint32_t ddrtiming;
77 uint32_t ddrmode;
78 uint32_t readlatency;
79 uint32_t activate;
80 uint32_t devtodev;
81 };
82
83 /* ddr suspend need save reg */
84 struct PCTL_SAVE_REG_TAG {
85 uint32_t SCFG;
86 uint32_t CMDTSTATEN;
87 uint32_t MCFG1;
88 uint32_t MCFG;
89 uint32_t PPCFG;
90 struct PCTRL_TIMING_TAG pctl_timing;
91 /* DFI Control Registers */
92 uint32_t DFITCTRLDELAY;
93 uint32_t DFIODTCFG;
94 uint32_t DFIODTCFG1;
95 uint32_t DFIODTRANKMAP;
96 /* DFI Write Data Registers */
97 uint32_t DFITPHYWRDATA;
98 uint32_t DFITPHYWRLAT;
99 uint32_t DFITPHYWRDATALAT;
100 /* DFI Read Data Registers */
101 uint32_t DFITRDDATAEN;
102 uint32_t DFITPHYRDLAT;
103 /* DFI Update Registers */
104 uint32_t DFITPHYUPDTYPE0;
105 uint32_t DFITPHYUPDTYPE1;
106 uint32_t DFITPHYUPDTYPE2;
107 uint32_t DFITPHYUPDTYPE3;
108 uint32_t DFITCTRLUPDMIN;
109 uint32_t DFITCTRLUPDMAX;
110 uint32_t DFITCTRLUPDDLY;
111 uint32_t DFIUPDCFG;
112 uint32_t DFITREFMSKI;
113 uint32_t DFITCTRLUPDI;
114 /* DFI Status Registers */
115 uint32_t DFISTCFG0;
116 uint32_t DFISTCFG1;
117 uint32_t DFITDRAMCLKEN;
118 uint32_t DFITDRAMCLKDIS;
119 uint32_t DFISTCFG2;
120 /* DFI Low Power Register */
121 uint32_t DFILPCFG0;
122 };
123
124 struct DDRPHY_SAVE_REG_TAG {
125 uint32_t PHY_REG0;
126 uint32_t PHY_REG1;
127 uint32_t PHY_REGB;
128 uint32_t PHY_REGC;
129 uint32_t PHY_REG11;
130 uint32_t PHY_REG13;
131 uint32_t PHY_REG14;
132 uint32_t PHY_REG16;
133 uint32_t PHY_REG20;
134 uint32_t PHY_REG21;
135 uint32_t PHY_REG26;
136 uint32_t PHY_REG27;
137 uint32_t PHY_REG28;
138 uint32_t PHY_REG30;
139 uint32_t PHY_REG31;
140 uint32_t PHY_REG36;
141 uint32_t PHY_REG37;
142 uint32_t PHY_REG38;
143 uint32_t PHY_REG40;
144 uint32_t PHY_REG41;
145 uint32_t PHY_REG46;
146 uint32_t PHY_REG47;
147 uint32_t PHY_REG48;
148 uint32_t PHY_REG50;
149 uint32_t PHY_REG51;
150 uint32_t PHY_REG56;
151 uint32_t PHY_REG57;
152 uint32_t PHY_REG58;
153 uint32_t PHY_REGDLL;
154 uint32_t PHY_REGEC;
155 uint32_t PHY_REGED;
156 uint32_t PHY_REGEE;
157 uint32_t PHY_REGEF;
158 uint32_t PHY_REGFB;
159 uint32_t PHY_REGFC;
160 uint32_t PHY_REGFD;
161 uint32_t PHY_REGFE;
162 };
163
164 struct BACKUP_REG_TAG {
165 uint32_t tag;
166 uint32_t pctladdr;
167 struct PCTL_SAVE_REG_TAG pctl;
168 uint32_t phyaddr;
169 struct DDRPHY_SAVE_REG_TAG phy;
170 uint32_t nocaddr;
171 struct MSCH_SAVE_REG_TAG noc;
172 uint32_t pllselect;
173 uint32_t phypllockaddr;
174 uint32_t phyplllockmask;
175 uint32_t phyplllockval;
176 uint32_t pllpdstat;
177 uint32_t dpllmodeaddr;
178 uint32_t dpllslowmode;
179 uint32_t dpllnormalmode;
180 uint32_t dpllresetaddr;
181 uint32_t dpllreset;
182 uint32_t dplldereset;
183 uint32_t dpllconaddr;
184 uint32_t dpllcon[4];
185 uint32_t dplllockaddr;
186 uint32_t dplllockmask;
187 uint32_t dplllockval;
188 uint32_t ddrpllsrcdivaddr;
189 uint32_t ddrpllsrcdiv;
190 uint32_t retendisaddr;
191 uint32_t retendisval;
192 uint32_t grfregaddr;
193 uint32_t grfddrcreg;
194 uint32_t crupctlphysoftrstaddr;
195 uint32_t cruresetpctlphy;
196 uint32_t cruderesetphy;
197 uint32_t cruderesetpctlphy;
198 uint32_t physoftrstaddr;
199 uint32_t endtag;
200 };
201
ddr_get_phy_pll_freq(void)202 static uint32_t ddr_get_phy_pll_freq(void)
203 {
204 uint32_t ret = 0;
205 uint32_t fb_div, pre_div;
206
207 fb_div = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGEC);
208 fb_div |= (mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGED) & 0x1) << 8;
209
210 pre_div = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGEE) & 0xff;
211 ret = 2 * 24 * fb_div / (4 * pre_div);
212
213 return ret;
214 }
215
ddr_copy(uint32_t * pdest,uint32_t * psrc,uint32_t words)216 static void ddr_copy(uint32_t *pdest, uint32_t *psrc, uint32_t words)
217 {
218 uint32_t i;
219
220 for (i = 0; i < words; i++)
221 pdest[i] = psrc[i];
222 }
223
ddr_get_dpll_cfg(uint32_t * p)224 static void ddr_get_dpll_cfg(uint32_t *p)
225 {
226 uint32_t nmhz, NO, NF, NR;
227
228 nmhz = ddr_get_phy_pll_freq();
229 if (nmhz <= 150)
230 NO = 6;
231 else if (nmhz <= 250)
232 NO = 4;
233 else if (nmhz <= 500)
234 NO = 2;
235 else
236 NO = 1;
237
238 NR = 1;
239 NF = 2 * nmhz * NR * NO / 24;
240
241 p[0] = SET_NR(NR) | SET_NO(NO);
242 p[1] = SET_NF(NF);
243 p[2] = SET_NB(NF / 2);
244 }
245
ddr_reg_save(uint32_t pllpdstat,uint64_t base_addr)246 void ddr_reg_save(uint32_t pllpdstat, uint64_t base_addr)
247 {
248 struct BACKUP_REG_TAG *p_ddr_reg = (struct BACKUP_REG_TAG *)base_addr;
249 struct PCTL_SAVE_REG_TAG *pctl_tim = &p_ddr_reg->pctl;
250
251 p_ddr_reg->tag = 0x56313031;
252 p_ddr_reg->pctladdr = DDR_PCTL_BASE;
253 p_ddr_reg->phyaddr = DDR_PHY_BASE;
254 p_ddr_reg->nocaddr = SERVICE_BUS_BASE;
255
256 /* PCTLR */
257 ddr_copy((uint32_t *)&pctl_tim->pctl_timing.TOGCNT1U,
258 (uint32_t *)(DDR_PCTL_BASE + DDR_PCTL_TOGCNT1U), 35);
259 pctl_tim->pctl_timing.TREFI |= DDR_UPD_REF_ENABLE;
260 pctl_tim->SCFG = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_SCFG);
261 pctl_tim->CMDTSTATEN = mmio_read_32(DDR_PCTL_BASE +
262 DDR_PCTL_CMDTSTATEN);
263 pctl_tim->MCFG1 = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_MCFG1);
264 pctl_tim->MCFG = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_MCFG);
265 pctl_tim->PPCFG = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_PPCFG);
266 pctl_tim->pctl_timing.ddrfreq = mmio_read_32(DDR_PCTL_BASE +
267 DDR_PCTL_TOGCNT1U * 2);
268 pctl_tim->DFITCTRLDELAY = mmio_read_32(DDR_PCTL_BASE +
269 DDR_PCTL_DFITCTRLDELAY);
270 pctl_tim->DFIODTCFG = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_DFIODTCFG);
271 pctl_tim->DFIODTCFG1 = mmio_read_32(DDR_PCTL_BASE +
272 DDR_PCTL_DFIODTCFG1);
273 pctl_tim->DFIODTRANKMAP = mmio_read_32(DDR_PCTL_BASE +
274 DDR_PCTL_DFIODTRANKMAP);
275 pctl_tim->DFITPHYWRDATA = mmio_read_32(DDR_PCTL_BASE +
276 DDR_PCTL_DFITPHYWRDATA);
277 pctl_tim->DFITPHYWRLAT = mmio_read_32(DDR_PCTL_BASE +
278 DDR_PCTL_DFITPHYWRLAT);
279 pctl_tim->DFITPHYWRDATALAT = mmio_read_32(DDR_PCTL_BASE +
280 DDR_PCTL_DFITPHYWRDATALAT);
281 pctl_tim->DFITRDDATAEN = mmio_read_32(DDR_PCTL_BASE +
282 DDR_PCTL_DFITRDDATAEN);
283 pctl_tim->DFITPHYRDLAT = mmio_read_32(DDR_PCTL_BASE +
284 DDR_PCTL_DFITPHYRDLAT);
285 pctl_tim->DFITPHYUPDTYPE0 = mmio_read_32(DDR_PCTL_BASE +
286 DDR_PCTL_DFITPHYUPDTYPE0);
287 pctl_tim->DFITPHYUPDTYPE1 = mmio_read_32(DDR_PCTL_BASE +
288 DDR_PCTL_DFITPHYUPDTYPE1);
289 pctl_tim->DFITPHYUPDTYPE2 = mmio_read_32(DDR_PCTL_BASE +
290 DDR_PCTL_DFITPHYUPDTYPE2);
291 pctl_tim->DFITPHYUPDTYPE3 = mmio_read_32(DDR_PCTL_BASE +
292 DDR_PCTL_DFITPHYUPDTYPE3);
293 pctl_tim->DFITCTRLUPDMIN = mmio_read_32(DDR_PCTL_BASE +
294 DDR_PCTL_DFITCTRLUPDMIN);
295 pctl_tim->DFITCTRLUPDMAX = mmio_read_32(DDR_PCTL_BASE +
296 DDR_PCTL_DFITCTRLUPDMAX);
297 pctl_tim->DFITCTRLUPDDLY = mmio_read_32(DDR_PCTL_BASE +
298 DDR_PCTL_DFITCTRLUPDDLY);
299
300 pctl_tim->DFIUPDCFG = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_DFIUPDCFG);
301 pctl_tim->DFITREFMSKI = mmio_read_32(DDR_PCTL_BASE +
302 DDR_PCTL_DFITREFMSKI);
303 pctl_tim->DFITCTRLUPDI = mmio_read_32(DDR_PCTL_BASE +
304 DDR_PCTL_DFITCTRLUPDI);
305 pctl_tim->DFISTCFG0 = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_DFISTCFG0);
306 pctl_tim->DFISTCFG1 = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_DFISTCFG1);
307 pctl_tim->DFITDRAMCLKEN = mmio_read_32(DDR_PCTL_BASE +
308 DDR_PCTL_DFITDRAMCLKEN);
309 pctl_tim->DFITDRAMCLKDIS = mmio_read_32(DDR_PCTL_BASE +
310 DDR_PCTL_DFITDRAMCLKDIS);
311 pctl_tim->DFISTCFG2 = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_DFISTCFG2);
312 pctl_tim->DFILPCFG0 = mmio_read_32(DDR_PCTL_BASE + DDR_PCTL_DFILPCFG0);
313
314 /* PHY */
315 p_ddr_reg->phy.PHY_REG0 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG0);
316 p_ddr_reg->phy.PHY_REG1 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG1);
317 p_ddr_reg->phy.PHY_REGB = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGB);
318 p_ddr_reg->phy.PHY_REGC = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGC);
319 p_ddr_reg->phy.PHY_REG11 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG11);
320 p_ddr_reg->phy.PHY_REG13 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG13);
321 p_ddr_reg->phy.PHY_REG14 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG14);
322 p_ddr_reg->phy.PHY_REG16 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG16);
323 p_ddr_reg->phy.PHY_REG20 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG20);
324 p_ddr_reg->phy.PHY_REG21 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG21);
325 p_ddr_reg->phy.PHY_REG26 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG26);
326 p_ddr_reg->phy.PHY_REG27 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG27);
327 p_ddr_reg->phy.PHY_REG28 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG28);
328 p_ddr_reg->phy.PHY_REG30 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG30);
329 p_ddr_reg->phy.PHY_REG31 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG31);
330 p_ddr_reg->phy.PHY_REG36 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG36);
331 p_ddr_reg->phy.PHY_REG37 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG37);
332 p_ddr_reg->phy.PHY_REG38 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG38);
333 p_ddr_reg->phy.PHY_REG40 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG40);
334 p_ddr_reg->phy.PHY_REG41 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG41);
335 p_ddr_reg->phy.PHY_REG46 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG46);
336 p_ddr_reg->phy.PHY_REG47 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG47);
337 p_ddr_reg->phy.PHY_REG48 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG48);
338 p_ddr_reg->phy.PHY_REG50 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG50);
339 p_ddr_reg->phy.PHY_REG51 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG51);
340 p_ddr_reg->phy.PHY_REG56 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG56);
341 p_ddr_reg->phy.PHY_REG57 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG57);
342 p_ddr_reg->phy.PHY_REG58 = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG58);
343 p_ddr_reg->phy.PHY_REGDLL = mmio_read_32(DDR_PHY_BASE +
344 DDR_PHY_REGDLL);
345 p_ddr_reg->phy.PHY_REGEC = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGEC);
346 p_ddr_reg->phy.PHY_REGED = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGED);
347 p_ddr_reg->phy.PHY_REGEE = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGEE);
348 p_ddr_reg->phy.PHY_REGEF = 0;
349
350 if (mmio_read_32(DDR_PHY_BASE + DDR_PHY_REG2) & 0x2) {
351 p_ddr_reg->phy.PHY_REGFB = mmio_read_32(DDR_PHY_BASE +
352 DDR_PHY_REG2C);
353 p_ddr_reg->phy.PHY_REGFC = mmio_read_32(DDR_PHY_BASE +
354 DDR_PHY_REG3C);
355 p_ddr_reg->phy.PHY_REGFD = mmio_read_32(DDR_PHY_BASE +
356 DDR_PHY_REG4C);
357 p_ddr_reg->phy.PHY_REGFE = mmio_read_32(DDR_PHY_BASE +
358 DDR_PHY_REG5C);
359 } else {
360 p_ddr_reg->phy.PHY_REGFB = mmio_read_32(DDR_PHY_BASE +
361 DDR_PHY_REGFB);
362 p_ddr_reg->phy.PHY_REGFC = mmio_read_32(DDR_PHY_BASE +
363 DDR_PHY_REGFC);
364 p_ddr_reg->phy.PHY_REGFD = mmio_read_32(DDR_PHY_BASE +
365 DDR_PHY_REGFD);
366 p_ddr_reg->phy.PHY_REGFE = mmio_read_32(DDR_PHY_BASE +
367 DDR_PHY_REGFE);
368 }
369
370 /* NOC */
371 p_ddr_reg->noc.ddrconf = mmio_read_32(SERVICE_BUS_BASE + MSCH_DDRCONF);
372 p_ddr_reg->noc.ddrtiming = mmio_read_32(SERVICE_BUS_BASE +
373 MSCH_DDRTIMING);
374 p_ddr_reg->noc.ddrmode = mmio_read_32(SERVICE_BUS_BASE + MSCH_DDRMODE);
375 p_ddr_reg->noc.readlatency = mmio_read_32(SERVICE_BUS_BASE +
376 MSCH_READLATENCY);
377 p_ddr_reg->noc.activate = mmio_read_32(SERVICE_BUS_BASE +
378 MSCH_ACTIVATE);
379 p_ddr_reg->noc.devtodev = mmio_read_32(SERVICE_BUS_BASE +
380 MSCH_DEVTODEV);
381
382 p_ddr_reg->pllselect = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGEE) * 0x1;
383 p_ddr_reg->phypllockaddr = GRF_BASE + GRF_SOC_STATUS0;
384 p_ddr_reg->phyplllockmask = GRF_DDRPHY_LOCK;
385 p_ddr_reg->phyplllockval = 0;
386
387 /* PLLPD */
388 p_ddr_reg->pllpdstat = pllpdstat;
389 /* DPLL */
390 p_ddr_reg->dpllmodeaddr = CRU_BASE + PLL_CONS(DPLL_ID, 3);
391 /* slow mode and power on */
392 p_ddr_reg->dpllslowmode = DPLL_WORK_SLOW_MODE | DPLL_POWER_DOWN;
393 p_ddr_reg->dpllnormalmode = DPLL_WORK_NORMAL_MODE;
394 p_ddr_reg->dpllresetaddr = CRU_BASE + PLL_CONS(DPLL_ID, 3);
395 p_ddr_reg->dpllreset = DPLL_RESET_CONTROL_NORMAL;
396 p_ddr_reg->dplldereset = DPLL_RESET_CONTROL_RESET;
397 p_ddr_reg->dpllconaddr = CRU_BASE + PLL_CONS(DPLL_ID, 0);
398
399 if (p_ddr_reg->pllselect == 0) {
400 p_ddr_reg->dpllcon[0] = (mmio_read_32(CRU_BASE +
401 PLL_CONS(DPLL_ID, 0))
402 & 0xffff) |
403 (0xFFFFu << 16);
404 p_ddr_reg->dpllcon[1] = (mmio_read_32(CRU_BASE +
405 PLL_CONS(DPLL_ID, 1))
406 & 0xffff);
407 p_ddr_reg->dpllcon[2] = (mmio_read_32(CRU_BASE +
408 PLL_CONS(DPLL_ID, 2))
409 & 0xffff);
410 p_ddr_reg->dpllcon[3] = (mmio_read_32(CRU_BASE +
411 PLL_CONS(DPLL_ID, 3))
412 & 0xffff) |
413 (0xFFFFu << 16);
414 } else {
415 ddr_get_dpll_cfg(&p_ddr_reg->dpllcon[0]);
416 }
417
418 p_ddr_reg->pllselect = 0;
419 p_ddr_reg->dplllockaddr = CRU_BASE + PLL_CONS(DPLL_ID, 1);
420 p_ddr_reg->dplllockmask = DPLL_STATUS_LOCK;
421 p_ddr_reg->dplllockval = DPLL_STATUS_LOCK;
422
423 /* SET_DDR_PLL_SRC */
424 p_ddr_reg->ddrpllsrcdivaddr = CRU_BASE + CRU_CLKSELS_CON(13);
425 p_ddr_reg->ddrpllsrcdiv = (mmio_read_32(CRU_BASE + CRU_CLKSELS_CON(13))
426 & DDR_PLL_SRC_MASK)
427 | (DDR_PLL_SRC_MASK << 16);
428 p_ddr_reg->retendisaddr = PMU_BASE + PMU_PWRMD_COM;
429 p_ddr_reg->retendisval = PD_PERI_PWRDN_ENABLE;
430 p_ddr_reg->grfregaddr = GRF_BASE + GRF_DDRC0_CON0;
431 p_ddr_reg->grfddrcreg = (mmio_read_32(GRF_BASE + GRF_DDRC0_CON0) &
432 DDR_PLL_SRC_MASK) |
433 (DDR_PLL_SRC_MASK << 16);
434
435 /* pctl phy soft reset */
436 p_ddr_reg->crupctlphysoftrstaddr = CRU_BASE + CRU_SOFTRSTS_CON(10);
437 p_ddr_reg->cruresetpctlphy = DDRCTRL0_PSRSTN_REQ(1) |
438 DDRCTRL0_SRSTN_REQ(1) |
439 DDRPHY0_PSRSTN_REQ(1) |
440 DDRPHY0_SRSTN_REQ(1);
441 p_ddr_reg->cruderesetphy = DDRCTRL0_PSRSTN_REQ(1) |
442 DDRCTRL0_SRSTN_REQ(1) |
443 DDRPHY0_PSRSTN_REQ(0) |
444 DDRPHY0_SRSTN_REQ(0);
445
446 p_ddr_reg->cruderesetpctlphy = DDRCTRL0_PSRSTN_REQ(0) |
447 DDRCTRL0_SRSTN_REQ(0) |
448 DDRPHY0_PSRSTN_REQ(0) |
449 DDRPHY0_SRSTN_REQ(0);
450
451 p_ddr_reg->physoftrstaddr = DDR_PHY_BASE + DDR_PHY_REG0;
452
453 p_ddr_reg->endtag = 0xFFFFFFFF;
454 }
455
456 /*
457 * "rk3368_ddr_reg_resume_V1.05.bin" is an executable bin which is generated
458 * by ARM DS5 for resuming ddr controller. If the soc wakes up from system
459 * suspend, ddr needs to be resumed and the resuming code needs to be run in
460 * sram. But there is not a way to pointing the resuming code to the PMUSRAM
461 * when linking .o files of bl31, so we use the
462 * "rk3368_ddr_reg_resume_V1.05.bin" whose code is position-independent and
463 * it can be loaded anywhere and run.
464 */
465 static __aligned(4) unsigned int ddr_reg_resume[] = {
466 #include "rk3368_ddr_reg_resume_V1.05.bin"
467 };
468
ddr_get_resume_code_size(void)469 uint32_t ddr_get_resume_code_size(void)
470 {
471 return sizeof(ddr_reg_resume);
472 }
473
ddr_get_resume_data_size(void)474 uint32_t ddr_get_resume_data_size(void)
475 {
476 return sizeof(struct BACKUP_REG_TAG);
477 }
478
ddr_get_resume_code_base(void)479 uint32_t *ddr_get_resume_code_base(void)
480 {
481 return (unsigned int *)ddr_reg_resume;
482 }
483