1 /* 2 * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef TZC_COMMON_H 8 #define TZC_COMMON_H 9 10 #include <lib/utils_def.h> 11 12 /* 13 * Offset of core registers from the start of the base of configuration 14 * registers for each region. 15 */ 16 17 /* ID Registers */ 18 #define PID0_OFF U(0xfe0) 19 #define PID1_OFF U(0xfe4) 20 #define PID2_OFF U(0xfe8) 21 #define PID3_OFF U(0xfec) 22 #define PID4_OFF U(0xfd0) 23 #define CID0_OFF U(0xff0) 24 #define CID1_OFF U(0xff4) 25 #define CID2_OFF U(0xff8) 26 #define CID3_OFF U(0xffc) 27 28 /* 29 * What type of action is expected when an access violation occurs. 30 * The memory requested is returned as zero. But we can also raise an event to 31 * let the system know it happened. 32 * We can raise an interrupt(INT) and/or cause an exception(ERR). 33 * TZC_ACTION_NONE - No interrupt, no Exception 34 * TZC_ACTION_ERR - No interrupt, raise exception -> sync external 35 * data abort 36 * TZC_ACTION_INT - Raise interrupt, no exception 37 * TZC_ACTION_ERR_INT - Raise interrupt, raise exception -> sync 38 * external data abort 39 */ 40 #define TZC_ACTION_NONE U(0) 41 #define TZC_ACTION_ERR U(1) 42 #define TZC_ACTION_INT U(2) 43 #define TZC_ACTION_ERR_INT (TZC_ACTION_ERR | TZC_ACTION_INT) 44 45 /* Bit positions of TZC_ACTION registers */ 46 #define TZC_ACTION_RV_SHIFT 0 47 #define TZC_ACTION_RV_MASK U(0x3) 48 #define TZC_ACTION_RV_LOWOK U(0x0) 49 #define TZC_ACTION_RV_LOWERR U(0x1) 50 #define TZC_ACTION_RV_HIGHOK U(0x2) 51 #define TZC_ACTION_RV_HIGHERR U(0x3) 52 53 /* 54 * Controls secure access to a region. If not enabled secure access is not 55 * allowed to region. 56 */ 57 #define TZC_REGION_S_NONE U(0) 58 #define TZC_REGION_S_RD U(1) 59 #define TZC_REGION_S_WR U(2) 60 #define TZC_REGION_S_RDWR (TZC_REGION_S_RD | TZC_REGION_S_WR) 61 62 #define TZC_REGION_ATTR_S_RD_SHIFT 30 63 #define TZC_REGION_ATTR_S_WR_SHIFT 31 64 #define TZC_REGION_ATTR_F_EN_SHIFT 0 65 #define TZC_REGION_ATTR_SEC_SHIFT 30 66 #define TZC_REGION_ATTR_S_RD_MASK U(0x1) 67 #define TZC_REGION_ATTR_S_WR_MASK U(0x1) 68 #define TZC_REGION_ATTR_SEC_MASK U(0x3) 69 70 #define TZC_REGION_ACCESS_WR_EN_SHIFT 16 71 #define TZC_REGION_ACCESS_RD_EN_SHIFT 0 72 #define TZC_REGION_ACCESS_ID_MASK U(0xf) 73 74 /* Macros for allowing Non-Secure access to a region based on NSAID */ 75 #define TZC_REGION_ACCESS_RD(nsaid) \ 76 ((U(1) << ((nsaid) & TZC_REGION_ACCESS_ID_MASK)) << \ 77 TZC_REGION_ACCESS_RD_EN_SHIFT) 78 #define TZC_REGION_ACCESS_WR(nsaid) \ 79 ((U(1) << ((nsaid) & TZC_REGION_ACCESS_ID_MASK)) << \ 80 TZC_REGION_ACCESS_WR_EN_SHIFT) 81 #define TZC_REGION_ACCESS_RDWR(nsaid) \ 82 (TZC_REGION_ACCESS_RD(nsaid) | \ 83 TZC_REGION_ACCESS_WR(nsaid)) 84 85 /* Returns offset of registers to program for a given region no */ 86 #define TZC_REGION_OFFSET(region_size, region_no) \ 87 ((region_size) * (region_no)) 88 89 #endif /* TZC_COMMON_H */ 90