1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2010-2015
4 * NVIDIA Corporation <www.nvidia.com>
5 */
6
7 #include <common.h>
8 #include <cpu_func.h>
9 #include <dm.h>
10 #include <init.h>
11 #include <log.h>
12 #include <ns16550.h>
13 #include <spl.h>
14 #include <asm/cache.h>
15 #include <asm/global_data.h>
16 #include <asm/io.h>
17 #if IS_ENABLED(CONFIG_TEGRA_CLKRST)
18 #include <asm/arch/clock.h>
19 #endif
20 #if IS_ENABLED(CONFIG_TEGRA_PINCTRL)
21 #include <asm/arch/funcmux.h>
22 #endif
23 #if IS_ENABLED(CONFIG_TEGRA_MC)
24 #include <asm/arch/mc.h>
25 #endif
26 #include <asm/arch/tegra.h>
27 #include <asm/arch-tegra/ap.h>
28 #include <asm/arch-tegra/board.h>
29 #include <asm/arch-tegra/cboot.h>
30 #include <asm/arch-tegra/pmc.h>
31 #include <asm/arch-tegra/sys_proto.h>
32 #include <asm/arch-tegra/warmboot.h>
33
34 void save_boot_params_ret(void);
35
36 DECLARE_GLOBAL_DATA_PTR;
37
38 enum {
39 /* UARTs which we can enable */
40 UARTA = 1 << 0,
41 UARTB = 1 << 1,
42 UARTC = 1 << 2,
43 UARTD = 1 << 3,
44 UARTE = 1 << 4,
45 UART_COUNT = 5,
46 };
47
48 static bool from_spl __attribute__ ((section(".data")));
49
50 #ifndef CONFIG_SPL_BUILD
save_boot_params(unsigned long r0,unsigned long r1,unsigned long r2,unsigned long r3)51 void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2,
52 unsigned long r3)
53 {
54 from_spl = r0 != UBOOT_NOT_LOADED_FROM_SPL;
55
56 /*
57 * The logic for this is somewhat indirect. The purpose of the marker
58 * (UBOOT_NOT_LOADED_FROM_SPL) is in fact used to determine if U-Boot
59 * was loaded from a read-only instance of itself, which is something
60 * that can happen in secure boot setups. So basically the presence
61 * of the marker is an indication that U-Boot was loaded by one such
62 * special variant of U-Boot. Conversely, the absence of the marker
63 * indicates that this instance of U-Boot was loaded by something
64 * other than a special U-Boot. This could be SPL, but it could just
65 * as well be one of any number of other first stage bootloaders.
66 */
67 if (from_spl)
68 cboot_save_boot_params(r0, r1, r2, r3);
69
70 save_boot_params_ret();
71 }
72 #endif
73
spl_was_boot_source(void)74 bool spl_was_boot_source(void)
75 {
76 return from_spl;
77 }
78
79 #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
80 #if !defined(CONFIG_TEGRA124)
81 #error tegra_cpu_is_non_secure has only been validated on Tegra124
82 #endif
tegra_cpu_is_non_secure(void)83 bool tegra_cpu_is_non_secure(void)
84 {
85 /*
86 * This register reads 0xffffffff in non-secure mode. This register
87 * only implements bits 31:20, so the lower bits will always read 0 in
88 * secure mode. Thus, the lower bits are an indicator for secure vs.
89 * non-secure mode.
90 */
91 struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
92 uint32_t mc_s_cfg0 = readl(&mc->mc_security_cfg0);
93 return (mc_s_cfg0 & 1) == 1;
94 }
95 #endif
96
97 #if IS_ENABLED(CONFIG_TEGRA_MC)
98 /* Read the RAM size directly from the memory controller */
query_sdram_size(void)99 static phys_size_t query_sdram_size(void)
100 {
101 struct mc_ctlr *const mc = (struct mc_ctlr *)NV_PA_MC_BASE;
102 u32 emem_cfg;
103 phys_size_t size_bytes;
104
105 emem_cfg = readl(&mc->mc_emem_cfg);
106 #if defined(CONFIG_TEGRA20)
107 debug("mc->mc_emem_cfg (MEM_SIZE_KB) = 0x%08x\n", emem_cfg);
108 size_bytes = get_ram_size((void *)PHYS_SDRAM_1, emem_cfg * 1024);
109 #else
110 debug("mc->mc_emem_cfg (MEM_SIZE_MB) = 0x%08x\n", emem_cfg);
111 #ifndef CONFIG_PHYS_64BIT
112 /*
113 * If >=4GB RAM is present, the byte RAM size won't fit into 32-bits
114 * and will wrap. Clip the reported size to the maximum that a 32-bit
115 * variable can represent (rounded to a page).
116 */
117 if (emem_cfg >= 4096) {
118 size_bytes = U32_MAX & ~(0x1000 - 1);
119 } else
120 #endif
121 {
122 /* RAM size EMC is programmed to. */
123 size_bytes = (phys_size_t)emem_cfg * 1024 * 1024;
124 #ifndef CONFIG_ARM64
125 /*
126 * If all RAM fits within 32-bits, it can be accessed without
127 * LPAE, so go test the RAM size. Otherwise, we can't access
128 * all the RAM, and get_ram_size() would get confused, so
129 * avoid using it. There's no reason we should need this
130 * validation step anyway.
131 */
132 if (emem_cfg <= (0 - PHYS_SDRAM_1) / (1024 * 1024))
133 size_bytes = get_ram_size((void *)PHYS_SDRAM_1,
134 size_bytes);
135 #endif
136 }
137 #endif
138
139 #if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114)
140 /* External memory limited to 2047 MB due to IROM/HI-VEC */
141 if (size_bytes == SZ_2G)
142 size_bytes -= SZ_1M;
143 #endif
144
145 return size_bytes;
146 }
147 #endif
148
dram_init(void)149 int dram_init(void)
150 {
151 int err;
152
153 /* try to initialize DRAM from cboot DTB first */
154 err = cboot_dram_init();
155 if (err == 0)
156 return 0;
157
158 #if IS_ENABLED(CONFIG_TEGRA_MC)
159 /* We do not initialise DRAM here. We just query the size */
160 gd->ram_size = query_sdram_size();
161 #endif
162
163 return 0;
164 }
165
166 #if IS_ENABLED(CONFIG_TEGRA_PINCTRL)
167 static int uart_configs[] = {
168 #if defined(CONFIG_TEGRA20)
169 #if defined(CONFIG_TEGRA_UARTA_UAA_UAB)
170 FUNCMUX_UART1_UAA_UAB,
171 #elif defined(CONFIG_TEGRA_UARTA_GPU)
172 FUNCMUX_UART1_GPU,
173 #elif defined(CONFIG_TEGRA_UARTA_SDIO1)
174 FUNCMUX_UART1_SDIO1,
175 #else
176 FUNCMUX_UART1_IRRX_IRTX,
177 #endif
178 FUNCMUX_UART2_UAD,
179 -1,
180 FUNCMUX_UART4_GMC,
181 -1,
182 #elif defined(CONFIG_TEGRA30)
183 FUNCMUX_UART1_ULPI, /* UARTA */
184 -1,
185 -1,
186 -1,
187 -1,
188 #elif defined(CONFIG_TEGRA114)
189 -1,
190 -1,
191 -1,
192 FUNCMUX_UART4_GMI, /* UARTD */
193 -1,
194 #elif defined(CONFIG_TEGRA124)
195 FUNCMUX_UART1_KBC, /* UARTA */
196 -1,
197 -1,
198 FUNCMUX_UART4_GPIO, /* UARTD */
199 -1,
200 #else /* Tegra210 */
201 FUNCMUX_UART1_UART1, /* UARTA */
202 -1,
203 -1,
204 FUNCMUX_UART4_UART4, /* UARTD */
205 -1,
206 #endif
207 };
208
209 /**
210 * Set up the specified uarts
211 *
212 * @param uarts_ids Mask containing UARTs to init (UARTx)
213 */
setup_uarts(int uart_ids)214 static void setup_uarts(int uart_ids)
215 {
216 static enum periph_id id_for_uart[] = {
217 PERIPH_ID_UART1,
218 PERIPH_ID_UART2,
219 PERIPH_ID_UART3,
220 PERIPH_ID_UART4,
221 PERIPH_ID_UART5,
222 };
223 size_t i;
224
225 for (i = 0; i < UART_COUNT; i++) {
226 if (uart_ids & (1 << i)) {
227 enum periph_id id = id_for_uart[i];
228
229 funcmux_select(id, uart_configs[i]);
230 clock_ll_start_uart(id);
231 }
232 }
233 }
234 #endif
235
board_init_uart_f(void)236 void board_init_uart_f(void)
237 {
238 #if IS_ENABLED(CONFIG_TEGRA_PINCTRL)
239 int uart_ids = 0; /* bit mask of which UART ids to enable */
240
241 #ifdef CONFIG_TEGRA_ENABLE_UARTA
242 uart_ids |= UARTA;
243 #endif
244 #ifdef CONFIG_TEGRA_ENABLE_UARTB
245 uart_ids |= UARTB;
246 #endif
247 #ifdef CONFIG_TEGRA_ENABLE_UARTC
248 uart_ids |= UARTC;
249 #endif
250 #ifdef CONFIG_TEGRA_ENABLE_UARTD
251 uart_ids |= UARTD;
252 #endif
253 #ifdef CONFIG_TEGRA_ENABLE_UARTE
254 uart_ids |= UARTE;
255 #endif
256 setup_uarts(uart_ids);
257 #endif
258 }
259
260 #if !CONFIG_IS_ENABLED(OF_CONTROL)
261 static struct ns16550_plat ns16550_com1_pdata = {
262 .base = CONFIG_SYS_NS16550_COM1,
263 .reg_shift = 2,
264 .clock = CONFIG_SYS_NS16550_CLK,
265 .fcr = UART_FCR_DEFVAL,
266 };
267
268 U_BOOT_DRVINFO(ns16550_com1) = {
269 "ns16550_serial", &ns16550_com1_pdata
270 };
271 #endif
272
273 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
enable_caches(void)274 void enable_caches(void)
275 {
276 /* Enable D-cache. I-cache is already enabled in start.S */
277 dcache_enable();
278 }
279 #endif
280