1 /* 2 * xen/include/xen/8250-uart.h 3 * 4 * This header is extracted from driver/char/ns16550.c 5 * 6 * Common constant definition between early printk and the UART driver 7 * for the 16550-series UART 8 * 9 * Copyright (c) 2003-2005, K A Fraser 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 */ 21 22 #ifndef __XEN_8250_UART_H__ 23 #define __XEN_8250_UART_H__ 24 25 /* Register offsets */ 26 #define UART_RBR 0x00 /* receive buffer */ 27 #define UART_THR 0x00 /* transmit holding */ 28 #define UART_IER 0x01 /* interrupt enable */ 29 #define UART_IIR 0x02 /* interrupt identity */ 30 #define UART_FCR 0x02 /* FIFO control */ 31 #define UART_LCR 0x03 /* line control */ 32 #define UART_MCR 0x04 /* Modem control */ 33 #define UART_LSR 0x05 /* line status */ 34 #define UART_MSR 0x06 /* Modem status */ 35 #define UART_USR 0x1f /* Status register (DW) */ 36 #define UART_DLL 0x00 /* divisor latch (ls) (DLAB=1) */ 37 #define UART_DLM 0x01 /* divisor latch (ms) (DLAB=1) */ 38 39 /* Interrupt Enable Register */ 40 #define UART_IER_ERDAI 0x01 /* rx data recv'd */ 41 #define UART_IER_ETHREI 0x02 /* tx reg. empty */ 42 #define UART_IER_ELSI 0x04 /* rx line status */ 43 #define UART_IER_EMSI 0x08 /* MODEM status */ 44 45 /* Interrupt Identification Register */ 46 #define UART_IIR_NOINT 0x01 /* no interrupt pending */ 47 #define UART_IIR_IMA 0x06 /* interrupt identity: */ 48 #define UART_IIR_LSI 0x06 /* - rx line status */ 49 #define UART_IIR_RDA 0x04 /* - rx data recv'd */ 50 #define UART_IIR_THR 0x02 /* - tx reg. empty */ 51 #define UART_IIR_MSI 0x00 /* - MODEM status */ 52 #define UART_IIR_BSY 0x07 /* - busy detect (DW) */ 53 54 /* FIFO Control Register */ 55 #define UART_FCR_ENABLE 0x01 /* enable FIFO */ 56 #define UART_FCR_CLRX 0x02 /* clear Rx FIFO */ 57 #define UART_FCR_CLTX 0x04 /* clear Tx FIFO */ 58 #define UART_FCR_DMA 0x10 /* enter DMA mode */ 59 #define UART_FCR_TRG1 0x00 /* Rx FIFO trig lev 1 */ 60 #define UART_FCR_TRG4 0x40 /* Rx FIFO trig lev 4 */ 61 #define UART_FCR_TRG8 0x80 /* Rx FIFO trig lev 8 */ 62 #define UART_FCR_TRG14 0xc0 /* Rx FIFO trig lev 14 */ 63 64 /* 65 * Note: The FIFO trigger levels are chip specific: 66 * RX:76 = 00 01 10 11 TX:54 = 00 01 10 11 67 * PC16550D: 1 4 8 14 xx xx xx xx 68 * TI16C550A: 1 4 8 14 xx xx xx xx 69 * TI16C550C: 1 4 8 14 xx xx xx xx 70 * ST16C550: 1 4 8 14 xx xx xx xx 71 * ST16C650: 8 16 24 28 16 8 24 30 PORT_16650V2 72 * NS16C552: 1 4 8 14 xx xx xx xx 73 * ST16C654: 8 16 56 60 8 16 32 56 PORT_16654 74 * TI16C750: 1 16 32 56 xx xx xx xx PORT_16750 75 * TI16C752: 8 16 56 60 8 16 32 56 76 * Tegra: 1 4 8 14 16 8 4 1 PORT_TEGRA 77 */ 78 #define UART_FCR_R_TRIG_00 0x00 79 #define UART_FCR_R_TRIG_01 0x40 80 #define UART_FCR_R_TRIG_10 0x80 81 #define UART_FCR_R_TRIG_11 0xc0 82 #define UART_FCR_T_TRIG_00 0x00 83 #define UART_FCR_T_TRIG_01 0x10 84 #define UART_FCR_T_TRIG_10 0x20 85 #define UART_FCR_T_TRIG_11 0x30 86 87 /* Line Control Register */ 88 #define UART_LCR_DLAB 0x80 /* Divisor Latch Access */ 89 90 /* 91 * Access to some registers depends on register access / configuration 92 * mode. 93 */ 94 #define UART_LCR_CONF_MODE_A UART_LCR_DLAB /* Configuration mode A */ 95 #define UART_LCR_CONF_MODE_B 0xBF /* Configuration mode B */ 96 97 /* Modem Control Register */ 98 #define UART_MCR_DTR 0x01 /* Data Terminal Ready */ 99 #define UART_MCR_RTS 0x02 /* Request to Send */ 100 #define UART_MCR_OUT2 0x08 /* OUT2: interrupt mask */ 101 #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ 102 #define UART_MCR_TCRTLR 0x40 /* Access TCR/TLR (TI16C752, EFR[4]=1) */ 103 104 /* Line Status Register */ 105 #define UART_LSR_DR 0x01 /* Data ready */ 106 #define UART_LSR_OE 0x02 /* Overrun */ 107 #define UART_LSR_PE 0x04 /* Parity error */ 108 #define UART_LSR_FE 0x08 /* Framing error */ 109 #define UART_LSR_BI 0x10 /* Break */ 110 #define UART_LSR_THRE 0x20 /* Xmit hold reg empty */ 111 #define UART_LSR_TEMT 0x40 /* Xmitter empty */ 112 #define UART_LSR_ERR 0x80 /* Error */ 113 114 /* These parity settings can be ORed directly into the LCR. */ 115 #define UART_PARITY_NONE (0<<3) 116 #define UART_PARITY_ODD (1<<3) 117 #define UART_PARITY_EVEN (3<<3) 118 #define UART_PARITY_MARK (5<<3) 119 #define UART_PARITY_SPACE (7<<3) 120 121 /* Frequency of external clock source. This definition assumes PC platform. */ 122 #define UART_CLOCK_HZ 1843200 123 124 /* Resume retry settings */ 125 #define RESUME_DELAY MILLISECS(10) 126 #define RESUME_RETRIES 100 127 128 #endif /* __XEN_8250_UART_H__ */ 129 130 /* 131 * Local variables: 132 * mode: C 133 * c-file-style: "BSD" 134 * c-basic-offset: 4 135 * indent-tabs-mode: nil 136 * End: 137 */ 138