1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * linux/include/mfd/ucb1x00.h
4 *
5 * Copyright (C) 2001 Russell King, All Rights Reserved.
6 */
7 #ifndef UCB1200_H
8 #define UCB1200_H
9
10 #include <linux/device.h>
11 #include <linux/mfd/mcp.h>
12 #include <linux/gpio.h>
13 #include <linux/mutex.h>
14
15 #define UCB_IO_DATA 0x00
16 #define UCB_IO_DIR 0x01
17
18 #define UCB_IO_0 (1 << 0)
19 #define UCB_IO_1 (1 << 1)
20 #define UCB_IO_2 (1 << 2)
21 #define UCB_IO_3 (1 << 3)
22 #define UCB_IO_4 (1 << 4)
23 #define UCB_IO_5 (1 << 5)
24 #define UCB_IO_6 (1 << 6)
25 #define UCB_IO_7 (1 << 7)
26 #define UCB_IO_8 (1 << 8)
27 #define UCB_IO_9 (1 << 9)
28
29 #define UCB_IE_RIS 0x02
30 #define UCB_IE_FAL 0x03
31 #define UCB_IE_STATUS 0x04
32 #define UCB_IE_CLEAR 0x04
33 #define UCB_IE_ADC (1 << 11)
34 #define UCB_IE_TSPX (1 << 12)
35 #define UCB_IE_TSMX (1 << 13)
36 #define UCB_IE_TCLIP (1 << 14)
37 #define UCB_IE_ACLIP (1 << 15)
38
39 #define UCB_IRQ_TSPX 12
40
41 #define UCB_TC_A 0x05
42 #define UCB_TC_A_LOOP (1 << 7) /* UCB1200 */
43 #define UCB_TC_A_AMPL (1 << 7) /* UCB1300 */
44
45 #define UCB_TC_B 0x06
46 #define UCB_TC_B_VOICE_ENA (1 << 3)
47 #define UCB_TC_B_CLIP (1 << 4)
48 #define UCB_TC_B_ATT (1 << 6)
49 #define UCB_TC_B_SIDE_ENA (1 << 11)
50 #define UCB_TC_B_MUTE (1 << 13)
51 #define UCB_TC_B_IN_ENA (1 << 14)
52 #define UCB_TC_B_OUT_ENA (1 << 15)
53
54 #define UCB_AC_A 0x07
55 #define UCB_AC_B 0x08
56 #define UCB_AC_B_LOOP (1 << 8)
57 #define UCB_AC_B_MUTE (1 << 13)
58 #define UCB_AC_B_IN_ENA (1 << 14)
59 #define UCB_AC_B_OUT_ENA (1 << 15)
60
61 #define UCB_TS_CR 0x09
62 #define UCB_TS_CR_TSMX_POW (1 << 0)
63 #define UCB_TS_CR_TSPX_POW (1 << 1)
64 #define UCB_TS_CR_TSMY_POW (1 << 2)
65 #define UCB_TS_CR_TSPY_POW (1 << 3)
66 #define UCB_TS_CR_TSMX_GND (1 << 4)
67 #define UCB_TS_CR_TSPX_GND (1 << 5)
68 #define UCB_TS_CR_TSMY_GND (1 << 6)
69 #define UCB_TS_CR_TSPY_GND (1 << 7)
70 #define UCB_TS_CR_MODE_INT (0 << 8)
71 #define UCB_TS_CR_MODE_PRES (1 << 8)
72 #define UCB_TS_CR_MODE_POS (2 << 8)
73 #define UCB_TS_CR_BIAS_ENA (1 << 11)
74 #define UCB_TS_CR_TSPX_LOW (1 << 12)
75 #define UCB_TS_CR_TSMX_LOW (1 << 13)
76
77 #define UCB_ADC_CR 0x0a
78 #define UCB_ADC_SYNC_ENA (1 << 0)
79 #define UCB_ADC_VREFBYP_CON (1 << 1)
80 #define UCB_ADC_INP_TSPX (0 << 2)
81 #define UCB_ADC_INP_TSMX (1 << 2)
82 #define UCB_ADC_INP_TSPY (2 << 2)
83 #define UCB_ADC_INP_TSMY (3 << 2)
84 #define UCB_ADC_INP_AD0 (4 << 2)
85 #define UCB_ADC_INP_AD1 (5 << 2)
86 #define UCB_ADC_INP_AD2 (6 << 2)
87 #define UCB_ADC_INP_AD3 (7 << 2)
88 #define UCB_ADC_EXT_REF (1 << 5)
89 #define UCB_ADC_START (1 << 7)
90 #define UCB_ADC_ENA (1 << 15)
91
92 #define UCB_ADC_DATA 0x0b
93 #define UCB_ADC_DAT_VAL (1 << 15)
94 #define UCB_ADC_DAT(x) (((x) & 0x7fe0) >> 5)
95
96 #define UCB_ID 0x0c
97 #define UCB_ID_1200 0x1004
98 #define UCB_ID_1300 0x1005
99 #define UCB_ID_TC35143 0x9712
100
101 #define UCB_MODE 0x0d
102 #define UCB_MODE_DYN_VFLAG_ENA (1 << 12)
103 #define UCB_MODE_AUD_OFF_CAN (1 << 13)
104
105 enum ucb1x00_reset {
106 UCB_RST_PROBE,
107 UCB_RST_RESUME,
108 UCB_RST_SUSPEND,
109 UCB_RST_REMOVE,
110 UCB_RST_PROBE_FAIL,
111 };
112
113 struct ucb1x00_plat_data {
114 void (*reset)(enum ucb1x00_reset);
115 unsigned irq_base;
116 int gpio_base;
117 unsigned can_wakeup;
118 };
119
120 struct ucb1x00 {
121 raw_spinlock_t irq_lock;
122 struct mcp *mcp;
123 unsigned int irq;
124 int irq_base;
125 struct mutex adc_mutex;
126 spinlock_t io_lock;
127 u16 id;
128 u16 io_dir;
129 u16 io_out;
130 u16 adc_cr;
131 u16 irq_fal_enbl;
132 u16 irq_ris_enbl;
133 u16 irq_mask;
134 u16 irq_wake;
135 struct device dev;
136 struct list_head node;
137 struct list_head devs;
138 struct gpio_chip gpio;
139 };
140
141 struct ucb1x00_driver;
142
143 struct ucb1x00_dev {
144 struct list_head dev_node;
145 struct list_head drv_node;
146 struct ucb1x00 *ucb;
147 struct ucb1x00_driver *drv;
148 void *priv;
149 };
150
151 struct ucb1x00_driver {
152 struct list_head node;
153 struct list_head devs;
154 int (*add)(struct ucb1x00_dev *dev);
155 void (*remove)(struct ucb1x00_dev *dev);
156 int (*suspend)(struct ucb1x00_dev *dev);
157 int (*resume)(struct ucb1x00_dev *dev);
158 };
159
160 #define classdev_to_ucb1x00(cd) container_of(cd, struct ucb1x00, dev)
161
162 int ucb1x00_register_driver(struct ucb1x00_driver *);
163 void ucb1x00_unregister_driver(struct ucb1x00_driver *);
164
165 /**
166 * ucb1x00_clkrate - return the UCB1x00 SIB clock rate
167 * @ucb: UCB1x00 structure describing chip
168 *
169 * Return the SIB clock rate in Hz.
170 */
ucb1x00_clkrate(struct ucb1x00 * ucb)171 static inline unsigned int ucb1x00_clkrate(struct ucb1x00 *ucb)
172 {
173 return mcp_get_sclk_rate(ucb->mcp);
174 }
175
176 /**
177 * ucb1x00_enable - enable the UCB1x00 SIB clock
178 * @ucb: UCB1x00 structure describing chip
179 *
180 * Enable the SIB clock. This can be called multiple times.
181 */
ucb1x00_enable(struct ucb1x00 * ucb)182 static inline void ucb1x00_enable(struct ucb1x00 *ucb)
183 {
184 mcp_enable(ucb->mcp);
185 }
186
187 /**
188 * ucb1x00_disable - disable the UCB1x00 SIB clock
189 * @ucb: UCB1x00 structure describing chip
190 *
191 * Disable the SIB clock. The SIB clock will only be disabled
192 * when the number of ucb1x00_enable calls match the number of
193 * ucb1x00_disable calls.
194 */
ucb1x00_disable(struct ucb1x00 * ucb)195 static inline void ucb1x00_disable(struct ucb1x00 *ucb)
196 {
197 mcp_disable(ucb->mcp);
198 }
199
200 /**
201 * ucb1x00_reg_write - write a UCB1x00 register
202 * @ucb: UCB1x00 structure describing chip
203 * @reg: UCB1x00 4-bit register index to write
204 * @val: UCB1x00 16-bit value to write
205 *
206 * Write the UCB1x00 register @reg with value @val. The SIB
207 * clock must be running for this function to return.
208 */
ucb1x00_reg_write(struct ucb1x00 * ucb,unsigned int reg,unsigned int val)209 static inline void ucb1x00_reg_write(struct ucb1x00 *ucb, unsigned int reg, unsigned int val)
210 {
211 mcp_reg_write(ucb->mcp, reg, val);
212 }
213
214 /**
215 * ucb1x00_reg_read - read a UCB1x00 register
216 * @ucb: UCB1x00 structure describing chip
217 * @reg: UCB1x00 4-bit register index to write
218 *
219 * Read the UCB1x00 register @reg and return its value. The SIB
220 * clock must be running for this function to return.
221 */
ucb1x00_reg_read(struct ucb1x00 * ucb,unsigned int reg)222 static inline unsigned int ucb1x00_reg_read(struct ucb1x00 *ucb, unsigned int reg)
223 {
224 return mcp_reg_read(ucb->mcp, reg);
225 }
226 /**
227 * ucb1x00_set_audio_divisor -
228 * @ucb: UCB1x00 structure describing chip
229 * @div: SIB clock divisor
230 */
ucb1x00_set_audio_divisor(struct ucb1x00 * ucb,unsigned int div)231 static inline void ucb1x00_set_audio_divisor(struct ucb1x00 *ucb, unsigned int div)
232 {
233 mcp_set_audio_divisor(ucb->mcp, div);
234 }
235
236 /**
237 * ucb1x00_set_telecom_divisor -
238 * @ucb: UCB1x00 structure describing chip
239 * @div: SIB clock divisor
240 */
ucb1x00_set_telecom_divisor(struct ucb1x00 * ucb,unsigned int div)241 static inline void ucb1x00_set_telecom_divisor(struct ucb1x00 *ucb, unsigned int div)
242 {
243 mcp_set_telecom_divisor(ucb->mcp, div);
244 }
245
246 void ucb1x00_io_set_dir(struct ucb1x00 *ucb, unsigned int, unsigned int);
247 void ucb1x00_io_write(struct ucb1x00 *ucb, unsigned int, unsigned int);
248 unsigned int ucb1x00_io_read(struct ucb1x00 *ucb);
249
250 #define UCB_NOSYNC (0)
251 #define UCB_SYNC (1)
252
253 unsigned int ucb1x00_adc_read(struct ucb1x00 *ucb, int adc_channel, int sync);
254 void ucb1x00_adc_enable(struct ucb1x00 *ucb);
255 void ucb1x00_adc_disable(struct ucb1x00 *ucb);
256
257 #endif
258