1 /*
2  * Copyright 2021 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 #ifndef __UMC_V6_7_H__
24 #define __UMC_V6_7_H__
25 
26 #include "soc15_common.h"
27 #include "amdgpu.h"
28 
29 /* EccErrCnt max value */
30 #define UMC_V6_7_CE_CNT_MAX		0xffff
31 /* umc ce interrupt threshold */
32 #define UMC_V6_7_CE_INT_THRESHOLD	0xffff
33 /* umc ce count initial value */
34 #define UMC_V6_7_CE_CNT_INIT	(UMC_V6_7_CE_CNT_MAX - UMC_V6_7_CE_INT_THRESHOLD)
35 
36 #define UMC_V6_7_INST_DIST	0x40000
37 
38 /* number of umc channel instance with memory map register access */
39 #define UMC_V6_7_UMC_INSTANCE_NUM		4
40 /* number of umc instance with memory map register access */
41 #define UMC_V6_7_CHANNEL_INSTANCE_NUM		8
42 /* total channel instances in one umc block */
43 #define UMC_V6_7_TOTAL_CHANNEL_NUM	(UMC_V6_7_CHANNEL_INSTANCE_NUM * UMC_V6_7_UMC_INSTANCE_NUM)
44 /* UMC regiser per channel offset */
45 #define UMC_V6_7_PER_CHANNEL_OFFSET		0x400
46 extern const struct amdgpu_umc_ras_funcs umc_v6_7_ras_funcs;
47 extern const uint32_t
48 	umc_v6_7_channel_idx_tbl_second[UMC_V6_7_UMC_INSTANCE_NUM][UMC_V6_7_CHANNEL_INSTANCE_NUM];
49 extern const uint32_t
50 	umc_v6_7_channel_idx_tbl_first[UMC_V6_7_UMC_INSTANCE_NUM][UMC_V6_7_CHANNEL_INSTANCE_NUM];
51 
52 #endif
53