1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * AArch64 processor specific defines
4 *
5 * Copyright (C) 2018, Red Hat, Inc.
6 */
7 #ifndef SELFTEST_KVM_PROCESSOR_H
8 #define SELFTEST_KVM_PROCESSOR_H
9
10 #include "kvm_util.h"
11 #include <linux/stringify.h>
12 #include <linux/types.h>
13 #include <asm/sysreg.h>
14
15
16 #define ARM64_CORE_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \
17 KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x))
18
19 /*
20 * KVM_ARM64_SYS_REG(sys_reg_id): Helper macro to convert
21 * SYS_* register definitions in asm/sysreg.h to use in KVM
22 * calls such as get_reg() and set_reg().
23 */
24 #define KVM_ARM64_SYS_REG(sys_reg_id) \
25 ARM64_SYS_REG(sys_reg_Op0(sys_reg_id), \
26 sys_reg_Op1(sys_reg_id), \
27 sys_reg_CRn(sys_reg_id), \
28 sys_reg_CRm(sys_reg_id), \
29 sys_reg_Op2(sys_reg_id))
30
31 /*
32 * Default MAIR
33 * index attribute
34 * DEVICE_nGnRnE 0 0000:0000
35 * DEVICE_nGnRE 1 0000:0100
36 * DEVICE_GRE 2 0000:1100
37 * NORMAL_NC 3 0100:0100
38 * NORMAL 4 1111:1111
39 * NORMAL_WT 5 1011:1011
40 */
41 #define DEFAULT_MAIR_EL1 ((0x00ul << (0 * 8)) | \
42 (0x04ul << (1 * 8)) | \
43 (0x0cul << (2 * 8)) | \
44 (0x44ul << (3 * 8)) | \
45 (0xfful << (4 * 8)) | \
46 (0xbbul << (5 * 8)))
47
48 #define MPIDR_HWID_BITMASK (0xff00fffffful)
49
get_reg(struct kvm_vm * vm,uint32_t vcpuid,uint64_t id,uint64_t * addr)50 static inline void get_reg(struct kvm_vm *vm, uint32_t vcpuid, uint64_t id, uint64_t *addr)
51 {
52 struct kvm_one_reg reg;
53 reg.id = id;
54 reg.addr = (uint64_t)addr;
55 vcpu_ioctl(vm, vcpuid, KVM_GET_ONE_REG, ®);
56 }
57
set_reg(struct kvm_vm * vm,uint32_t vcpuid,uint64_t id,uint64_t val)58 static inline void set_reg(struct kvm_vm *vm, uint32_t vcpuid, uint64_t id, uint64_t val)
59 {
60 struct kvm_one_reg reg;
61 reg.id = id;
62 reg.addr = (uint64_t)&val;
63 vcpu_ioctl(vm, vcpuid, KVM_SET_ONE_REG, ®);
64 }
65
66 void aarch64_vcpu_setup(struct kvm_vm *vm, uint32_t vcpuid, struct kvm_vcpu_init *init);
67 void aarch64_vcpu_add_default(struct kvm_vm *vm, uint32_t vcpuid,
68 struct kvm_vcpu_init *init, void *guest_code);
69
70 struct ex_regs {
71 u64 regs[31];
72 u64 sp;
73 u64 pc;
74 u64 pstate;
75 };
76
77 #define VECTOR_NUM 16
78
79 enum {
80 VECTOR_SYNC_CURRENT_SP0,
81 VECTOR_IRQ_CURRENT_SP0,
82 VECTOR_FIQ_CURRENT_SP0,
83 VECTOR_ERROR_CURRENT_SP0,
84
85 VECTOR_SYNC_CURRENT,
86 VECTOR_IRQ_CURRENT,
87 VECTOR_FIQ_CURRENT,
88 VECTOR_ERROR_CURRENT,
89
90 VECTOR_SYNC_LOWER_64,
91 VECTOR_IRQ_LOWER_64,
92 VECTOR_FIQ_LOWER_64,
93 VECTOR_ERROR_LOWER_64,
94
95 VECTOR_SYNC_LOWER_32,
96 VECTOR_IRQ_LOWER_32,
97 VECTOR_FIQ_LOWER_32,
98 VECTOR_ERROR_LOWER_32,
99 };
100
101 #define VECTOR_IS_SYNC(v) ((v) == VECTOR_SYNC_CURRENT_SP0 || \
102 (v) == VECTOR_SYNC_CURRENT || \
103 (v) == VECTOR_SYNC_LOWER_64 || \
104 (v) == VECTOR_SYNC_LOWER_32)
105
106 #define ESR_EC_NUM 64
107 #define ESR_EC_SHIFT 26
108 #define ESR_EC_MASK (ESR_EC_NUM - 1)
109
110 #define ESR_EC_SVC64 0x15
111 #define ESR_EC_HW_BP_CURRENT 0x31
112 #define ESR_EC_SSTEP_CURRENT 0x33
113 #define ESR_EC_WP_CURRENT 0x35
114 #define ESR_EC_BRK_INS 0x3c
115
116 void vm_init_descriptor_tables(struct kvm_vm *vm);
117 void vcpu_init_descriptor_tables(struct kvm_vm *vm, uint32_t vcpuid);
118
119 typedef void(*handler_fn)(struct ex_regs *);
120 void vm_install_exception_handler(struct kvm_vm *vm,
121 int vector, handler_fn handler);
122 void vm_install_sync_handler(struct kvm_vm *vm,
123 int vector, int ec, handler_fn handler);
124
cpu_relax(void)125 static inline void cpu_relax(void)
126 {
127 asm volatile("yield" ::: "memory");
128 }
129
130 #define isb() asm volatile("isb" : : : "memory")
131 #define dsb(opt) asm volatile("dsb " #opt : : : "memory")
132 #define dmb(opt) asm volatile("dmb " #opt : : : "memory")
133
134 #define dma_wmb() dmb(oshst)
135 #define __iowmb() dma_wmb()
136
137 #define dma_rmb() dmb(oshld)
138
139 #define __iormb(v) \
140 ({ \
141 unsigned long tmp; \
142 \
143 dma_rmb(); \
144 \
145 /* \
146 * Courtesy of arch/arm64/include/asm/io.h: \
147 * Create a dummy control dependency from the IO read to any \
148 * later instructions. This ensures that a subsequent call \
149 * to udelay() will be ordered due to the ISB in __delay(). \
150 */ \
151 asm volatile("eor %0, %1, %1\n" \
152 "cbnz %0, ." \
153 : "=r" (tmp) : "r" ((unsigned long)(v)) \
154 : "memory"); \
155 })
156
__raw_writel(u32 val,volatile void * addr)157 static __always_inline void __raw_writel(u32 val, volatile void *addr)
158 {
159 asm volatile("str %w0, [%1]" : : "rZ" (val), "r" (addr));
160 }
161
__raw_readl(const volatile void * addr)162 static __always_inline u32 __raw_readl(const volatile void *addr)
163 {
164 u32 val;
165 asm volatile("ldr %w0, [%1]" : "=r" (val) : "r" (addr));
166 return val;
167 }
168
169 #define writel_relaxed(v,c) ((void)__raw_writel((__force u32)cpu_to_le32(v),(c)))
170 #define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32)__raw_readl(c)); __r; })
171
172 #define writel(v,c) ({ __iowmb(); writel_relaxed((v),(c));})
173 #define readl(c) ({ u32 __v = readl_relaxed(c); __iormb(__v); __v; })
174
local_irq_enable(void)175 static inline void local_irq_enable(void)
176 {
177 asm volatile("msr daifclr, #3" : : : "memory");
178 }
179
local_irq_disable(void)180 static inline void local_irq_disable(void)
181 {
182 asm volatile("msr daifset, #3" : : : "memory");
183 }
184
185 #endif /* SELFTEST_KVM_PROCESSOR_H */
186