1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2015 Amlogic, Inc. All rights reserved. 4 */ 5 6 #ifndef __MESON_REGISTERS_H 7 #define __MESON_REGISTERS_H 8 9 /* Shift all registers by 2 */ 10 #include <linux/bitops.h> 11 #define _REG(reg) ((reg) << 2) 12 13 #define writel_bits(mask, val, addr) \ 14 writel((readl(addr) & ~(mask)) | (val), addr) 15 16 /* vpp2 */ 17 #define VPP2_DUMMY_DATA 0x1900 18 #define VPP2_LINE_IN_LENGTH 0x1901 19 #define VPP2_PIC_IN_HEIGHT 0x1902 20 #define VPP2_SCALE_COEF_IDX 0x1903 21 #define VPP2_SCALE_COEF 0x1904 22 #define VPP2_VSC_REGION12_STARTP 0x1905 23 #define VPP2_VSC_REGION34_STARTP 0x1906 24 #define VPP2_VSC_REGION4_ENDP 0x1907 25 #define VPP2_VSC_START_PHASE_STEP 0x1908 26 #define VPP2_VSC_REGION0_PHASE_SLOPE 0x1909 27 #define VPP2_VSC_REGION1_PHASE_SLOPE 0x190a 28 #define VPP2_VSC_REGION3_PHASE_SLOPE 0x190b 29 #define VPP2_VSC_REGION4_PHASE_SLOPE 0x190c 30 #define VPP2_VSC_PHASE_CTRL 0x190d 31 #define VPP2_VSC_INI_PHASE 0x190e 32 #define VPP2_HSC_REGION12_STARTP 0x1910 33 #define VPP2_HSC_REGION34_STARTP 0x1911 34 #define VPP2_HSC_REGION4_ENDP 0x1912 35 #define VPP2_HSC_START_PHASE_STEP 0x1913 36 #define VPP2_HSC_REGION0_PHASE_SLOPE 0x1914 37 #define VPP2_HSC_REGION1_PHASE_SLOPE 0x1915 38 #define VPP2_HSC_REGION3_PHASE_SLOPE 0x1916 39 #define VPP2_HSC_REGION4_PHASE_SLOPE 0x1917 40 #define VPP2_HSC_PHASE_CTRL 0x1918 41 #define VPP2_SC_MISC 0x1919 42 #define VPP2_PREBLEND_VD1_H_START_END 0x191a 43 #define VPP2_PREBLEND_VD1_V_START_END 0x191b 44 #define VPP2_POSTBLEND_VD1_H_START_END 0x191c 45 #define VPP2_POSTBLEND_VD1_V_START_END 0x191d 46 #define VPP2_PREBLEND_H_SIZE 0x1920 47 #define VPP2_POSTBLEND_H_SIZE 0x1921 48 #define VPP2_HOLD_LINES 0x1922 49 #define VPP2_BLEND_ONECOLOR_CTRL 0x1923 50 #define VPP2_PREBLEND_CURRENT_XY 0x1924 51 #define VPP2_POSTBLEND_CURRENT_XY 0x1925 52 #define VPP2_MISC 0x1926 53 #define VPP2_OFIFO_SIZE 0x1927 54 #define VPP2_FIFO_STATUS 0x1928 55 #define VPP2_SMOKE_CTRL 0x1929 56 #define VPP2_SMOKE1_VAL 0x192a 57 #define VPP2_SMOKE2_VAL 0x192b 58 #define VPP2_SMOKE1_H_START_END 0x192d 59 #define VPP2_SMOKE1_V_START_END 0x192e 60 #define VPP2_SMOKE2_H_START_END 0x192f 61 #define VPP2_SMOKE2_V_START_END 0x1930 62 #define VPP2_SCO_FIFO_CTRL 0x1933 63 #define VPP2_HSC_PHASE_CTRL1 0x1934 64 #define VPP2_HSC_INI_PAT_CTRL 0x1935 65 #define VPP2_VADJ_CTRL 0x1940 66 #define VPP2_VADJ1_Y 0x1941 67 #define VPP2_VADJ1_MA_MB 0x1942 68 #define VPP2_VADJ1_MC_MD 0x1943 69 #define VPP2_VADJ2_Y 0x1944 70 #define VPP2_VADJ2_MA_MB 0x1945 71 #define VPP2_VADJ2_MC_MD 0x1946 72 #define VPP2_MATRIX_PROBE_COLOR 0x195c 73 #define VPP2_MATRIX_HL_COLOR 0x195d 74 #define VPP2_MATRIX_PROBE_POS 0x195e 75 #define VPP2_MATRIX_CTRL 0x195f 76 #define VPP2_MATRIX_COEF00_01 0x1960 77 #define VPP2_MATRIX_COEF02_10 0x1961 78 #define VPP2_MATRIX_COEF11_12 0x1962 79 #define VPP2_MATRIX_COEF20_21 0x1963 80 #define VPP2_MATRIX_COEF22 0x1964 81 #define VPP2_MATRIX_OFFSET0_1 0x1965 82 #define VPP2_MATRIX_OFFSET2 0x1966 83 #define VPP2_MATRIX_PRE_OFFSET0_1 0x1967 84 #define VPP2_MATRIX_PRE_OFFSET2 0x1968 85 #define VPP2_DUMMY_DATA1 0x1969 86 #define VPP2_GAINOFF_CTRL0 0x196a 87 #define VPP2_GAINOFF_CTRL1 0x196b 88 #define VPP2_GAINOFF_CTRL2 0x196c 89 #define VPP2_GAINOFF_CTRL3 0x196d 90 #define VPP2_GAINOFF_CTRL4 0x196e 91 #define VPP2_CHROMA_ADDR_PORT 0x1970 92 #define VPP2_CHROMA_DATA_PORT 0x1971 93 #define VPP2_GCLK_CTRL0 0x1972 94 #define VPP2_GCLK_CTRL1 0x1973 95 #define VPP2_SC_GCLK_CTRL 0x1974 96 #define VPP2_MISC1 0x1976 97 #define VPP2_DNLP_CTRL_00 0x1981 98 #define VPP2_DNLP_CTRL_01 0x1982 99 #define VPP2_DNLP_CTRL_02 0x1983 100 #define VPP2_DNLP_CTRL_03 0x1984 101 #define VPP2_DNLP_CTRL_04 0x1985 102 #define VPP2_DNLP_CTRL_05 0x1986 103 #define VPP2_DNLP_CTRL_06 0x1987 104 #define VPP2_DNLP_CTRL_07 0x1988 105 #define VPP2_DNLP_CTRL_08 0x1989 106 #define VPP2_DNLP_CTRL_09 0x198a 107 #define VPP2_DNLP_CTRL_10 0x198b 108 #define VPP2_DNLP_CTRL_11 0x198c 109 #define VPP2_DNLP_CTRL_12 0x198d 110 #define VPP2_DNLP_CTRL_13 0x198e 111 #define VPP2_DNLP_CTRL_14 0x198f 112 #define VPP2_DNLP_CTRL_15 0x1990 113 #define VPP2_VE_ENABLE_CTRL 0x19a1 114 #define VPP2_VE_DEMO_LEFT_TOP_SCREEN_WIDTH 0x19a2 115 #define VPP2_VE_DEMO_CENTER_BAR 0x19a3 116 #define VPP2_VE_H_V_SIZE 0x19a4 117 #define VPP2_VDO_MEAS_CTRL 0x19a8 118 #define VPP2_VDO_MEAS_VS_COUNT_HI 0x19a9 119 #define VPP2_VDO_MEAS_VS_COUNT_LO 0x19aa 120 #define VPP2_OSD_VSC_PHASE_STEP 0x19c0 121 #define VPP2_OSD_VSC_INI_PHASE 0x19c1 122 #define VPP2_OSD_VSC_CTRL0 0x19c2 123 #define VPP2_OSD_HSC_PHASE_STEP 0x19c3 124 #define VPP2_OSD_HSC_INI_PHASE 0x19c4 125 #define VPP2_OSD_HSC_CTRL0 0x19c5 126 #define VPP2_OSD_HSC_INI_PAT_CTRL 0x19c6 127 #define VPP2_OSD_SC_DUMMY_DATA 0x19c7 128 #define VPP2_OSD_SC_CTRL0 0x19c8 129 #define VPP2_OSD_SCI_WH_M1 0x19c9 130 #define VPP2_OSD_SCO_H_START_END 0x19ca 131 #define VPP2_OSD_SCO_V_START_END 0x19cb 132 #define VPP2_OSD_SCALE_COEF_IDX 0x19cc 133 #define VPP2_OSD_SCALE_COEF 0x19cd 134 #define VPP2_INT_LINE_NUM 0x19ce 135 136 /* viu */ 137 #define VIU_ADDR_START 0x1a00 138 #define VIU_ADDR_END 0x1aff 139 #define VIU_SW_RESET 0x1a01 140 #define VIU_SW_RESET_OSD1 BIT(0) 141 #define VIU_MISC_CTRL0 0x1a06 142 #define VIU_CTRL0_VD1_AFBC_MASK 0x170000 143 #define VIU_MISC_CTRL1 0x1a07 144 #define D2D3_INTF_LENGTH 0x1a08 145 #define D2D3_INTF_CTRL0 0x1a09 146 #define VIU_OSD1_CTRL_STAT 0x1a10 147 #define VIU_OSD1_OSD_BLK_ENABLE BIT(0) 148 #define VIU_OSD1_POSTBLD_SRC_VD1 (1 << 8) 149 #define VIU_OSD1_POSTBLD_SRC_VD2 (2 << 8) 150 #define VIU_OSD1_POSTBLD_SRC_OSD1 (3 << 8) 151 #define VIU_OSD1_POSTBLD_SRC_OSD2 (4 << 8) 152 #define VIU_OSD1_OSD_ENABLE BIT(21) 153 #define VIU_OSD1_CTRL_STAT2 0x1a2d 154 #define VIU_OSD1_COLOR_ADDR 0x1a11 155 #define VIU_OSD1_COLOR 0x1a12 156 #define VIU_OSD1_TCOLOR_AG0 0x1a17 157 #define VIU_OSD1_TCOLOR_AG1 0x1a18 158 #define VIU_OSD1_TCOLOR_AG2 0x1a19 159 #define VIU_OSD1_TCOLOR_AG3 0x1a1a 160 #define VIU_OSD1_BLK0_CFG_W0 0x1a1b 161 #define VIU_OSD1_BLK1_CFG_W0 0x1a1f 162 #define VIU_OSD1_BLK2_CFG_W0 0x1a23 163 #define VIU_OSD1_BLK3_CFG_W0 0x1a27 164 #define VIU_OSD1_BLK0_CFG_W1 0x1a1c 165 #define VIU_OSD1_BLK1_CFG_W1 0x1a20 166 #define VIU_OSD1_BLK2_CFG_W1 0x1a24 167 #define VIU_OSD1_BLK3_CFG_W1 0x1a28 168 #define VIU_OSD1_BLK0_CFG_W2 0x1a1d 169 #define VIU_OSD1_BLK1_CFG_W2 0x1a21 170 #define VIU_OSD1_BLK2_CFG_W2 0x1a25 171 #define VIU_OSD1_BLK3_CFG_W2 0x1a29 172 #define VIU_OSD1_BLK0_CFG_W3 0x1a1e 173 #define VIU_OSD1_BLK1_CFG_W3 0x1a22 174 #define VIU_OSD1_BLK2_CFG_W3 0x1a26 175 #define VIU_OSD1_BLK3_CFG_W3 0x1a2a 176 #define VIU_OSD1_BLK0_CFG_W4 0x1a13 177 #define VIU_OSD1_BLK1_CFG_W4 0x1a14 178 #define VIU_OSD1_BLK2_CFG_W4 0x1a15 179 #define VIU_OSD1_BLK3_CFG_W4 0x1a16 180 #define VIU_OSD1_FIFO_CTRL_STAT 0x1a2b 181 #define VIU_OSD1_TEST_RDDATA 0x1a2c 182 #define VIU_OSD1_PROT_CTRL 0x1a2e 183 #define VIU_OSD2_CTRL_STAT 0x1a30 184 #define VIU_OSD2_CTRL_STAT2 0x1a4d 185 #define VIU_OSD2_COLOR_ADDR 0x1a31 186 #define VIU_OSD2_COLOR 0x1a32 187 #define VIU_OSD2_HL1_H_START_END 0x1a33 188 #define VIU_OSD2_HL1_V_START_END 0x1a34 189 #define VIU_OSD2_HL2_H_START_END 0x1a35 190 #define VIU_OSD2_HL2_V_START_END 0x1a36 191 #define VIU_OSD2_TCOLOR_AG0 0x1a37 192 #define VIU_OSD2_TCOLOR_AG1 0x1a38 193 #define VIU_OSD2_TCOLOR_AG2 0x1a39 194 #define VIU_OSD2_TCOLOR_AG3 0x1a3a 195 #define VIU_OSD2_BLK0_CFG_W0 0x1a3b 196 #define VIU_OSD2_BLK1_CFG_W0 0x1a3f 197 #define VIU_OSD2_BLK2_CFG_W0 0x1a43 198 #define VIU_OSD2_BLK3_CFG_W0 0x1a47 199 #define VIU_OSD2_BLK0_CFG_W1 0x1a3c 200 #define VIU_OSD2_BLK1_CFG_W1 0x1a40 201 #define VIU_OSD2_BLK2_CFG_W1 0x1a44 202 #define VIU_OSD2_BLK3_CFG_W1 0x1a48 203 #define VIU_OSD2_BLK0_CFG_W2 0x1a3d 204 #define VIU_OSD2_BLK1_CFG_W2 0x1a41 205 #define VIU_OSD2_BLK2_CFG_W2 0x1a45 206 #define VIU_OSD2_BLK3_CFG_W2 0x1a49 207 #define VIU_OSD2_BLK0_CFG_W3 0x1a3e 208 #define VIU_OSD2_BLK1_CFG_W3 0x1a42 209 #define VIU_OSD2_BLK2_CFG_W3 0x1a46 210 #define VIU_OSD2_BLK3_CFG_W3 0x1a4a 211 #define VIU_OSD2_BLK0_CFG_W4 0x1a64 212 #define VIU_OSD2_BLK1_CFG_W4 0x1a65 213 #define VIU_OSD2_BLK2_CFG_W4 0x1a66 214 #define VIU_OSD2_BLK3_CFG_W4 0x1a67 215 #define VIU_OSD2_FIFO_CTRL_STAT 0x1a4b 216 #define VIU_OSD2_TEST_RDDATA 0x1a4c 217 #define VIU_OSD2_PROT_CTRL 0x1a4e 218 #define VIU_OSD2_MALI_UNPACK_CTRL 0x1abd 219 #define VIU_OSD2_DIMM_CTRL 0x1acf 220 221 #define VIU_OSD3_CTRL_STAT 0x3d80 222 #define VIU_OSD3_CTRL_STAT2 0x3d81 223 #define VIU_OSD3_COLOR_ADDR 0x3d82 224 #define VIU_OSD3_COLOR 0x3d83 225 #define VIU_OSD3_TCOLOR_AG0 0x3d84 226 #define VIU_OSD3_TCOLOR_AG1 0x3d85 227 #define VIU_OSD3_TCOLOR_AG2 0x3d86 228 #define VIU_OSD3_TCOLOR_AG3 0x3d87 229 #define VIU_OSD3_BLK0_CFG_W0 0x3d88 230 #define VIU_OSD3_BLK0_CFG_W1 0x3d8c 231 #define VIU_OSD3_BLK0_CFG_W2 0x3d90 232 #define VIU_OSD3_BLK0_CFG_W3 0x3d94 233 #define VIU_OSD3_BLK0_CFG_W4 0x3d98 234 #define VIU_OSD3_BLK1_CFG_W4 0x3d99 235 #define VIU_OSD3_BLK2_CFG_W4 0x3d9a 236 #define VIU_OSD3_FIFO_CTRL_STAT 0x3d9c 237 #define VIU_OSD3_TEST_RDDATA 0x3d9d 238 #define VIU_OSD3_PROT_CTRL 0x3d9e 239 #define VIU_OSD3_MALI_UNPACK_CTRL 0x3d9f 240 #define VIU_OSD3_DIMM_CTRL 0x3da0 241 242 #define VIU_OSD_DDR_PRIORITY_URGENT BIT(0) 243 #define VIU_OSD_HOLD_FIFO_LINES(lines) ((lines & 0x1f) << 5) 244 #define VIU_OSD_FIFO_DEPTH_VAL(val) ((val & 0x7f) << 12) 245 #define VIU_OSD_WORDS_PER_BURST(words) (((words & 0x4) >> 1) << 22) 246 #define VIU_OSD_FIFO_LIMITS(size) ((size & 0xf) << 24) 247 248 #define VD1_IF0_GEN_REG 0x1a50 249 #define VD1_IF0_CANVAS0 0x1a51 250 #define VD1_IF0_CANVAS1 0x1a52 251 #define VD1_IF0_LUMA_X0 0x1a53 252 #define VD1_IF0_LUMA_Y0 0x1a54 253 #define VD1_IF0_CHROMA_X0 0x1a55 254 #define VD1_IF0_CHROMA_Y0 0x1a56 255 #define VD1_IF0_LUMA_X1 0x1a57 256 #define VD1_IF0_LUMA_Y1 0x1a58 257 #define VD1_IF0_CHROMA_X1 0x1a59 258 #define VD1_IF0_CHROMA_Y1 0x1a5a 259 #define VD1_IF0_RPT_LOOP 0x1a5b 260 #define VD1_IF0_LUMA0_RPT_PAT 0x1a5c 261 #define VD1_IF0_CHROMA0_RPT_PAT 0x1a5d 262 #define VD1_IF0_LUMA1_RPT_PAT 0x1a5e 263 #define VD1_IF0_CHROMA1_RPT_PAT 0x1a5f 264 #define VD1_IF0_LUMA_PSEL 0x1a60 265 #define VD1_IF0_CHROMA_PSEL 0x1a61 266 #define VD1_IF0_DUMMY_PIXEL 0x1a62 267 #define VD1_IF0_LUMA_FIFO_SIZE 0x1a63 268 #define VD1_IF0_RANGE_MAP_Y 0x1a6a 269 #define VD1_IF0_RANGE_MAP_CB 0x1a6b 270 #define VD1_IF0_RANGE_MAP_CR 0x1a6c 271 #define VD1_IF0_GEN_REG2 0x1a6d 272 #define VD1_IF0_PROT_CNTL 0x1a6e 273 #define VIU_VD1_FMT_CTRL 0x1a68 274 #define VIU_VD1_FMT_W 0x1a69 275 #define VD2_IF0_GEN_REG 0x1a70 276 #define VD2_IF0_CANVAS0 0x1a71 277 #define VD2_IF0_CANVAS1 0x1a72 278 #define VD2_IF0_LUMA_X0 0x1a73 279 #define VD2_IF0_LUMA_Y0 0x1a74 280 #define VD2_IF0_CHROMA_X0 0x1a75 281 #define VD2_IF0_CHROMA_Y0 0x1a76 282 #define VD2_IF0_LUMA_X1 0x1a77 283 #define VD2_IF0_LUMA_Y1 0x1a78 284 #define VD2_IF0_CHROMA_X1 0x1a79 285 #define VD2_IF0_CHROMA_Y1 0x1a7a 286 #define VD2_IF0_RPT_LOOP 0x1a7b 287 #define VD2_IF0_LUMA0_RPT_PAT 0x1a7c 288 #define VD2_IF0_CHROMA0_RPT_PAT 0x1a7d 289 #define VD2_IF0_LUMA1_RPT_PAT 0x1a7e 290 #define VD2_IF0_CHROMA1_RPT_PAT 0x1a7f 291 #define VD2_IF0_LUMA_PSEL 0x1a80 292 #define VD2_IF0_CHROMA_PSEL 0x1a81 293 #define VD2_IF0_DUMMY_PIXEL 0x1a82 294 #define VD2_IF0_LUMA_FIFO_SIZE 0x1a83 295 #define VD2_IF0_RANGE_MAP_Y 0x1a8a 296 #define VD2_IF0_RANGE_MAP_CB 0x1a8b 297 #define VD2_IF0_RANGE_MAP_CR 0x1a8c 298 #define VD2_IF0_GEN_REG2 0x1a8d 299 #define VD2_IF0_PROT_CNTL 0x1a8e 300 #define VIU_VD2_FMT_CTRL 0x1a88 301 #define VIU_VD2_FMT_W 0x1a89 302 303 /* VIU Matrix Registers */ 304 #define VIU_OSD1_MATRIX_CTRL 0x1a90 305 #define VIU_OSD1_MATRIX_COEF00_01 0x1a91 306 #define VIU_OSD1_MATRIX_COEF02_10 0x1a92 307 #define VIU_OSD1_MATRIX_COEF11_12 0x1a93 308 #define VIU_OSD1_MATRIX_COEF20_21 0x1a94 309 #define VIU_OSD1_MATRIX_COLMOD_COEF42 0x1a95 310 #define VIU_OSD1_MATRIX_OFFSET0_1 0x1a96 311 #define VIU_OSD1_MATRIX_OFFSET2 0x1a97 312 #define VIU_OSD1_MATRIX_PRE_OFFSET0_1 0x1a98 313 #define VIU_OSD1_MATRIX_PRE_OFFSET2 0x1a99 314 #define VIU_OSD1_MATRIX_COEF22_30 0x1a9d 315 #define VIU_OSD1_MATRIX_COEF31_32 0x1a9e 316 #define VIU_OSD1_MATRIX_COEF40_41 0x1a9f 317 #define VD1_IF0_GEN_REG3 0x1aa7 318 319 #define VIU_OSD_BLENDO_H_START_END 0x1aa9 320 #define VIU_OSD_BLENDO_V_START_END 0x1aaa 321 #define VIU_OSD_BLEND_GEN_CTRL0 0x1aab 322 #define VIU_OSD_BLEND_GEN_CTRL1 0x1aac 323 #define VIU_OSD_BLEND_DUMMY_DATA 0x1aad 324 #define VIU_OSD_BLEND_CURRENT_XY 0x1aae 325 326 #define VIU_OSD2_MATRIX_CTRL 0x1ab0 327 #define VIU_OSD2_MATRIX_COEF00_01 0x1ab1 328 #define VIU_OSD2_MATRIX_COEF02_10 0x1ab2 329 #define VIU_OSD2_MATRIX_COEF11_12 0x1ab3 330 #define VIU_OSD2_MATRIX_COEF20_21 0x1ab4 331 #define VIU_OSD2_MATRIX_COEF22 0x1ab5 332 #define VIU_OSD2_MATRIX_OFFSET0_1 0x1ab6 333 #define VIU_OSD2_MATRIX_OFFSET2 0x1ab7 334 #define VIU_OSD2_MATRIX_PRE_OFFSET0_1 0x1ab8 335 #define VIU_OSD2_MATRIX_PRE_OFFSET2 0x1ab9 336 #define VIU_OSD2_MATRIX_PROBE_COLOR 0x1aba 337 #define VIU_OSD2_MATRIX_HL_COLOR 0x1abb 338 #define VIU_OSD2_MATRIX_PROBE_POS 0x1abc 339 #define VIU_OSD1_EOTF_CTL 0x1ad4 340 #define VIU_OSD1_EOTF_COEF00_01 0x1ad5 341 #define VIU_OSD1_EOTF_COEF02_10 0x1ad6 342 #define VIU_OSD1_EOTF_COEF11_12 0x1ad7 343 #define VIU_OSD1_EOTF_COEF20_21 0x1ad8 344 #define VIU_OSD1_EOTF_COEF22_RS 0x1ad9 345 #define VIU_OSD1_EOTF_LUT_ADDR_PORT 0x1ada 346 #define VIU_OSD1_EOTF_LUT_DATA_PORT 0x1adb 347 #define VIU_OSD1_OETF_CTL 0x1adc 348 #define VIU_OSD1_OETF_LUT_ADDR_PORT 0x1add 349 #define VIU_OSD1_OETF_LUT_DATA_PORT 0x1ade 350 #define AFBC_ENABLE 0x1ae0 351 352 /* vpp */ 353 #define VPP_DUMMY_DATA 0x1d00 354 #define VPP_LINE_IN_LENGTH 0x1d01 355 #define VPP_PIC_IN_HEIGHT 0x1d02 356 #define VPP_SCALE_COEF_IDX 0x1d03 357 #define VPP_SCALE_HORIZONTAL_COEF BIT(8) 358 #define VPP_SCALE_COEF 0x1d04 359 #define VPP_VSC_REGION12_STARTP 0x1d05 360 #define VPP_VSC_REGION34_STARTP 0x1d06 361 #define VPP_VSC_REGION4_ENDP 0x1d07 362 #define VPP_VSC_START_PHASE_STEP 0x1d08 363 #define VPP_VSC_REGION0_PHASE_SLOPE 0x1d09 364 #define VPP_VSC_REGION1_PHASE_SLOPE 0x1d0a 365 #define VPP_VSC_REGION3_PHASE_SLOPE 0x1d0b 366 #define VPP_VSC_REGION4_PHASE_SLOPE 0x1d0c 367 #define VPP_VSC_PHASE_CTRL 0x1d0d 368 #define VPP_VSC_INI_PHASE 0x1d0e 369 #define VPP_HSC_REGION12_STARTP 0x1d10 370 #define VPP_HSC_REGION34_STARTP 0x1d11 371 #define VPP_HSC_REGION4_ENDP 0x1d12 372 #define VPP_HSC_START_PHASE_STEP 0x1d13 373 #define VPP_HSC_REGION0_PHASE_SLOPE 0x1d14 374 #define VPP_HSC_REGION1_PHASE_SLOPE 0x1d15 375 #define VPP_HSC_REGION3_PHASE_SLOPE 0x1d16 376 #define VPP_HSC_REGION4_PHASE_SLOPE 0x1d17 377 #define VPP_HSC_PHASE_CTRL 0x1d18 378 #define VPP_SC_MISC 0x1d19 379 #define VPP_SC_VD_EN_ENABLE BIT(15) 380 #define VPP_SC_TOP_EN_ENABLE BIT(16) 381 #define VPP_SC_HSC_EN_ENABLE BIT(17) 382 #define VPP_SC_VSC_EN_ENABLE BIT(18) 383 #define VPP_VSC_BANK_LENGTH(length) (length & 0x7) 384 #define VPP_HSC_BANK_LENGTH(length) ((length & 0x7) << 8) 385 #define VPP_PREBLEND_VD1_H_START_END 0x1d1a 386 #define VPP_PREBLEND_VD1_V_START_END 0x1d1b 387 #define VPP_POSTBLEND_VD1_H_START_END 0x1d1c 388 #define VPP_POSTBLEND_VD1_V_START_END 0x1d1d 389 #define VPP_BLEND_VD2_H_START_END 0x1d1e 390 #define VPP_BLEND_VD2_V_START_END 0x1d1f 391 #define VPP_PREBLEND_H_SIZE 0x1d20 392 #define VPP_POSTBLEND_H_SIZE 0x1d21 393 #define VPP_HOLD_LINES 0x1d22 394 #define VPP_POSTBLEND_HOLD_LINES(lines) (lines & 0xf) 395 #define VPP_PREBLEND_HOLD_LINES(lines) ((lines & 0xf) << 8) 396 #define VPP_BLEND_ONECOLOR_CTRL 0x1d23 397 #define VPP_PREBLEND_CURRENT_XY 0x1d24 398 #define VPP_POSTBLEND_CURRENT_XY 0x1d25 399 #define VPP_MISC 0x1d26 400 #define VPP_PREBLEND_ENABLE BIT(6) 401 #define VPP_POSTBLEND_ENABLE BIT(7) 402 #define VPP_OSD2_ALPHA_PREMULT BIT(8) 403 #define VPP_OSD1_ALPHA_PREMULT BIT(9) 404 #define VPP_VD1_POSTBLEND BIT(10) 405 #define VPP_VD2_POSTBLEND BIT(11) 406 #define VPP_OSD1_POSTBLEND BIT(12) 407 #define VPP_OSD2_POSTBLEND BIT(13) 408 #define VPP_VD1_PREBLEND BIT(14) 409 #define VPP_VD2_PREBLEND BIT(15) 410 #define VPP_OSD1_PREBLEND BIT(16) 411 #define VPP_OSD2_PREBLEND BIT(17) 412 #define VPP_COLOR_MNG_ENABLE BIT(28) 413 #define VPP_OFIFO_SIZE 0x1d27 414 #define VPP_OFIFO_SIZE_MASK GENMASK(13, 0) 415 #define VPP_OFIFO_SIZE_DEFAULT (0xfff << 20 | 0x1000) 416 #define VPP_FIFO_STATUS 0x1d28 417 #define VPP_SMOKE_CTRL 0x1d29 418 #define VPP_SMOKE1_VAL 0x1d2a 419 #define VPP_SMOKE2_VAL 0x1d2b 420 #define VPP_SMOKE3_VAL 0x1d2c 421 #define VPP_SMOKE1_H_START_END 0x1d2d 422 #define VPP_SMOKE1_V_START_END 0x1d2e 423 #define VPP_SMOKE2_H_START_END 0x1d2f 424 #define VPP_SMOKE2_V_START_END 0x1d30 425 #define VPP_SMOKE3_H_START_END 0x1d31 426 #define VPP_SMOKE3_V_START_END 0x1d32 427 #define VPP_SCO_FIFO_CTRL 0x1d33 428 #define VPP_HSC_PHASE_CTRL1 0x1d34 429 #define VPP_HSC_INI_PAT_CTRL 0x1d35 430 #define VPP_VADJ_CTRL 0x1d40 431 #define VPP_MINUS_BLACK_LVL_VADJ1_ENABLE BIT(1) 432 433 #define VPP_VADJ1_Y 0x1d41 434 #define VPP_VADJ1_MA_MB 0x1d42 435 #define VPP_VADJ1_MC_MD 0x1d43 436 #define VPP_VADJ2_Y 0x1d44 437 #define VPP_VADJ2_MA_MB 0x1d45 438 #define VPP_VADJ2_MC_MD 0x1d46 439 #define VPP_HSHARP_CTRL 0x1d50 440 #define VPP_HSHARP_LUMA_THRESH01 0x1d51 441 #define VPP_HSHARP_LUMA_THRESH23 0x1d52 442 #define VPP_HSHARP_CHROMA_THRESH01 0x1d53 443 #define VPP_HSHARP_CHROMA_THRESH23 0x1d54 444 #define VPP_HSHARP_LUMA_GAIN 0x1d55 445 #define VPP_HSHARP_CHROMA_GAIN 0x1d56 446 #define VPP_MATRIX_PROBE_COLOR 0x1d5c 447 #define VPP_MATRIX_HL_COLOR 0x1d5d 448 #define VPP_MATRIX_PROBE_POS 0x1d5e 449 #define VPP_MATRIX_CTRL 0x1d5f 450 #define VPP_MATRIX_COEF00_01 0x1d60 451 #define VPP_MATRIX_COEF02_10 0x1d61 452 #define VPP_MATRIX_COEF11_12 0x1d62 453 #define VPP_MATRIX_COEF20_21 0x1d63 454 #define VPP_MATRIX_COEF22 0x1d64 455 #define VPP_MATRIX_OFFSET0_1 0x1d65 456 #define VPP_MATRIX_OFFSET2 0x1d66 457 #define VPP_MATRIX_PRE_OFFSET0_1 0x1d67 458 #define VPP_MATRIX_PRE_OFFSET2 0x1d68 459 #define VPP_DUMMY_DATA1 0x1d69 460 #define VPP_GAINOFF_CTRL0 0x1d6a 461 #define VPP_GAINOFF_CTRL1 0x1d6b 462 #define VPP_GAINOFF_CTRL2 0x1d6c 463 #define VPP_GAINOFF_CTRL3 0x1d6d 464 #define VPP_GAINOFF_CTRL4 0x1d6e 465 #define VPP_CHROMA_ADDR_PORT 0x1d70 466 #define VPP_CHROMA_DATA_PORT 0x1d71 467 #define VPP_GCLK_CTRL0 0x1d72 468 #define VPP_GCLK_CTRL1 0x1d73 469 #define VPP_SC_GCLK_CTRL 0x1d74 470 #define VPP_MISC1 0x1d76 471 #define VPP_BLACKEXT_CTRL 0x1d80 472 #define VPP_DNLP_CTRL_00 0x1d81 473 #define VPP_DNLP_CTRL_01 0x1d82 474 #define VPP_DNLP_CTRL_02 0x1d83 475 #define VPP_DNLP_CTRL_03 0x1d84 476 #define VPP_DNLP_CTRL_04 0x1d85 477 #define VPP_DNLP_CTRL_05 0x1d86 478 #define VPP_DNLP_CTRL_06 0x1d87 479 #define VPP_DNLP_CTRL_07 0x1d88 480 #define VPP_DNLP_CTRL_08 0x1d89 481 #define VPP_DNLP_CTRL_09 0x1d8a 482 #define VPP_DNLP_CTRL_10 0x1d8b 483 #define VPP_DNLP_CTRL_11 0x1d8c 484 #define VPP_DNLP_CTRL_12 0x1d8d 485 #define VPP_DNLP_CTRL_13 0x1d8e 486 #define VPP_DNLP_CTRL_14 0x1d8f 487 #define VPP_DNLP_CTRL_15 0x1d90 488 #define VPP_PEAKING_HGAIN 0x1d91 489 #define VPP_PEAKING_VGAIN 0x1d92 490 #define VPP_PEAKING_NLP_1 0x1d93 491 #define VPP_DOLBY_CTRL 0x1d93 492 #define VPP_PPS_DUMMY_DATA_MODE (1 << 17) 493 #define VPP_PEAKING_NLP_2 0x1d94 494 #define VPP_PEAKING_NLP_3 0x1d95 495 #define VPP_PEAKING_NLP_4 0x1d96 496 #define VPP_PEAKING_NLP_5 0x1d97 497 #define VPP_SHARP_LIMIT 0x1d98 498 #define VPP_VLTI_CTRL 0x1d99 499 #define VPP_HLTI_CTRL 0x1d9a 500 #define VPP_CTI_CTRL 0x1d9b 501 #define VPP_BLUE_STRETCH_1 0x1d9c 502 #define VPP_BLUE_STRETCH_2 0x1d9d 503 #define VPP_BLUE_STRETCH_3 0x1d9e 504 #define VPP_CCORING_CTRL 0x1da0 505 #define VPP_VE_ENABLE_CTRL 0x1da1 506 #define VPP_VE_DEMO_LEFT_TOP_SCREEN_WIDTH 0x1da2 507 #define VPP_VE_DEMO_CENTER_BAR 0x1da3 508 #define VPP_VE_H_V_SIZE 0x1da4 509 #define VPP_VDO_MEAS_CTRL 0x1da8 510 #define VPP_VDO_MEAS_VS_COUNT_HI 0x1da9 511 #define VPP_VDO_MEAS_VS_COUNT_LO 0x1daa 512 #define VPP_INPUT_CTRL 0x1dab 513 #define VPP_CTI_CTRL2 0x1dac 514 #define VPP_PEAKING_SAT_THD1 0x1dad 515 #define VPP_PEAKING_SAT_THD2 0x1dae 516 #define VPP_PEAKING_SAT_THD3 0x1daf 517 #define VPP_PEAKING_SAT_THD4 0x1db0 518 #define VPP_PEAKING_SAT_THD5 0x1db1 519 #define VPP_PEAKING_SAT_THD6 0x1db2 520 #define VPP_PEAKING_SAT_THD7 0x1db3 521 #define VPP_PEAKING_SAT_THD8 0x1db4 522 #define VPP_PEAKING_SAT_THD9 0x1db5 523 #define VPP_PEAKING_GAIN_ADD1 0x1db6 524 #define VPP_PEAKING_GAIN_ADD2 0x1db7 525 #define VPP_PEAKING_DNLP 0x1db8 526 #define VPP_SHARP_DEMO_WIN_CTRL1 0x1db9 527 #define VPP_SHARP_DEMO_WIN_CTRL2 0x1dba 528 #define VPP_FRONT_HLTI_CTRL 0x1dbb 529 #define VPP_FRONT_CTI_CTRL 0x1dbc 530 #define VPP_FRONT_CTI_CTRL2 0x1dbd 531 #define VPP_OSD_VSC_PHASE_STEP 0x1dc0 532 #define VPP_OSD_VSC_INI_PHASE 0x1dc1 533 #define VPP_OSD_VSC_CTRL0 0x1dc2 534 #define VPP_OSD_HSC_PHASE_STEP 0x1dc3 535 #define VPP_OSD_HSC_INI_PHASE 0x1dc4 536 #define VPP_OSD_HSC_CTRL0 0x1dc5 537 #define VPP_OSD_HSC_INI_PAT_CTRL 0x1dc6 538 #define VPP_OSD_SC_DUMMY_DATA 0x1dc7 539 #define VPP_OSD_SC_CTRL0 0x1dc8 540 #define VPP_OSD_SCI_WH_M1 0x1dc9 541 #define VPP_OSD_SCO_H_START_END 0x1dca 542 #define VPP_OSD_SCO_V_START_END 0x1dcb 543 #define VPP_OSD_SCALE_COEF_IDX 0x1dcc 544 #define VPP_OSD_SCALE_COEF 0x1dcd 545 #define VPP_INT_LINE_NUM 0x1dce 546 547 #define VPP_WRAP_OSD1_MATRIX_COEF00_01 0x3d60 548 #define VPP_WRAP_OSD1_MATRIX_COEF02_10 0x3d61 549 #define VPP_WRAP_OSD1_MATRIX_COEF11_12 0x3d62 550 #define VPP_WRAP_OSD1_MATRIX_COEF20_21 0x3d63 551 #define VPP_WRAP_OSD1_MATRIX_COEF22 0x3d64 552 #define VPP_WRAP_OSD1_MATRIX_COEF13_14 0x3d65 553 #define VPP_WRAP_OSD1_MATRIX_COEF23_24 0x3d66 554 #define VPP_WRAP_OSD1_MATRIX_COEF15_25 0x3d67 555 #define VPP_WRAP_OSD1_MATRIX_CLIP 0x3d68 556 #define VPP_WRAP_OSD1_MATRIX_OFFSET0_1 0x3d69 557 #define VPP_WRAP_OSD1_MATRIX_OFFSET2 0x3d6a 558 #define VPP_WRAP_OSD1_MATRIX_PRE_OFFSET0_1 0x3d6b 559 #define VPP_WRAP_OSD1_MATRIX_PRE_OFFSET2 0x3d6c 560 #define VPP_WRAP_OSD1_MATRIX_EN_CTRL 0x3d6d 561 562 #define VPP_WRAP_OSD2_MATRIX_COEF00_01 0x3d70 563 #define VPP_WRAP_OSD2_MATRIX_COEF02_10 0x3d71 564 #define VPP_WRAP_OSD2_MATRIX_COEF11_12 0x3d72 565 #define VPP_WRAP_OSD2_MATRIX_COEF20_21 0x3d73 566 #define VPP_WRAP_OSD2_MATRIX_COEF22 0x3d74 567 #define VPP_WRAP_OSD2_MATRIX_COEF13_14 0x3d75 568 #define VPP_WRAP_OSD2_MATRIX_COEF23_24 0x3d76 569 #define VPP_WRAP_OSD2_MATRIX_COEF15_25 0x3d77 570 #define VPP_WRAP_OSD2_MATRIX_CLIP 0x3d78 571 #define VPP_WRAP_OSD2_MATRIX_OFFSET0_1 0x3d79 572 #define VPP_WRAP_OSD2_MATRIX_OFFSET2 0x3d7a 573 #define VPP_WRAP_OSD2_MATRIX_PRE_OFFSET0_1 0x3d7b 574 #define VPP_WRAP_OSD2_MATRIX_PRE_OFFSET2 0x3d7c 575 #define VPP_WRAP_OSD2_MATRIX_EN_CTRL 0x3d7d 576 577 #define VPP_WRAP_OSD3_MATRIX_COEF00_01 0x3db0 578 #define VPP_WRAP_OSD3_MATRIX_COEF02_10 0x3db1 579 #define VPP_WRAP_OSD3_MATRIX_COEF11_12 0x3db2 580 #define VPP_WRAP_OSD3_MATRIX_COEF20_21 0x3db3 581 #define VPP_WRAP_OSD3_MATRIX_COEF22 0x3db4 582 #define VPP_WRAP_OSD3_MATRIX_COEF13_14 0x3db5 583 #define VPP_WRAP_OSD3_MATRIX_COEF23_24 0x3db6 584 #define VPP_WRAP_OSD3_MATRIX_COEF15_25 0x3db7 585 #define VPP_WRAP_OSD3_MATRIX_CLIP 0x3db8 586 #define VPP_WRAP_OSD3_MATRIX_OFFSET0_1 0x3db9 587 #define VPP_WRAP_OSD3_MATRIX_OFFSET2 0x3dba 588 #define VPP_WRAP_OSD3_MATRIX_PRE_OFFSET0_1 0x3dbb 589 #define VPP_WRAP_OSD3_MATRIX_PRE_OFFSET2 0x3dbc 590 #define VPP_WRAP_OSD3_MATRIX_EN_CTRL 0x3dbd 591 592 /* osd2 scaler */ 593 #define OSD2_VSC_PHASE_STEP 0x3d00 594 #define OSD2_VSC_INI_PHASE 0x3d01 595 #define OSD2_VSC_CTRL0 0x3d02 596 #define OSD2_HSC_PHASE_STEP 0x3d03 597 #define OSD2_HSC_INI_PHASE 0x3d04 598 #define OSD2_HSC_CTRL0 0x3d05 599 #define OSD2_HSC_INI_PAT_CTRL 0x3d06 600 #define OSD2_SC_DUMMY_DATA 0x3d07 601 #define OSD2_SC_CTRL0 0x3d08 602 #define OSD2_SCI_WH_M1 0x3d09 603 #define OSD2_SCO_H_START_END 0x3d0a 604 #define OSD2_SCO_V_START_END 0x3d0b 605 #define OSD2_SCALE_COEF_IDX 0x3d18 606 #define OSD2_SCALE_COEF 0x3d19 607 608 /* osd34 scaler */ 609 #define OSD34_SCALE_COEF_IDX 0x3d1e 610 #define OSD34_SCALE_COEF 0x3d1f 611 #define OSD34_VSC_PHASE_STEP 0x3d20 612 #define OSD34_VSC_INI_PHASE 0x3d21 613 #define OSD34_VSC_CTRL0 0x3d22 614 #define OSD34_HSC_PHASE_STEP 0x3d23 615 #define OSD34_HSC_INI_PHASE 0x3d24 616 #define OSD34_HSC_CTRL0 0x3d25 617 #define OSD34_HSC_INI_PAT_CTRL 0x3d26 618 #define OSD34_SC_DUMMY_DATA 0x3d27 619 #define OSD34_SC_CTRL0 0x3d28 620 #define OSD34_SCI_WH_M1 0x3d29 621 #define OSD34_SCO_H_START_END 0x3d2a 622 #define OSD34_SCO_V_START_END 0x3d2b 623 624 /* viu2 */ 625 #define VIU2_ADDR_START 0x1e00 626 #define VIU2_ADDR_END 0x1eff 627 #define VIU2_SW_RESET 0x1e01 628 #define VIU2_OSD1_CTRL_STAT 0x1e10 629 #define VIU2_OSD1_CTRL_STAT2 0x1e2d 630 #define VIU2_OSD1_COLOR_ADDR 0x1e11 631 #define VIU2_OSD1_COLOR 0x1e12 632 #define VIU2_OSD1_TCOLOR_AG0 0x1e17 633 #define VIU2_OSD1_TCOLOR_AG1 0x1e18 634 #define VIU2_OSD1_TCOLOR_AG2 0x1e19 635 #define VIU2_OSD1_TCOLOR_AG3 0x1e1a 636 #define VIU2_OSD1_BLK0_CFG_W0 0x1e1b 637 #define VIU2_OSD1_BLK1_CFG_W0 0x1e1f 638 #define VIU2_OSD1_BLK2_CFG_W0 0x1e23 639 #define VIU2_OSD1_BLK3_CFG_W0 0x1e27 640 #define VIU2_OSD1_BLK0_CFG_W1 0x1e1c 641 #define VIU2_OSD1_BLK1_CFG_W1 0x1e20 642 #define VIU2_OSD1_BLK2_CFG_W1 0x1e24 643 #define VIU2_OSD1_BLK3_CFG_W1 0x1e28 644 #define VIU2_OSD1_BLK0_CFG_W2 0x1e1d 645 #define VIU2_OSD1_BLK1_CFG_W2 0x1e21 646 #define VIU2_OSD1_BLK2_CFG_W2 0x1e25 647 #define VIU2_OSD1_BLK3_CFG_W2 0x1e29 648 #define VIU2_OSD1_BLK0_CFG_W3 0x1e1e 649 #define VIU2_OSD1_BLK1_CFG_W3 0x1e22 650 #define VIU2_OSD1_BLK2_CFG_W3 0x1e26 651 #define VIU2_OSD1_BLK3_CFG_W3 0x1e2a 652 #define VIU2_OSD1_BLK0_CFG_W4 0x1e13 653 #define VIU2_OSD1_BLK1_CFG_W4 0x1e14 654 #define VIU2_OSD1_BLK2_CFG_W4 0x1e15 655 #define VIU2_OSD1_BLK3_CFG_W4 0x1e16 656 #define VIU2_OSD1_FIFO_CTRL_STAT 0x1e2b 657 #define VIU2_OSD1_TEST_RDDATA 0x1e2c 658 #define VIU2_OSD1_PROT_CTRL 0x1e2e 659 #define VIU2_OSD2_CTRL_STAT 0x1e30 660 #define VIU2_OSD2_CTRL_STAT2 0x1e4d 661 #define VIU2_OSD2_COLOR_ADDR 0x1e31 662 #define VIU2_OSD2_COLOR 0x1e32 663 #define VIU2_OSD2_HL1_H_START_END 0x1e33 664 #define VIU2_OSD2_HL1_V_START_END 0x1e34 665 #define VIU2_OSD2_HL2_H_START_END 0x1e35 666 #define VIU2_OSD2_HL2_V_START_END 0x1e36 667 #define VIU2_OSD2_TCOLOR_AG0 0x1e37 668 #define VIU2_OSD2_TCOLOR_AG1 0x1e38 669 #define VIU2_OSD2_TCOLOR_AG2 0x1e39 670 #define VIU2_OSD2_TCOLOR_AG3 0x1e3a 671 #define VIU2_OSD2_BLK0_CFG_W0 0x1e3b 672 #define VIU2_OSD2_BLK1_CFG_W0 0x1e3f 673 #define VIU2_OSD2_BLK2_CFG_W0 0x1e43 674 #define VIU2_OSD2_BLK3_CFG_W0 0x1e47 675 #define VIU2_OSD2_BLK0_CFG_W1 0x1e3c 676 #define VIU2_OSD2_BLK1_CFG_W1 0x1e40 677 #define VIU2_OSD2_BLK2_CFG_W1 0x1e44 678 #define VIU2_OSD2_BLK3_CFG_W1 0x1e48 679 #define VIU2_OSD2_BLK0_CFG_W2 0x1e3d 680 #define VIU2_OSD2_BLK1_CFG_W2 0x1e41 681 #define VIU2_OSD2_BLK2_CFG_W2 0x1e45 682 #define VIU2_OSD2_BLK3_CFG_W2 0x1e49 683 #define VIU2_OSD2_BLK0_CFG_W3 0x1e3e 684 #define VIU2_OSD2_BLK1_CFG_W3 0x1e42 685 #define VIU2_OSD2_BLK2_CFG_W3 0x1e46 686 #define VIU2_OSD2_BLK3_CFG_W3 0x1e4a 687 #define VIU2_OSD2_BLK0_CFG_W4 0x1e64 688 #define VIU2_OSD2_BLK1_CFG_W4 0x1e65 689 #define VIU2_OSD2_BLK2_CFG_W4 0x1e66 690 #define VIU2_OSD2_BLK3_CFG_W4 0x1e67 691 #define VIU2_OSD2_FIFO_CTRL_STAT 0x1e4b 692 #define VIU2_OSD2_TEST_RDDATA 0x1e4c 693 #define VIU2_OSD2_PROT_CTRL 0x1e4e 694 #define VIU2_VD1_IF0_GEN_REG 0x1e50 695 #define VIU2_VD1_IF0_CANVAS0 0x1e51 696 #define VIU2_VD1_IF0_CANVAS1 0x1e52 697 #define VIU2_VD1_IF0_LUMA_X0 0x1e53 698 #define VIU2_VD1_IF0_LUMA_Y0 0x1e54 699 #define VIU2_VD1_IF0_CHROMA_X0 0x1e55 700 #define VIU2_VD1_IF0_CHROMA_Y0 0x1e56 701 #define VIU2_VD1_IF0_LUMA_X1 0x1e57 702 #define VIU2_VD1_IF0_LUMA_Y1 0x1e58 703 #define VIU2_VD1_IF0_CHROMA_X1 0x1e59 704 #define VIU2_VD1_IF0_CHROMA_Y1 0x1e5a 705 #define VIU2_VD1_IF0_RPT_LOOP 0x1e5b 706 #define VIU2_VD1_IF0_LUMA0_RPT_PAT 0x1e5c 707 #define VIU2_VD1_IF0_CHROMA0_RPT_PAT 0x1e5d 708 #define VIU2_VD1_IF0_LUMA1_RPT_PAT 0x1e5e 709 #define VIU2_VD1_IF0_CHROMA1_RPT_PAT 0x1e5f 710 #define VIU2_VD1_IF0_LUMA_PSEL 0x1e60 711 #define VIU2_VD1_IF0_CHROMA_PSEL 0x1e61 712 #define VIU2_VD1_IF0_DUMMY_PIXEL 0x1e62 713 #define VIU2_VD1_IF0_LUMA_FIFO_SIZE 0x1e63 714 #define VIU2_VD1_IF0_RANGE_MAP_Y 0x1e6a 715 #define VIU2_VD1_IF0_RANGE_MAP_CB 0x1e6b 716 #define VIU2_VD1_IF0_RANGE_MAP_CR 0x1e6c 717 #define VIU2_VD1_IF0_GEN_REG2 0x1e6d 718 #define VIU2_VD1_IF0_PROT_CNTL 0x1e6e 719 #define VIU2_VD1_FMT_CTRL 0x1e68 720 #define VIU2_VD1_FMT_W 0x1e69 721 722 /* encode */ 723 #define ENCP_VFIFO2VD_CTL 0x1b58 724 #define ENCP_VFIFO2VD_PIXEL_START 0x1b59 725 #define ENCP_VFIFO2VD_PIXEL_END 0x1b5a 726 #define ENCP_VFIFO2VD_LINE_TOP_START 0x1b5b 727 #define ENCP_VFIFO2VD_LINE_TOP_END 0x1b5c 728 #define ENCP_VFIFO2VD_LINE_BOT_START 0x1b5d 729 #define ENCP_VFIFO2VD_LINE_BOT_END 0x1b5e 730 #define VENC_SYNC_ROUTE 0x1b60 731 #define VENC_VIDEO_EXSRC 0x1b61 732 #define VENC_DVI_SETTING 0x1b62 733 #define VENC_C656_CTRL 0x1b63 734 #define VENC_UPSAMPLE_CTRL0 0x1b64 735 #define VENC_UPSAMPLE_CTRL1 0x1b65 736 #define VENC_UPSAMPLE_CTRL2 0x1b66 737 #define VENC_UPSAMPLE_CTRL_F0_2_CLK_RATIO BIT(0) 738 #define VENC_UPSAMPLE_CTRL_F1_EN BIT(5) 739 #define VENC_UPSAMPLE_CTRL_F1_UPSAMPLE_EN BIT(6) 740 #define VENC_UPSAMPLE_CTRL_INTERLACE_HIGH_LUMA (0x0 << 12) 741 #define VENC_UPSAMPLE_CTRL_CVBS (0x1 << 12) 742 #define VENC_UPSAMPLE_CTRL_S_VIDEO_LUMA (0x2 << 12) 743 #define VENC_UPSAMPLE_CTRL_S_VIDEO_CHROMA (0x3 << 12) 744 #define VENC_UPSAMPLE_CTRL_INTERLACE_PB (0x4 << 12) 745 #define VENC_UPSAMPLE_CTRL_INTERLACE_PR (0x5 << 12) 746 #define VENC_UPSAMPLE_CTRL_INTERLACE_R (0x6 << 12) 747 #define VENC_UPSAMPLE_CTRL_INTERLACE_G (0x7 << 12) 748 #define VENC_UPSAMPLE_CTRL_INTERLACE_B (0x8 << 12) 749 #define VENC_UPSAMPLE_CTRL_PROGRESSIVE_Y (0x9 << 12) 750 #define VENC_UPSAMPLE_CTRL_PROGRESSIVE_PB (0xa << 12) 751 #define VENC_UPSAMPLE_CTRL_PROGRESSIVE_PR (0xb << 12) 752 #define VENC_UPSAMPLE_CTRL_PROGRESSIVE_R (0xc << 12) 753 #define VENC_UPSAMPLE_CTRL_PROGRESSIVE_G (0xd << 12) 754 #define VENC_UPSAMPLE_CTRL_PROGRESSIVE_B (0xe << 12) 755 #define VENC_UPSAMPLE_CTRL_VDAC_TEST_VALUE (0xf << 12) 756 #define TCON_INVERT_CTL 0x1b67 757 #define VENC_VIDEO_PROG_MODE 0x1b68 758 #define VENC_ENCI_LINE 0x1b69 759 #define VENC_ENCI_PIXEL 0x1b6a 760 #define VENC_ENCP_LINE 0x1b6b 761 #define VENC_ENCP_PIXEL 0x1b6c 762 #define VENC_STATA 0x1b6d 763 #define VENC_INTCTRL 0x1b6e 764 #define VENC_INTCTRL_ENCI_LNRST_INT_EN BIT(1) 765 #define VENC_INTFLAG 0x1b6f 766 #define VENC_VIDEO_TST_EN 0x1b70 767 #define VENC_VIDEO_TST_MDSEL 0x1b71 768 #define VENC_VIDEO_TST_Y 0x1b72 769 #define VENC_VIDEO_TST_CB 0x1b73 770 #define VENC_VIDEO_TST_CR 0x1b74 771 #define VENC_VIDEO_TST_CLRBAR_STRT 0x1b75 772 #define VENC_VIDEO_TST_CLRBAR_WIDTH 0x1b76 773 #define VENC_VIDEO_TST_VDCNT_STSET 0x1b77 774 #define VENC_VDAC_DACSEL0 0x1b78 775 #define VENC_VDAC_SEL_ATV_DMD BIT(5) 776 #define VENC_VDAC_DACSEL1 0x1b79 777 #define VENC_VDAC_DACSEL2 0x1b7a 778 #define VENC_VDAC_DACSEL3 0x1b7b 779 #define VENC_VDAC_DACSEL4 0x1b7c 780 #define VENC_VDAC_DACSEL5 0x1b7d 781 #define VENC_VDAC_SETTING 0x1b7e 782 #define VENC_VDAC_TST_VAL 0x1b7f 783 #define VENC_VDAC_DAC0_GAINCTRL 0x1bf0 784 #define VENC_VDAC_DAC0_OFFSET 0x1bf1 785 #define VENC_VDAC_DAC1_GAINCTRL 0x1bf2 786 #define VENC_VDAC_DAC1_OFFSET 0x1bf3 787 #define VENC_VDAC_DAC2_GAINCTRL 0x1bf4 788 #define VENC_VDAC_DAC2_OFFSET 0x1bf5 789 #define VENC_VDAC_DAC3_GAINCTRL 0x1bf6 790 #define VENC_VDAC_DAC3_OFFSET 0x1bf7 791 #define VENC_VDAC_DAC4_GAINCTRL 0x1bf8 792 #define VENC_VDAC_DAC4_OFFSET 0x1bf9 793 #define VENC_VDAC_DAC5_GAINCTRL 0x1bfa 794 #define VENC_VDAC_DAC5_OFFSET 0x1bfb 795 #define VENC_VDAC_FIFO_CTRL 0x1bfc 796 #define VENC_VDAC_FIFO_EN_ENCI_ENABLE BIT(13) 797 #define ENCL_TCON_INVERT_CTL 0x1bfd 798 #define ENCP_VIDEO_EN 0x1b80 799 #define ENCP_VIDEO_SYNC_MODE 0x1b81 800 #define ENCP_MACV_EN 0x1b82 801 #define ENCP_VIDEO_Y_SCL 0x1b83 802 #define ENCP_VIDEO_PB_SCL 0x1b84 803 #define ENCP_VIDEO_PR_SCL 0x1b85 804 #define ENCP_VIDEO_SYNC_SCL 0x1b86 805 #define ENCP_VIDEO_MACV_SCL 0x1b87 806 #define ENCP_VIDEO_Y_OFFST 0x1b88 807 #define ENCP_VIDEO_PB_OFFST 0x1b89 808 #define ENCP_VIDEO_PR_OFFST 0x1b8a 809 #define ENCP_VIDEO_SYNC_OFFST 0x1b8b 810 #define ENCP_VIDEO_MACV_OFFST 0x1b8c 811 #define ENCP_VIDEO_MODE 0x1b8d 812 #define ENCP_VIDEO_MODE_DE_V_HIGH BIT(14) 813 #define ENCP_VIDEO_MODE_ADV 0x1b8e 814 #define ENCP_DBG_PX_RST 0x1b90 815 #define ENCP_DBG_LN_RST 0x1b91 816 #define ENCP_DBG_PX_INT 0x1b92 817 #define ENCP_DBG_LN_INT 0x1b93 818 #define ENCP_VIDEO_YFP1_HTIME 0x1b94 819 #define ENCP_VIDEO_YFP2_HTIME 0x1b95 820 #define ENCP_VIDEO_YC_DLY 0x1b96 821 #define ENCP_VIDEO_MAX_PXCNT 0x1b97 822 #define ENCP_VIDEO_HSPULS_BEGIN 0x1b98 823 #define ENCP_VIDEO_HSPULS_END 0x1b99 824 #define ENCP_VIDEO_HSPULS_SWITCH 0x1b9a 825 #define ENCP_VIDEO_VSPULS_BEGIN 0x1b9b 826 #define ENCP_VIDEO_VSPULS_END 0x1b9c 827 #define ENCP_VIDEO_VSPULS_BLINE 0x1b9d 828 #define ENCP_VIDEO_VSPULS_ELINE 0x1b9e 829 #define ENCP_VIDEO_EQPULS_BEGIN 0x1b9f 830 #define ENCP_VIDEO_EQPULS_END 0x1ba0 831 #define ENCP_VIDEO_EQPULS_BLINE 0x1ba1 832 #define ENCP_VIDEO_EQPULS_ELINE 0x1ba2 833 #define ENCP_VIDEO_HAVON_END 0x1ba3 834 #define ENCP_VIDEO_HAVON_BEGIN 0x1ba4 835 #define ENCP_VIDEO_VAVON_ELINE 0x1baf 836 #define ENCP_VIDEO_VAVON_BLINE 0x1ba6 837 #define ENCP_VIDEO_HSO_BEGIN 0x1ba7 838 #define ENCP_VIDEO_HSO_END 0x1ba8 839 #define ENCP_VIDEO_VSO_BEGIN 0x1ba9 840 #define ENCP_VIDEO_VSO_END 0x1baa 841 #define ENCP_VIDEO_VSO_BLINE 0x1bab 842 #define ENCP_VIDEO_VSO_ELINE 0x1bac 843 #define ENCP_VIDEO_SYNC_WAVE_CURVE 0x1bad 844 #define ENCP_VIDEO_MAX_LNCNT 0x1bae 845 #define ENCP_VIDEO_SY_VAL 0x1bb0 846 #define ENCP_VIDEO_SY2_VAL 0x1bb1 847 #define ENCP_VIDEO_BLANKY_VAL 0x1bb2 848 #define ENCP_VIDEO_BLANKPB_VAL 0x1bb3 849 #define ENCP_VIDEO_BLANKPR_VAL 0x1bb4 850 #define ENCP_VIDEO_HOFFST 0x1bb5 851 #define ENCP_VIDEO_VOFFST 0x1bb6 852 #define ENCP_VIDEO_RGB_CTRL 0x1bb7 853 #define ENCP_VIDEO_FILT_CTRL 0x1bb8 854 #define ENCP_VIDEO_OFLD_VPEQ_OFST 0x1bb9 855 #define ENCP_VIDEO_OFLD_VOAV_OFST 0x1bba 856 #define ENCP_VIDEO_MATRIX_CB 0x1bbb 857 #define ENCP_VIDEO_MATRIX_CR 0x1bbc 858 #define ENCP_VIDEO_RGBIN_CTRL 0x1bbd 859 #define ENCP_MACV_BLANKY_VAL 0x1bc0 860 #define ENCP_MACV_MAXY_VAL 0x1bc1 861 #define ENCP_MACV_1ST_PSSYNC_STRT 0x1bc2 862 #define ENCP_MACV_PSSYNC_STRT 0x1bc3 863 #define ENCP_MACV_AGC_STRT 0x1bc4 864 #define ENCP_MACV_AGC_END 0x1bc5 865 #define ENCP_MACV_WAVE_END 0x1bc6 866 #define ENCP_MACV_STRTLINE 0x1bc7 867 #define ENCP_MACV_ENDLINE 0x1bc8 868 #define ENCP_MACV_TS_CNT_MAX_L 0x1bc9 869 #define ENCP_MACV_TS_CNT_MAX_H 0x1bca 870 #define ENCP_MACV_TIME_DOWN 0x1bcb 871 #define ENCP_MACV_TIME_LO 0x1bcc 872 #define ENCP_MACV_TIME_UP 0x1bcd 873 #define ENCP_MACV_TIME_RST 0x1bce 874 #define ENCP_VBI_CTRL 0x1bd0 875 #define ENCP_VBI_SETTING 0x1bd1 876 #define ENCP_VBI_BEGIN 0x1bd2 877 #define ENCP_VBI_WIDTH 0x1bd3 878 #define ENCP_VBI_HVAL 0x1bd4 879 #define ENCP_VBI_DATA0 0x1bd5 880 #define ENCP_VBI_DATA1 0x1bd6 881 #define C656_HS_ST 0x1be0 882 #define C656_HS_ED 0x1be1 883 #define C656_VS_LNST_E 0x1be2 884 #define C656_VS_LNST_O 0x1be3 885 #define C656_VS_LNED_E 0x1be4 886 #define C656_VS_LNED_O 0x1be5 887 #define C656_FS_LNST 0x1be6 888 #define C656_FS_LNED 0x1be7 889 #define ENCI_VIDEO_MODE 0x1b00 890 #define ENCI_VIDEO_MODE_ADV 0x1b01 891 #define ENCI_VIDEO_MODE_ADV_DMXMD(val) (val & 0x3) 892 #define ENCI_VIDEO_MODE_ADV_VBICTL_LINE_17_22 BIT(2) 893 #define ENCI_VIDEO_MODE_ADV_YBW_MEDIUM (0 << 4) 894 #define ENCI_VIDEO_MODE_ADV_YBW_LOW (0x1 << 4) 895 #define ENCI_VIDEO_MODE_ADV_YBW_HIGH (0x2 << 4) 896 #define ENCI_VIDEO_FSC_ADJ 0x1b02 897 #define ENCI_VIDEO_BRIGHT 0x1b03 898 #define ENCI_VIDEO_CONT 0x1b04 899 #define ENCI_VIDEO_SAT 0x1b05 900 #define ENCI_VIDEO_HUE 0x1b06 901 #define ENCI_VIDEO_SCH 0x1b07 902 #define ENCI_SYNC_MODE 0x1b08 903 #define ENCI_SYNC_CTRL 0x1b09 904 #define ENCI_SYNC_HSO_BEGIN 0x1b0a 905 #define ENCI_SYNC_HSO_END 0x1b0b 906 #define ENCI_SYNC_VSO_EVN 0x1b0c 907 #define ENCI_SYNC_VSO_ODD 0x1b0d 908 #define ENCI_SYNC_VSO_EVNLN 0x1b0e 909 #define ENCI_SYNC_VSO_ODDLN 0x1b0f 910 #define ENCI_SYNC_HOFFST 0x1b10 911 #define ENCI_SYNC_VOFFST 0x1b11 912 #define ENCI_SYNC_ADJ 0x1b12 913 #define ENCI_RGB_SETTING 0x1b13 914 #define ENCI_DE_H_BEGIN 0x1b16 915 #define ENCI_DE_H_END 0x1b17 916 #define ENCI_DE_V_BEGIN_EVEN 0x1b18 917 #define ENCI_DE_V_END_EVEN 0x1b19 918 #define ENCI_DE_V_BEGIN_ODD 0x1b1a 919 #define ENCI_DE_V_END_ODD 0x1b1b 920 #define ENCI_VBI_SETTING 0x1b20 921 #define ENCI_VBI_CCDT_EVN 0x1b21 922 #define ENCI_VBI_CCDT_ODD 0x1b22 923 #define ENCI_VBI_CC525_LN 0x1b23 924 #define ENCI_VBI_CC625_LN 0x1b24 925 #define ENCI_VBI_WSSDT 0x1b25 926 #define ENCI_VBI_WSS_LN 0x1b26 927 #define ENCI_VBI_CGMSDT_L 0x1b27 928 #define ENCI_VBI_CGMSDT_H 0x1b28 929 #define ENCI_VBI_CGMS_LN 0x1b29 930 #define ENCI_VBI_TTX_HTIME 0x1b2a 931 #define ENCI_VBI_TTX_LN 0x1b2b 932 #define ENCI_VBI_TTXDT0 0x1b2c 933 #define ENCI_VBI_TTXDT1 0x1b2d 934 #define ENCI_VBI_TTXDT2 0x1b2e 935 #define ENCI_VBI_TTXDT3 0x1b2f 936 #define ENCI_MACV_N0 0x1b30 937 #define ENCI_MACV_N1 0x1b31 938 #define ENCI_MACV_N2 0x1b32 939 #define ENCI_MACV_N3 0x1b33 940 #define ENCI_MACV_N4 0x1b34 941 #define ENCI_MACV_N5 0x1b35 942 #define ENCI_MACV_N6 0x1b36 943 #define ENCI_MACV_N7 0x1b37 944 #define ENCI_MACV_N8 0x1b38 945 #define ENCI_MACV_N9 0x1b39 946 #define ENCI_MACV_N10 0x1b3a 947 #define ENCI_MACV_N11 0x1b3b 948 #define ENCI_MACV_N12 0x1b3c 949 #define ENCI_MACV_N13 0x1b3d 950 #define ENCI_MACV_N14 0x1b3e 951 #define ENCI_MACV_N15 0x1b3f 952 #define ENCI_MACV_N16 0x1b40 953 #define ENCI_MACV_N17 0x1b41 954 #define ENCI_MACV_N18 0x1b42 955 #define ENCI_MACV_N19 0x1b43 956 #define ENCI_MACV_N20 0x1b44 957 #define ENCI_MACV_N21 0x1b45 958 #define ENCI_MACV_N22 0x1b46 959 #define ENCI_DBG_PX_RST 0x1b48 960 #define ENCI_DBG_FLDLN_RST 0x1b49 961 #define ENCI_DBG_PX_INT 0x1b4a 962 #define ENCI_DBG_FLDLN_INT 0x1b4b 963 #define ENCI_DBG_MAXPX 0x1b4c 964 #define ENCI_DBG_MAXLN 0x1b4d 965 #define ENCI_MACV_MAX_AMP 0x1b50 966 #define ENCI_MACV_MAX_AMP_ENABLE_CHANGE BIT(15) 967 #define ENCI_MACV_MAX_AMP_VAL(val) (val & 0x83ff) 968 #define ENCI_MACV_PULSE_LO 0x1b51 969 #define ENCI_MACV_PULSE_HI 0x1b52 970 #define ENCI_MACV_BKP_MAX 0x1b53 971 #define ENCI_CFILT_CTRL 0x1b54 972 #define ENCI_CFILT_CMPT_SEL_HIGH BIT(1) 973 #define ENCI_CFILT7 0x1b55 974 #define ENCI_YC_DELAY 0x1b56 975 #define ENCI_VIDEO_EN 0x1b57 976 #define ENCI_VIDEO_EN_ENABLE BIT(0) 977 #define ENCI_DVI_HSO_BEGIN 0x1c00 978 #define ENCI_DVI_HSO_END 0x1c01 979 #define ENCI_DVI_VSO_BLINE_EVN 0x1c02 980 #define ENCI_DVI_VSO_BLINE_ODD 0x1c03 981 #define ENCI_DVI_VSO_ELINE_EVN 0x1c04 982 #define ENCI_DVI_VSO_ELINE_ODD 0x1c05 983 #define ENCI_DVI_VSO_BEGIN_EVN 0x1c06 984 #define ENCI_DVI_VSO_BEGIN_ODD 0x1c07 985 #define ENCI_DVI_VSO_END_EVN 0x1c08 986 #define ENCI_DVI_VSO_END_ODD 0x1c09 987 #define ENCI_CFILT_CTRL2 0x1c0a 988 #define ENCI_CFILT_CMPT_CR_DLY(delay) (delay & 0xf) 989 #define ENCI_CFILT_CMPT_CB_DLY(delay) ((delay & 0xf) << 4) 990 #define ENCI_CFILT_CVBS_CR_DLY(delay) ((delay & 0xf) << 8) 991 #define ENCI_CFILT_CVBS_CB_DLY(delay) ((delay & 0xf) << 12) 992 #define ENCI_DACSEL_0 0x1c0b 993 #define ENCI_DACSEL_1 0x1c0c 994 #define ENCP_DACSEL_0 0x1c0d 995 #define ENCP_DACSEL_1 0x1c0e 996 #define ENCP_MAX_LINE_SWITCH_POINT 0x1c0f 997 #define ENCI_TST_EN 0x1c10 998 #define ENCI_TST_MDSEL 0x1c11 999 #define ENCI_TST_Y 0x1c12 1000 #define ENCI_TST_CB 0x1c13 1001 #define ENCI_TST_CR 0x1c14 1002 #define ENCI_TST_CLRBAR_STRT 0x1c15 1003 #define ENCI_TST_CLRBAR_WIDTH 0x1c16 1004 #define ENCI_TST_VDCNT_STSET 0x1c17 1005 #define ENCI_VFIFO2VD_CTL 0x1c18 1006 #define ENCI_VFIFO2VD_CTL_ENABLE BIT(0) 1007 #define ENCI_VFIFO2VD_CTL_VD_SEL(val) ((val & 0xff) << 8) 1008 #define ENCI_VFIFO2VD_PIXEL_START 0x1c19 1009 #define ENCI_VFIFO2VD_PIXEL_END 0x1c1a 1010 #define ENCI_VFIFO2VD_LINE_TOP_START 0x1c1b 1011 #define ENCI_VFIFO2VD_LINE_TOP_END 0x1c1c 1012 #define ENCI_VFIFO2VD_LINE_BOT_START 0x1c1d 1013 #define ENCI_VFIFO2VD_LINE_BOT_END 0x1c1e 1014 #define ENCI_VFIFO2VD_CTL2 0x1c1f 1015 #define ENCT_VFIFO2VD_CTL 0x1c20 1016 #define ENCT_VFIFO2VD_PIXEL_START 0x1c21 1017 #define ENCT_VFIFO2VD_PIXEL_END 0x1c22 1018 #define ENCT_VFIFO2VD_LINE_TOP_START 0x1c23 1019 #define ENCT_VFIFO2VD_LINE_TOP_END 0x1c24 1020 #define ENCT_VFIFO2VD_LINE_BOT_START 0x1c25 1021 #define ENCT_VFIFO2VD_LINE_BOT_END 0x1c26 1022 #define ENCT_VFIFO2VD_CTL2 0x1c27 1023 #define ENCT_TST_EN 0x1c28 1024 #define ENCT_TST_MDSEL 0x1c29 1025 #define ENCT_TST_Y 0x1c2a 1026 #define ENCT_TST_CB 0x1c2b 1027 #define ENCT_TST_CR 0x1c2c 1028 #define ENCT_TST_CLRBAR_STRT 0x1c2d 1029 #define ENCT_TST_CLRBAR_WIDTH 0x1c2e 1030 #define ENCT_TST_VDCNT_STSET 0x1c2f 1031 #define ENCP_DVI_HSO_BEGIN 0x1c30 1032 #define ENCP_DVI_HSO_END 0x1c31 1033 #define ENCP_DVI_VSO_BLINE_EVN 0x1c32 1034 #define ENCP_DVI_VSO_BLINE_ODD 0x1c33 1035 #define ENCP_DVI_VSO_ELINE_EVN 0x1c34 1036 #define ENCP_DVI_VSO_ELINE_ODD 0x1c35 1037 #define ENCP_DVI_VSO_BEGIN_EVN 0x1c36 1038 #define ENCP_DVI_VSO_BEGIN_ODD 0x1c37 1039 #define ENCP_DVI_VSO_END_EVN 0x1c38 1040 #define ENCP_DVI_VSO_END_ODD 0x1c39 1041 #define ENCP_DE_H_BEGIN 0x1c3a 1042 #define ENCP_DE_H_END 0x1c3b 1043 #define ENCP_DE_V_BEGIN_EVEN 0x1c3c 1044 #define ENCP_DE_V_END_EVEN 0x1c3d 1045 #define ENCP_DE_V_BEGIN_ODD 0x1c3e 1046 #define ENCP_DE_V_END_ODD 0x1c3f 1047 #define ENCI_SYNC_LINE_LENGTH 0x1c40 1048 #define ENCI_SYNC_PIXEL_EN 0x1c41 1049 #define ENCI_SYNC_TO_LINE_EN 0x1c42 1050 #define ENCI_SYNC_TO_PIXEL 0x1c43 1051 #define ENCP_SYNC_LINE_LENGTH 0x1c44 1052 #define ENCP_SYNC_PIXEL_EN 0x1c45 1053 #define ENCP_SYNC_TO_LINE_EN 0x1c46 1054 #define ENCP_SYNC_TO_PIXEL 0x1c47 1055 #define ENCT_SYNC_LINE_LENGTH 0x1c48 1056 #define ENCT_SYNC_PIXEL_EN 0x1c49 1057 #define ENCT_SYNC_TO_LINE_EN 0x1c4a 1058 #define ENCT_SYNC_TO_PIXEL 0x1c4b 1059 #define ENCL_SYNC_LINE_LENGTH 0x1c4c 1060 #define ENCL_SYNC_PIXEL_EN 0x1c4d 1061 #define ENCL_SYNC_TO_LINE_EN 0x1c4e 1062 #define ENCL_SYNC_TO_PIXEL 0x1c4f 1063 #define ENCP_VFIFO2VD_CTL2 0x1c50 1064 #define VENC_DVI_SETTING_MORE 0x1c51 1065 #define VENC_VDAC_DAC4_FILT_CTRL0 0x1c54 1066 #define VENC_VDAC_DAC4_FILT_CTRL1 0x1c55 1067 #define VENC_VDAC_DAC5_FILT_CTRL0 0x1c56 1068 #define VENC_VDAC_DAC5_FILT_CTRL1 0x1c57 1069 #define VENC_VDAC_DAC0_FILT_CTRL0 0x1c58 1070 #define VENC_VDAC_DAC0_FILT_CTRL0_EN BIT(0) 1071 #define VENC_VDAC_DAC0_FILT_CTRL1 0x1c59 1072 #define VENC_VDAC_DAC1_FILT_CTRL0 0x1c5a 1073 #define VENC_VDAC_DAC1_FILT_CTRL1 0x1c5b 1074 #define VENC_VDAC_DAC2_FILT_CTRL0 0x1c5c 1075 #define VENC_VDAC_DAC2_FILT_CTRL1 0x1c5d 1076 #define VENC_VDAC_DAC3_FILT_CTRL0 0x1c5e 1077 #define VENC_VDAC_DAC3_FILT_CTRL1 0x1c5f 1078 #define ENCT_VIDEO_EN 0x1c60 1079 #define ENCT_VIDEO_Y_SCL 0x1c61 1080 #define ENCT_VIDEO_PB_SCL 0x1c62 1081 #define ENCT_VIDEO_PR_SCL 0x1c63 1082 #define ENCT_VIDEO_Y_OFFST 0x1c64 1083 #define ENCT_VIDEO_PB_OFFST 0x1c65 1084 #define ENCT_VIDEO_PR_OFFST 0x1c66 1085 #define ENCT_VIDEO_MODE 0x1c67 1086 #define ENCT_VIDEO_MODE_ADV 0x1c68 1087 #define ENCT_DBG_PX_RST 0x1c69 1088 #define ENCT_DBG_LN_RST 0x1c6a 1089 #define ENCT_DBG_PX_INT 0x1c6b 1090 #define ENCT_DBG_LN_INT 0x1c6c 1091 #define ENCT_VIDEO_YFP1_HTIME 0x1c6d 1092 #define ENCT_VIDEO_YFP2_HTIME 0x1c6e 1093 #define ENCT_VIDEO_YC_DLY 0x1c6f 1094 #define ENCT_VIDEO_MAX_PXCNT 0x1c70 1095 #define ENCT_VIDEO_HAVON_END 0x1c71 1096 #define ENCT_VIDEO_HAVON_BEGIN 0x1c72 1097 #define ENCT_VIDEO_VAVON_ELINE 0x1c73 1098 #define ENCT_VIDEO_VAVON_BLINE 0x1c74 1099 #define ENCT_VIDEO_HSO_BEGIN 0x1c75 1100 #define ENCT_VIDEO_HSO_END 0x1c76 1101 #define ENCT_VIDEO_VSO_BEGIN 0x1c77 1102 #define ENCT_VIDEO_VSO_END 0x1c78 1103 #define ENCT_VIDEO_VSO_BLINE 0x1c79 1104 #define ENCT_VIDEO_VSO_ELINE 0x1c7a 1105 #define ENCT_VIDEO_MAX_LNCNT 0x1c7b 1106 #define ENCT_VIDEO_BLANKY_VAL 0x1c7c 1107 #define ENCT_VIDEO_BLANKPB_VAL 0x1c7d 1108 #define ENCT_VIDEO_BLANKPR_VAL 0x1c7e 1109 #define ENCT_VIDEO_HOFFST 0x1c7f 1110 #define ENCT_VIDEO_VOFFST 0x1c80 1111 #define ENCT_VIDEO_RGB_CTRL 0x1c81 1112 #define ENCT_VIDEO_FILT_CTRL 0x1c82 1113 #define ENCT_VIDEO_OFLD_VPEQ_OFST 0x1c83 1114 #define ENCT_VIDEO_OFLD_VOAV_OFST 0x1c84 1115 #define ENCT_VIDEO_MATRIX_CB 0x1c85 1116 #define ENCT_VIDEO_MATRIX_CR 0x1c86 1117 #define ENCT_VIDEO_RGBIN_CTRL 0x1c87 1118 #define ENCT_MAX_LINE_SWITCH_POINT 0x1c88 1119 #define ENCT_DACSEL_0 0x1c89 1120 #define ENCT_DACSEL_1 0x1c8a 1121 #define ENCL_VFIFO2VD_CTL 0x1c90 1122 #define ENCL_VFIFO2VD_PIXEL_START 0x1c91 1123 #define ENCL_VFIFO2VD_PIXEL_END 0x1c92 1124 #define ENCL_VFIFO2VD_LINE_TOP_START 0x1c93 1125 #define ENCL_VFIFO2VD_LINE_TOP_END 0x1c94 1126 #define ENCL_VFIFO2VD_LINE_BOT_START 0x1c95 1127 #define ENCL_VFIFO2VD_LINE_BOT_END 0x1c96 1128 #define ENCL_VFIFO2VD_CTL2 0x1c97 1129 #define ENCL_TST_EN 0x1c98 1130 #define ENCL_TST_MDSEL 0x1c99 1131 #define ENCL_TST_Y 0x1c9a 1132 #define ENCL_TST_CB 0x1c9b 1133 #define ENCL_TST_CR 0x1c9c 1134 #define ENCL_TST_CLRBAR_STRT 0x1c9d 1135 #define ENCL_TST_CLRBAR_WIDTH 0x1c9e 1136 #define ENCL_TST_VDCNT_STSET 0x1c9f 1137 #define ENCL_VIDEO_EN 0x1ca0 1138 #define ENCL_VIDEO_Y_SCL 0x1ca1 1139 #define ENCL_VIDEO_PB_SCL 0x1ca2 1140 #define ENCL_VIDEO_PR_SCL 0x1ca3 1141 #define ENCL_VIDEO_Y_OFFST 0x1ca4 1142 #define ENCL_VIDEO_PB_OFFST 0x1ca5 1143 #define ENCL_VIDEO_PR_OFFST 0x1ca6 1144 #define ENCL_VIDEO_MODE 0x1ca7 1145 #define ENCL_VIDEO_MODE_ADV 0x1ca8 1146 #define ENCL_DBG_PX_RST 0x1ca9 1147 #define ENCL_DBG_LN_RST 0x1caa 1148 #define ENCL_DBG_PX_INT 0x1cab 1149 #define ENCL_DBG_LN_INT 0x1cac 1150 #define ENCL_VIDEO_YFP1_HTIME 0x1cad 1151 #define ENCL_VIDEO_YFP2_HTIME 0x1cae 1152 #define ENCL_VIDEO_YC_DLY 0x1caf 1153 #define ENCL_VIDEO_MAX_PXCNT 0x1cb0 1154 #define ENCL_VIDEO_HAVON_END 0x1cb1 1155 #define ENCL_VIDEO_HAVON_BEGIN 0x1cb2 1156 #define ENCL_VIDEO_VAVON_ELINE 0x1cb3 1157 #define ENCL_VIDEO_VAVON_BLINE 0x1cb4 1158 #define ENCL_VIDEO_HSO_BEGIN 0x1cb5 1159 #define ENCL_VIDEO_HSO_END 0x1cb6 1160 #define ENCL_VIDEO_VSO_BEGIN 0x1cb7 1161 #define ENCL_VIDEO_VSO_END 0x1cb8 1162 #define ENCL_VIDEO_VSO_BLINE 0x1cb9 1163 #define ENCL_VIDEO_VSO_ELINE 0x1cba 1164 #define ENCL_VIDEO_MAX_LNCNT 0x1cbb 1165 #define ENCL_VIDEO_BLANKY_VAL 0x1cbc 1166 #define ENCL_VIDEO_BLANKPB_VAL 0x1cbd 1167 #define ENCL_VIDEO_BLANKPR_VAL 0x1cbe 1168 #define ENCL_VIDEO_HOFFST 0x1cbf 1169 #define ENCL_VIDEO_VOFFST 0x1cc0 1170 #define ENCL_VIDEO_RGB_CTRL 0x1cc1 1171 #define ENCL_VIDEO_FILT_CTRL 0x1cc2 1172 #define ENCL_VIDEO_OFLD_VPEQ_OFST 0x1cc3 1173 #define ENCL_VIDEO_OFLD_VOAV_OFST 0x1cc4 1174 #define ENCL_VIDEO_MATRIX_CB 0x1cc5 1175 #define ENCL_VIDEO_MATRIX_CR 0x1cc6 1176 #define ENCL_VIDEO_RGBIN_CTRL 0x1cc7 1177 #define ENCL_MAX_LINE_SWITCH_POINT 0x1cc8 1178 #define ENCL_DACSEL_0 0x1cc9 1179 #define ENCL_DACSEL_1 0x1cca 1180 #define RDMA_AHB_START_ADDR_MAN 0x1100 1181 #define RDMA_AHB_END_ADDR_MAN 0x1101 1182 #define RDMA_AHB_START_ADDR_1 0x1102 1183 #define RDMA_AHB_END_ADDR_1 0x1103 1184 #define RDMA_AHB_START_ADDR_2 0x1104 1185 #define RDMA_AHB_END_ADDR_2 0x1105 1186 #define RDMA_AHB_START_ADDR_3 0x1106 1187 #define RDMA_AHB_END_ADDR_3 0x1107 1188 #define RDMA_AHB_START_ADDR_4 0x1108 1189 #define RDMA_AHB_END_ADDR_4 0x1109 1190 #define RDMA_AHB_START_ADDR_5 0x110a 1191 #define RDMA_AHB_END_ADDR_5 0x110b 1192 #define RDMA_AHB_START_ADDR_6 0x110c 1193 #define RDMA_AHB_END_ADDR_6 0x110d 1194 #define RDMA_AHB_START_ADDR_7 0x110e 1195 #define RDMA_AHB_END_ADDR_7 0x110f 1196 #define RDMA_ACCESS_AUTO 0x1110 1197 #define RDMA_ACCESS_AUTO2 0x1111 1198 #define RDMA_ACCESS_AUTO3 0x1112 1199 #define RDMA_ACCESS_MAN 0x1113 1200 #define RDMA_CTRL 0x1114 1201 #define RDMA_STATUS 0x1115 1202 #define RDMA_STATUS2 0x1116 1203 #define RDMA_STATUS3 0x1117 1204 #define L_GAMMA_CNTL_PORT 0x1400 1205 #define L_GAMMA_DATA_PORT 0x1401 1206 #define L_GAMMA_ADDR_PORT 0x1402 1207 #define L_GAMMA_VCOM_HSWITCH_ADDR 0x1403 1208 #define L_RGB_BASE_ADDR 0x1405 1209 #define L_RGB_COEFF_ADDR 0x1406 1210 #define L_POL_CNTL_ADDR 0x1407 1211 #define L_DITH_CNTL_ADDR 0x1408 1212 #define L_GAMMA_PROBE_CTRL 0x1409 1213 #define L_GAMMA_PROBE_COLOR_L 0x140a 1214 #define L_GAMMA_PROBE_COLOR_H 0x140b 1215 #define L_GAMMA_PROBE_HL_COLOR 0x140c 1216 #define L_GAMMA_PROBE_POS_X 0x140d 1217 #define L_GAMMA_PROBE_POS_Y 0x140e 1218 #define L_STH1_HS_ADDR 0x1410 1219 #define L_STH1_HE_ADDR 0x1411 1220 #define L_STH1_VS_ADDR 0x1412 1221 #define L_STH1_VE_ADDR 0x1413 1222 #define L_STH2_HS_ADDR 0x1414 1223 #define L_STH2_HE_ADDR 0x1415 1224 #define L_STH2_VS_ADDR 0x1416 1225 #define L_STH2_VE_ADDR 0x1417 1226 #define L_OEH_HS_ADDR 0x1418 1227 #define L_OEH_HE_ADDR 0x1419 1228 #define L_OEH_VS_ADDR 0x141a 1229 #define L_OEH_VE_ADDR 0x141b 1230 #define L_VCOM_HSWITCH_ADDR 0x141c 1231 #define L_VCOM_VS_ADDR 0x141d 1232 #define L_VCOM_VE_ADDR 0x141e 1233 #define L_CPV1_HS_ADDR 0x141f 1234 #define L_CPV1_HE_ADDR 0x1420 1235 #define L_CPV1_VS_ADDR 0x1421 1236 #define L_CPV1_VE_ADDR 0x1422 1237 #define L_CPV2_HS_ADDR 0x1423 1238 #define L_CPV2_HE_ADDR 0x1424 1239 #define L_CPV2_VS_ADDR 0x1425 1240 #define L_CPV2_VE_ADDR 0x1426 1241 #define L_STV1_HS_ADDR 0x1427 1242 #define L_STV1_HE_ADDR 0x1428 1243 #define L_STV1_VS_ADDR 0x1429 1244 #define L_STV1_VE_ADDR 0x142a 1245 #define L_STV2_HS_ADDR 0x142b 1246 #define L_STV2_HE_ADDR 0x142c 1247 #define L_STV2_VS_ADDR 0x142d 1248 #define L_STV2_VE_ADDR 0x142e 1249 #define L_OEV1_HS_ADDR 0x142f 1250 #define L_OEV1_HE_ADDR 0x1430 1251 #define L_OEV1_VS_ADDR 0x1431 1252 #define L_OEV1_VE_ADDR 0x1432 1253 #define L_OEV2_HS_ADDR 0x1433 1254 #define L_OEV2_HE_ADDR 0x1434 1255 #define L_OEV2_VS_ADDR 0x1435 1256 #define L_OEV2_VE_ADDR 0x1436 1257 #define L_OEV3_HS_ADDR 0x1437 1258 #define L_OEV3_HE_ADDR 0x1438 1259 #define L_OEV3_VS_ADDR 0x1439 1260 #define L_OEV3_VE_ADDR 0x143a 1261 #define L_LCD_PWR_ADDR 0x143b 1262 #define L_LCD_PWM0_LO_ADDR 0x143c 1263 #define L_LCD_PWM0_HI_ADDR 0x143d 1264 #define L_LCD_PWM1_LO_ADDR 0x143e 1265 #define L_LCD_PWM1_HI_ADDR 0x143f 1266 #define L_INV_CNT_ADDR 0x1440 1267 #define L_TCON_MISC_SEL_ADDR 0x1441 1268 #define L_DUAL_PORT_CNTL_ADDR 0x1442 1269 #define MLVDS_CLK_CTL1_HI 0x1443 1270 #define MLVDS_CLK_CTL1_LO 0x1444 1271 #define L_TCON_DOUBLE_CTL 0x1449 1272 #define L_TCON_PATTERN_HI 0x144a 1273 #define L_TCON_PATTERN_LO 0x144b 1274 #define LDIM_BL_ADDR_PORT 0x144e 1275 #define LDIM_BL_DATA_PORT 0x144f 1276 #define L_DE_HS_ADDR 0x1451 1277 #define L_DE_HE_ADDR 0x1452 1278 #define L_DE_VS_ADDR 0x1453 1279 #define L_DE_VE_ADDR 0x1454 1280 #define L_HSYNC_HS_ADDR 0x1455 1281 #define L_HSYNC_HE_ADDR 0x1456 1282 #define L_HSYNC_VS_ADDR 0x1457 1283 #define L_HSYNC_VE_ADDR 0x1458 1284 #define L_VSYNC_HS_ADDR 0x1459 1285 #define L_VSYNC_HE_ADDR 0x145a 1286 #define L_VSYNC_VS_ADDR 0x145b 1287 #define L_VSYNC_VE_ADDR 0x145c 1288 #define L_LCD_MCU_CTL 0x145d 1289 #define DUAL_MLVDS_CTL 0x1460 1290 #define DUAL_MLVDS_LINE_START 0x1461 1291 #define DUAL_MLVDS_LINE_END 0x1462 1292 #define DUAL_MLVDS_PIXEL_W_START_L 0x1463 1293 #define DUAL_MLVDS_PIXEL_W_END_L 0x1464 1294 #define DUAL_MLVDS_PIXEL_W_START_R 0x1465 1295 #define DUAL_MLVDS_PIXEL_W_END_R 0x1466 1296 #define DUAL_MLVDS_PIXEL_R_START_L 0x1467 1297 #define DUAL_MLVDS_PIXEL_R_CNT_L 0x1468 1298 #define DUAL_MLVDS_PIXEL_R_START_R 0x1469 1299 #define DUAL_MLVDS_PIXEL_R_CNT_R 0x146a 1300 #define V_INVERSION_PIXEL 0x1470 1301 #define V_INVERSION_LINE 0x1471 1302 #define V_INVERSION_CONTROL 0x1472 1303 #define MLVDS2_CONTROL 0x1474 1304 #define MLVDS2_CONFIG_HI 0x1475 1305 #define MLVDS2_CONFIG_LO 0x1476 1306 #define MLVDS2_DUAL_GATE_WR_START 0x1477 1307 #define MLVDS2_DUAL_GATE_WR_END 0x1478 1308 #define MLVDS2_DUAL_GATE_RD_START 0x1479 1309 #define MLVDS2_DUAL_GATE_RD_END 0x147a 1310 #define MLVDS2_SECOND_RESET_CTL 0x147b 1311 #define MLVDS2_DUAL_GATE_CTL_HI 0x147c 1312 #define MLVDS2_DUAL_GATE_CTL_LO 0x147d 1313 #define MLVDS2_RESET_CONFIG_HI 0x147e 1314 #define MLVDS2_RESET_CONFIG_LO 0x147f 1315 #define GAMMA_CNTL_PORT 0x1480 1316 #define GAMMA_DATA_PORT 0x1481 1317 #define GAMMA_ADDR_PORT 0x1482 1318 #define GAMMA_VCOM_HSWITCH_ADDR 0x1483 1319 #define RGB_BASE_ADDR 0x1485 1320 #define RGB_COEFF_ADDR 0x1486 1321 #define POL_CNTL_ADDR 0x1487 1322 #define DITH_CNTL_ADDR 0x1488 1323 #define GAMMA_PROBE_CTRL 0x1489 1324 #define GAMMA_PROBE_COLOR_L 0x148a 1325 #define GAMMA_PROBE_COLOR_H 0x148b 1326 #define GAMMA_PROBE_HL_COLOR 0x148c 1327 #define GAMMA_PROBE_POS_X 0x148d 1328 #define GAMMA_PROBE_POS_Y 0x148e 1329 #define STH1_HS_ADDR 0x1490 1330 #define STH1_HE_ADDR 0x1491 1331 #define STH1_VS_ADDR 0x1492 1332 #define STH1_VE_ADDR 0x1493 1333 #define STH2_HS_ADDR 0x1494 1334 #define STH2_HE_ADDR 0x1495 1335 #define STH2_VS_ADDR 0x1496 1336 #define STH2_VE_ADDR 0x1497 1337 #define OEH_HS_ADDR 0x1498 1338 #define OEH_HE_ADDR 0x1499 1339 #define OEH_VS_ADDR 0x149a 1340 #define OEH_VE_ADDR 0x149b 1341 #define VCOM_HSWITCH_ADDR 0x149c 1342 #define VCOM_VS_ADDR 0x149d 1343 #define VCOM_VE_ADDR 0x149e 1344 #define CPV1_HS_ADDR 0x149f 1345 #define CPV1_HE_ADDR 0x14a0 1346 #define CPV1_VS_ADDR 0x14a1 1347 #define CPV1_VE_ADDR 0x14a2 1348 #define CPV2_HS_ADDR 0x14a3 1349 #define CPV2_HE_ADDR 0x14a4 1350 #define CPV2_VS_ADDR 0x14a5 1351 #define CPV2_VE_ADDR 0x14a6 1352 #define STV1_HS_ADDR 0x14a7 1353 #define STV1_HE_ADDR 0x14a8 1354 #define STV1_VS_ADDR 0x14a9 1355 #define STV1_VE_ADDR 0x14aa 1356 #define STV2_HS_ADDR 0x14ab 1357 #define STV2_HE_ADDR 0x14ac 1358 #define STV2_VS_ADDR 0x14ad 1359 #define STV2_VE_ADDR 0x14ae 1360 #define OEV1_HS_ADDR 0x14af 1361 #define OEV1_HE_ADDR 0x14b0 1362 #define OEV1_VS_ADDR 0x14b1 1363 #define OEV1_VE_ADDR 0x14b2 1364 #define OEV2_HS_ADDR 0x14b3 1365 #define OEV2_HE_ADDR 0x14b4 1366 #define OEV2_VS_ADDR 0x14b5 1367 #define OEV2_VE_ADDR 0x14b6 1368 #define OEV3_HS_ADDR 0x14b7 1369 #define OEV3_HE_ADDR 0x14b8 1370 #define OEV3_VS_ADDR 0x14b9 1371 #define OEV3_VE_ADDR 0x14ba 1372 #define LCD_PWR_ADDR 0x14bb 1373 #define LCD_PWM0_LO_ADDR 0x14bc 1374 #define LCD_PWM0_HI_ADDR 0x14bd 1375 #define LCD_PWM1_LO_ADDR 0x14be 1376 #define LCD_PWM1_HI_ADDR 0x14bf 1377 #define INV_CNT_ADDR 0x14c0 1378 #define TCON_MISC_SEL_ADDR 0x14c1 1379 #define DUAL_PORT_CNTL_ADDR 0x14c2 1380 #define MLVDS_CONTROL 0x14c3 1381 #define MLVDS_RESET_PATTERN_HI 0x14c4 1382 #define MLVDS_RESET_PATTERN_LO 0x14c5 1383 #define MLVDS_RESET_PATTERN_EXT 0x14c6 1384 #define MLVDS_CONFIG_HI 0x14c7 1385 #define MLVDS_CONFIG_LO 0x14c8 1386 #define TCON_DOUBLE_CTL 0x14c9 1387 #define TCON_PATTERN_HI 0x14ca 1388 #define TCON_PATTERN_LO 0x14cb 1389 #define TCON_CONTROL_HI 0x14cc 1390 #define TCON_CONTROL_LO 0x14cd 1391 #define LVDS_BLANK_DATA_HI 0x14ce 1392 #define LVDS_BLANK_DATA_LO 0x14cf 1393 #define LVDS_PACK_CNTL_ADDR 0x14d0 1394 #define DE_HS_ADDR 0x14d1 1395 #define DE_HE_ADDR 0x14d2 1396 #define DE_VS_ADDR 0x14d3 1397 #define DE_VE_ADDR 0x14d4 1398 #define HSYNC_HS_ADDR 0x14d5 1399 #define HSYNC_HE_ADDR 0x14d6 1400 #define HSYNC_VS_ADDR 0x14d7 1401 #define HSYNC_VE_ADDR 0x14d8 1402 #define VSYNC_HS_ADDR 0x14d9 1403 #define VSYNC_HE_ADDR 0x14da 1404 #define VSYNC_VS_ADDR 0x14db 1405 #define VSYNC_VE_ADDR 0x14dc 1406 #define LCD_MCU_CTL 0x14dd 1407 #define LCD_MCU_DATA_0 0x14de 1408 #define LCD_MCU_DATA_1 0x14df 1409 #define LVDS_GEN_CNTL 0x14e0 1410 #define LVDS_PHY_CNTL0 0x14e1 1411 #define LVDS_PHY_CNTL1 0x14e2 1412 #define LVDS_PHY_CNTL2 0x14e3 1413 #define LVDS_PHY_CNTL3 0x14e4 1414 #define LVDS_PHY_CNTL4 0x14e5 1415 #define LVDS_PHY_CNTL5 0x14e6 1416 #define LVDS_SRG_TEST 0x14e8 1417 #define LVDS_BIST_MUX0 0x14e9 1418 #define LVDS_BIST_MUX1 0x14ea 1419 #define LVDS_BIST_FIXED0 0x14eb 1420 #define LVDS_BIST_FIXED1 0x14ec 1421 #define LVDS_BIST_CNTL0 0x14ed 1422 #define LVDS_CLKB_CLKA 0x14ee 1423 #define LVDS_PHY_CLK_CNTL 0x14ef 1424 #define LVDS_SER_EN 0x14f0 1425 #define LVDS_PHY_CNTL6 0x14f1 1426 #define LVDS_PHY_CNTL7 0x14f2 1427 #define LVDS_PHY_CNTL8 0x14f3 1428 #define MLVDS_CLK_CTL0_HI 0x14f4 1429 #define MLVDS_CLK_CTL0_LO 0x14f5 1430 #define MLVDS_DUAL_GATE_WR_START 0x14f6 1431 #define MLVDS_DUAL_GATE_WR_END 0x14f7 1432 #define MLVDS_DUAL_GATE_RD_START 0x14f8 1433 #define MLVDS_DUAL_GATE_RD_END 0x14f9 1434 #define MLVDS_SECOND_RESET_CTL 0x14fa 1435 #define MLVDS_DUAL_GATE_CTL_HI 0x14fb 1436 #define MLVDS_DUAL_GATE_CTL_LO 0x14fc 1437 #define MLVDS_RESET_CONFIG_HI 0x14fd 1438 #define MLVDS_RESET_CONFIG_LO 0x14fe 1439 #define VPU_OSD1_MMC_CTRL 0x2701 1440 #define VPU_OSD2_MMC_CTRL 0x2702 1441 #define VPU_VD1_MMC_CTRL 0x2703 1442 #define VPU_VD2_MMC_CTRL 0x2704 1443 #define VPU_DI_IF1_MMC_CTRL 0x2705 1444 #define VPU_DI_MEM_MMC_CTRL 0x2706 1445 #define VPU_DI_INP_MMC_CTRL 0x2707 1446 #define VPU_DI_MTNRD_MMC_CTRL 0x2708 1447 #define VPU_DI_CHAN2_MMC_CTRL 0x2709 1448 #define VPU_DI_MTNWR_MMC_CTRL 0x270a 1449 #define VPU_DI_NRWR_MMC_CTRL 0x270b 1450 #define VPU_DI_DIWR_MMC_CTRL 0x270c 1451 #define VPU_VDIN0_MMC_CTRL 0x270d 1452 #define VPU_VDIN1_MMC_CTRL 0x270e 1453 #define VPU_BT656_MMC_CTRL 0x270f 1454 #define VPU_TVD3D_MMC_CTRL 0x2710 1455 #define VPU_TVDVBI_MMC_CTRL 0x2711 1456 #define VPU_TVDVBI_VSLATCH_ADDR 0x2712 1457 #define VPU_TVDVBI_WRRSP_ADDR 0x2713 1458 #define VPU_VDIN_PRE_ARB_CTRL 0x2714 1459 #define VPU_VDISP_PRE_ARB_CTRL 0x2715 1460 #define VPU_VPUARB2_PRE_ARB_CTRL 0x2716 1461 #define VPU_OSD3_MMC_CTRL 0x2717 1462 #define VPU_OSD4_MMC_CTRL 0x2718 1463 #define VPU_VD3_MMC_CTRL 0x2719 1464 #define VPU_VIU_VENC_MUX_CTRL 0x271a 1465 #define VIU1_SEL_VENC_MASK 0x3 1466 #define VIU1_SEL_VENC_ENCL 0 1467 #define VIU1_SEL_VENC_ENCI 1 1468 #define VIU1_SEL_VENC_ENCP 2 1469 #define VIU1_SEL_VENC_ENCT 3 1470 #define VIU2_SEL_VENC_MASK 0xc 1471 #define VIU2_SEL_VENC_ENCL 0 1472 #define VIU2_SEL_VENC_ENCI (1 << 2) 1473 #define VIU2_SEL_VENC_ENCP (2 << 2) 1474 #define VIU2_SEL_VENC_ENCT (3 << 2) 1475 #define VPU_HDMI_SETTING 0x271b 1476 #define VPU_HDMI_ENCI_DATA_TO_HDMI BIT(0) 1477 #define VPU_HDMI_ENCP_DATA_TO_HDMI BIT(1) 1478 #define VPU_HDMI_INV_HSYNC BIT(2) 1479 #define VPU_HDMI_INV_VSYNC BIT(3) 1480 #define VPU_HDMI_OUTPUT_CRYCB (0 << 5) 1481 #define VPU_HDMI_OUTPUT_YCBCR (1 << 5) 1482 #define VPU_HDMI_OUTPUT_YCRCB (2 << 5) 1483 #define VPU_HDMI_OUTPUT_CBCRY (3 << 5) 1484 #define VPU_HDMI_OUTPUT_CBYCR (4 << 5) 1485 #define VPU_HDMI_OUTPUT_CRCBY (5 << 5) 1486 #define VPU_HDMI_WR_RATE(rate) (((rate & 0x1f) - 1) << 8) 1487 #define VPU_HDMI_RD_RATE(rate) (((rate & 0x1f) - 1) << 12) 1488 #define ENCI_INFO_READ 0x271c 1489 #define ENCP_INFO_READ 0x271d 1490 #define ENCT_INFO_READ 0x271e 1491 #define ENCL_INFO_READ 0x271f 1492 #define VPU_SW_RESET 0x2720 1493 #define VPU_D2D3_MMC_CTRL 0x2721 1494 #define VPU_CONT_MMC_CTRL 0x2722 1495 #define VPU_CLK_GATE 0x2723 1496 #define VPU_RDMA_MMC_CTRL 0x2724 1497 #define VPU_MEM_PD_REG0 0x2725 1498 #define VPU_MEM_PD_REG1 0x2726 1499 #define VPU_HDMI_DATA_OVR 0x2727 1500 #define VPU_PROT1_MMC_CTRL 0x2728 1501 #define VPU_PROT2_MMC_CTRL 0x2729 1502 #define VPU_PROT3_MMC_CTRL 0x272a 1503 #define VPU_ARB4_V1_MMC_CTRL 0x272b 1504 #define VPU_ARB4_V2_MMC_CTRL 0x272c 1505 #define VPU_VPU_PWM_V0 0x2730 1506 #define VPU_VPU_PWM_V1 0x2731 1507 #define VPU_VPU_PWM_V2 0x2732 1508 #define VPU_VPU_PWM_V3 0x2733 1509 #define VPU_VPU_PWM_H0 0x2734 1510 #define VPU_VPU_PWM_H1 0x2735 1511 #define VPU_VPU_PWM_H2 0x2736 1512 #define VPU_VPU_PWM_H3 0x2737 1513 #define VPU_MISC_CTRL 0x2740 1514 #define VPU_ISP_GCLK_CTRL0 0x2741 1515 #define VPU_ISP_GCLK_CTRL1 0x2742 1516 #define VPU_HDMI_FMT_CTRL 0x2743 1517 #define VPU_VDIN_ASYNC_HOLD_CTRL 0x2743 1518 #define VPU_VDISP_ASYNC_HOLD_CTRL 0x2744 1519 #define VPU_VPUARB2_ASYNC_HOLD_CTRL 0x2745 1520 1521 #define VPU_PROT1_CLK_GATE 0x2750 1522 #define VPU_PROT1_GEN_CNTL 0x2751 1523 #define VPU_PROT1_X_START_END 0x2752 1524 #define VPU_PROT1_Y_START_END 0x2753 1525 #define VPU_PROT1_Y_LEN_STEP 0x2754 1526 #define VPU_PROT1_RPT_LOOP 0x2755 1527 #define VPU_PROT1_RPT_PAT 0x2756 1528 #define VPU_PROT1_DDR 0x2757 1529 #define VPU_PROT1_RBUF_ROOM 0x2758 1530 #define VPU_PROT1_STAT_0 0x2759 1531 #define VPU_PROT1_STAT_1 0x275a 1532 #define VPU_PROT1_STAT_2 0x275b 1533 #define VPU_PROT1_REQ_ONOFF 0x275c 1534 #define VPU_PROT2_CLK_GATE 0x2760 1535 #define VPU_PROT2_GEN_CNTL 0x2761 1536 #define VPU_PROT2_X_START_END 0x2762 1537 #define VPU_PROT2_Y_START_END 0x2763 1538 #define VPU_PROT2_Y_LEN_STEP 0x2764 1539 #define VPU_PROT2_RPT_LOOP 0x2765 1540 #define VPU_PROT2_RPT_PAT 0x2766 1541 #define VPU_PROT2_DDR 0x2767 1542 #define VPU_PROT2_RBUF_ROOM 0x2768 1543 #define VPU_PROT2_STAT_0 0x2769 1544 #define VPU_PROT2_STAT_1 0x276a 1545 #define VPU_PROT2_STAT_2 0x276b 1546 #define VPU_PROT2_REQ_ONOFF 0x276c 1547 #define VPU_PROT3_CLK_GATE 0x2770 1548 #define VPU_PROT3_GEN_CNTL 0x2771 1549 #define VPU_PROT3_X_START_END 0x2772 1550 #define VPU_PROT3_Y_START_END 0x2773 1551 #define VPU_PROT3_Y_LEN_STEP 0x2774 1552 #define VPU_PROT3_RPT_LOOP 0x2775 1553 #define VPU_PROT3_RPT_PAT 0x2776 1554 #define VPU_PROT3_DDR 0x2777 1555 #define VPU_PROT3_RBUF_ROOM 0x2778 1556 #define VPU_PROT3_STAT_0 0x2779 1557 #define VPU_PROT3_STAT_1 0x277a 1558 #define VPU_PROT3_STAT_2 0x277b 1559 #define VPU_PROT3_REQ_ONOFF 0x277c 1560 #define VPU_RDARB_MODE_L1C1 0x2790 1561 #define VPU_RDARB_MODE_L1C2 0x2799 1562 #define VPU_RDARB_MODE_L2C1 0x279d 1563 #define VPU_WRARB_MODE_L2C1 0x27a2 1564 #define VPU_RDARB_SLAVE_TO_MASTER_PORT(dc, port) (port << (16 + dc)) 1565 1566 /* osd super scale */ 1567 #define OSDSR_HV_SIZEIN 0x3130 1568 #define OSDSR_CTRL_MODE 0x3131 1569 #define OSDSR_ABIC_HCOEF 0x3132 1570 #define OSDSR_YBIC_HCOEF 0x3133 1571 #define OSDSR_CBIC_HCOEF 0x3134 1572 #define OSDSR_ABIC_VCOEF 0x3135 1573 #define OSDSR_YBIC_VCOEF 0x3136 1574 #define OSDSR_CBIC_VCOEF 0x3137 1575 #define OSDSR_VAR_PARA 0x3138 1576 #define OSDSR_CONST_PARA 0x3139 1577 #define OSDSR_RKE_EXTWIN 0x313a 1578 #define OSDSR_UK_GRAD2DDIAG_TH_RATE 0x313b 1579 #define OSDSR_UK_GRAD2DDIAG_LIMIT 0x313c 1580 #define OSDSR_UK_GRAD2DADJA_TH_RATE 0x313d 1581 #define OSDSR_UK_GRAD2DADJA_LIMIT 0x313e 1582 #define OSDSR_UK_BST_GAIN 0x313f 1583 #define OSDSR_HVBLEND_TH 0x3140 1584 #define OSDSR_DEMO_WIND_TB 0x3141 1585 #define OSDSR_DEMO_WIND_LR 0x3142 1586 #define OSDSR_INT_BLANK_NUM 0x3143 1587 #define OSDSR_FRM_END_STAT 0x3144 1588 #define OSDSR_ABIC_HCOEF0 0x3145 1589 #define OSDSR_YBIC_HCOEF0 0x3146 1590 #define OSDSR_CBIC_HCOEF0 0x3147 1591 #define OSDSR_ABIC_VCOEF0 0x3148 1592 #define OSDSR_YBIC_VCOEF0 0x3149 1593 #define OSDSR_CBIC_VCOEF0 0x314a 1594 1595 /* osd afbcd on gxtvbb */ 1596 #define OSD1_AFBCD_ENABLE 0x31a0 1597 #define OSD1_AFBCD_MODE 0x31a1 1598 #define OSD1_AFBCD_SIZE_IN 0x31a2 1599 #define OSD1_AFBCD_HDR_PTR 0x31a3 1600 #define OSD1_AFBCD_FRAME_PTR 0x31a4 1601 #define OSD1_AFBCD_CHROMA_PTR 0x31a5 1602 #define OSD1_AFBCD_CONV_CTRL 0x31a6 1603 #define OSD1_AFBCD_STATUS 0x31a8 1604 #define OSD1_AFBCD_PIXEL_HSCOPE 0x31a9 1605 #define OSD1_AFBCD_PIXEL_VSCOPE 0x31aa 1606 1607 /* add for gxm and 962e dv core2 */ 1608 #define DOLBY_CORE2A_SWAP_CTRL1 0x3434 1609 #define DOLBY_CORE2A_SWAP_CTRL2 0x3435 1610 1611 /* osd afbc on g12a */ 1612 #define VPU_MAFBC_BLOCK_ID 0x3a00 1613 #define VPU_MAFBC_IRQ_RAW_STATUS 0x3a01 1614 #define VPU_MAFBC_IRQ_CLEAR 0x3a02 1615 #define VPU_MAFBC_IRQ_MASK 0x3a03 1616 #define VPU_MAFBC_IRQ_STATUS 0x3a04 1617 #define VPU_MAFBC_COMMAND 0x3a05 1618 #define VPU_MAFBC_STATUS 0x3a06 1619 #define VPU_MAFBC_SURFACE_CFG 0x3a07 1620 #define VPU_MAFBC_HEADER_BUF_ADDR_LOW_S0 0x3a10 1621 #define VPU_MAFBC_HEADER_BUF_ADDR_HIGH_S0 0x3a11 1622 #define VPU_MAFBC_FORMAT_SPECIFIER_S0 0x3a12 1623 #define VPU_MAFBC_BUFFER_WIDTH_S0 0x3a13 1624 #define VPU_MAFBC_BUFFER_HEIGHT_S0 0x3a14 1625 #define VPU_MAFBC_BOUNDING_BOX_X_START_S0 0x3a15 1626 #define VPU_MAFBC_BOUNDING_BOX_X_END_S0 0x3a16 1627 #define VPU_MAFBC_BOUNDING_BOX_Y_START_S0 0x3a17 1628 #define VPU_MAFBC_BOUNDING_BOX_Y_END_S0 0x3a18 1629 #define VPU_MAFBC_OUTPUT_BUF_ADDR_LOW_S0 0x3a19 1630 #define VPU_MAFBC_OUTPUT_BUF_ADDR_HIGH_S0 0x3a1a 1631 #define VPU_MAFBC_OUTPUT_BUF_STRIDE_S0 0x3a1b 1632 #define VPU_MAFBC_PREFETCH_CFG_S0 0x3a1c 1633 1634 #define VPU_MAFBC_HEADER_BUF_ADDR_LOW_S1 0x3a30 1635 #define VPU_MAFBC_HEADER_BUF_ADDR_HIGH_S1 0x3a31 1636 #define VPU_MAFBC_FORMAT_SPECIFIER_S1 0x3a32 1637 #define VPU_MAFBC_BUFFER_WIDTH_S1 0x3a33 1638 #define VPU_MAFBC_BUFFER_HEIGHT_S1 0x3a34 1639 #define VPU_MAFBC_BOUNDING_BOX_X_START_S1 0x3a35 1640 #define VPU_MAFBC_BOUNDING_BOX_X_END_S1 0x3a36 1641 #define VPU_MAFBC_BOUNDING_BOX_Y_START_S1 0x3a37 1642 #define VPU_MAFBC_BOUNDING_BOX_Y_END_S1 0x3a38 1643 #define VPU_MAFBC_OUTPUT_BUF_ADDR_LOW_S1 0x3a39 1644 #define VPU_MAFBC_OUTPUT_BUF_ADDR_HIGH_S1 0x3a3a 1645 #define VPU_MAFBC_OUTPUT_BUF_STRIDE_S1 0x3a3b 1646 #define VPU_MAFBC_PREFETCH_CFG_S1 0x3a3c 1647 1648 #define VPU_MAFBC_HEADER_BUF_ADDR_LOW_S2 0x3a50 1649 #define VPU_MAFBC_HEADER_BUF_ADDR_HIGH_S2 0x3a51 1650 #define VPU_MAFBC_FORMAT_SPECIFIER_S2 0x3a52 1651 #define VPU_MAFBC_BUFFER_WIDTH_S2 0x3a53 1652 #define VPU_MAFBC_BUFFER_HEIGHT_S2 0x3a54 1653 #define VPU_MAFBC_BOUNDING_BOX_X_START_S2 0x3a55 1654 #define VPU_MAFBC_BOUNDING_BOX_X_END_S2 0x3a56 1655 #define VPU_MAFBC_BOUNDING_BOX_Y_START_S2 0x3a57 1656 #define VPU_MAFBC_BOUNDING_BOX_Y_END_S2 0x3a58 1657 #define VPU_MAFBC_OUTPUT_BUF_ADDR_LOW_S2 0x3a59 1658 #define VPU_MAFBC_OUTPUT_BUF_ADDR_HIGH_S2 0x3a5a 1659 #define VPU_MAFBC_OUTPUT_BUF_STRIDE_S2 0x3a5b 1660 #define VPU_MAFBC_PREFETCH_CFG_S2 0x3a5c 1661 1662 #define VPU_MAFBC_HEADER_BUF_ADDR_LOW_S3 0x3a70 1663 #define VPU_MAFBC_HEADER_BUF_ADDR_HIGH_S3 0x3a71 1664 #define VPU_MAFBC_FORMAT_SPECIFIER_S3 0x3a72 1665 #define VPU_MAFBC_BUFFER_WIDTH_S3 0x3a73 1666 #define VPU_MAFBC_BUFFER_HEIGHT_S3 0x3a74 1667 #define VPU_MAFBC_BOUNDING_BOX_X_START_S3 0x3a75 1668 #define VPU_MAFBC_BOUNDING_BOX_X_END_S3 0x3a76 1669 #define VPU_MAFBC_BOUNDING_BOX_Y_START_S3 0x3a77 1670 #define VPU_MAFBC_BOUNDING_BOX_Y_END_S3 0x3a78 1671 #define VPU_MAFBC_OUTPUT_BUF_ADDR_LOW_S3 0x3a79 1672 #define VPU_MAFBC_OUTPUT_BUF_ADDR_HIGH_S3 0x3a7a 1673 #define VPU_MAFBC_OUTPUT_BUF_STRIDE_S3 0x3a7b 1674 #define VPU_MAFBC_PREFETCH_CFG_S3 0x3a7c 1675 1676 #define DOLBY_PATH_CTRL 0x1a0c 1677 #define DOLBY_BYPASS_EN(val) (val & 0xf) 1678 #define OSD_PATH_MISC_CTRL 0x1a0e 1679 #define MALI_AFBCD_TOP_CTRL 0x1a0f 1680 1681 #define VIU_OSD_BLEND_CTRL 0x39b0 1682 #define VIU_OSD_BLEND_REORDER(dest, src) ((src) << (dest * 4)) 1683 #define VIU_OSD_BLEND_DIN_EN(bits) ((bits & 0xf) << 20) 1684 #define VIU_OSD_BLEND1_DIN3_BYPASS_TO_DOUT1 BIT(24) 1685 #define VIU_OSD_BLEND1_DOUT_BYPASS_TO_BLEND2 BIT(25) 1686 #define VIU_OSD_BLEND_DIN0_BYPASS_TO_DOUT0 BIT(26) 1687 #define VIU_OSD_BLEND_BLEN2_PREMULT_EN(input) ((input & 0x3) << 27) 1688 #define VIU_OSD_BLEND_HOLD_LINES(lines) ((u32)(lines & 0x7) << 29) 1689 #define VIU_OSD_BLEND_CTRL1 0x39c0 1690 #define VIU_OSD_BLEND_DIN0_SCOPE_H 0x39b1 1691 #define VIU_OSD_BLEND_DIN0_SCOPE_V 0x39b2 1692 #define VIU_OSD_BLEND_DIN1_SCOPE_H 0x39b3 1693 #define VIU_OSD_BLEND_DIN1_SCOPE_V 0x39b4 1694 #define VIU_OSD_BLEND_DIN2_SCOPE_H 0x39b5 1695 #define VIU_OSD_BLEND_DIN2_SCOPE_V 0x39b6 1696 #define VIU_OSD_BLEND_DIN3_SCOPE_H 0x39b7 1697 #define VIU_OSD_BLEND_DIN3_SCOPE_V 0x39b8 1698 #define VIU_OSD_BLEND_DUMMY_DATA0 0x39b9 1699 #define VIU_OSD_BLEND_DUMMY_ALPHA 0x39ba 1700 #define VIU_OSD_BLEND_BLEND0_SIZE 0x39bb 1701 #define VIU_OSD_BLEND_BLEND1_SIZE 0x39bc 1702 #define VIU_OSD_BLEND_RO_CURRENT_XY 0x39bf 1703 1704 #define VPP_OUT_H_V_SIZE 0x1da5 1705 1706 #define VPP_VD2_HDR_IN_SIZE 0x1df0 1707 #define VPP_OSD1_IN_SIZE 0x1df1 1708 #define VPP_GCLK_CTRL2 0x1df2 1709 #define VD2_PPS_DUMMY_DATA 0x1df4 1710 #define VPP_OSD1_BLD_H_SCOPE 0x1df5 1711 #define VPP_OSD1_BLD_V_SCOPE 0x1df6 1712 #define VPP_OSD2_BLD_H_SCOPE 0x1df7 1713 #define VPP_OSD2_BLD_V_SCOPE 0x1df8 1714 #define VPP_WRBAK_CTRL 0x1df9 1715 #define VPP_SLEEP_CTRL 0x1dfa 1716 #define VD1_BLEND_SRC_CTRL 0x1dfb 1717 #define VD2_BLEND_SRC_CTRL 0x1dfc 1718 #define VD_BLEND_PREBLD_SRC_VD1 (1 << 0) 1719 #define VD_BLEND_PREBLD_SRC_VD2 (2 << 0) 1720 #define VD_BLEND_PREBLD_SRC_OSD1 (3 << 0) 1721 #define VD_BLEND_PREBLD_SRC_OSD2 (4 << 0) 1722 #define VD_BLEND_PREBLD_PREMULT_EN BIT(4) 1723 #define VD_BLEND_POSTBLD_SRC_VD1 (1 << 8) 1724 #define VD_BLEND_POSTBLD_SRC_VD2 (2 << 8) 1725 #define VD_BLEND_POSTBLD_SRC_OSD1 (3 << 8) 1726 #define VD_BLEND_POSTBLD_SRC_OSD2 (4 << 8) 1727 #define VD_BLEND_POSTBLD_PREMULT_EN BIT(16) 1728 #define OSD1_BLEND_SRC_CTRL 0x1dfd 1729 #define OSD2_BLEND_SRC_CTRL 0x1dfe 1730 #define OSD_BLEND_POSTBLD_SRC_VD1 (1 << 8) 1731 #define OSD_BLEND_POSTBLD_SRC_VD2 (2 << 8) 1732 #define OSD_BLEND_POSTBLD_SRC_OSD1 (3 << 8) 1733 #define OSD_BLEND_POSTBLD_SRC_OSD2 (4 << 8) 1734 #define OSD_BLEND_PATH_SEL_ENABLE BIT(20) 1735 1736 #define VPP_POST_BLEND_BLEND_DUMMY_DATA 0x3968 1737 #define VPP_POST_BLEND_DUMMY_ALPHA 0x3969 1738 #define VPP_RDARB_MODE 0x3978 1739 #define VPP_RDARB_REQEN_SLV 0x3979 1740 1741 #endif /* __MESON_REGISTERS_H */ 1742