1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2015 Google, Inc 4 * Copyright 2014 Rockchip Inc. 5 */ 6 7 #ifndef _ASM_ARCH_VOP_RK3288_H 8 #define _ASM_ARCH_VOP_RK3288_H 9 10 struct rk3288_vop { 11 u32 reg_cfg_done; 12 u32 version_info; 13 u32 sys_ctrl; 14 u32 sys_ctrl1; 15 u32 dsp_ctrl0; 16 u32 dsp_ctrl1; 17 u32 dsp_bg; 18 u32 mcu_ctrl; 19 u32 intr_ctrl0; 20 u32 intr_ctrl1; 21 u32 intr_reserved0; 22 u32 intr_reserved1; 23 24 u32 win0_ctrl0; 25 u32 win0_ctrl1; 26 u32 win0_color_key; 27 u32 win0_vir; 28 u32 win0_yrgb_mst; 29 u32 win0_cbr_mst; 30 u32 win0_act_info; 31 u32 win0_dsp_info; 32 u32 win0_dsp_st; 33 u32 win0_scl_factor_yrgb; 34 u32 win0_scl_factor_cbr; 35 u32 win0_scl_offset; 36 u32 win0_src_alpha_ctrl; 37 u32 win0_dst_alpha_ctrl; 38 u32 win0_fading_ctrl; 39 u32 win0_reserved0; 40 41 u32 win1_ctrl0; 42 u32 win1_ctrl1; 43 u32 win1_color_key; 44 u32 win1_vir; 45 u32 win1_yrgb_mst; 46 u32 win1_cbr_mst; 47 u32 win1_act_info; 48 u32 win1_dsp_info; 49 u32 win1_dsp_st; 50 u32 win1_scl_factor_yrgb; 51 u32 win1_scl_factor_cbr; 52 u32 win1_scl_offset; 53 u32 win1_src_alpha_ctrl; 54 u32 win1_dst_alpha_ctrl; 55 u32 win1_fading_ctrl; 56 u32 win1_reservd0; 57 u32 reserved2[48]; 58 u32 post_dsp_hact_info; 59 u32 post_dsp_vact_info; 60 u32 post_scl_factor_yrgb; 61 u32 post_reserved; 62 u32 post_scl_ctrl; 63 u32 post_dsp_vact_info_f1; 64 u32 dsp_htotal_hs_end; 65 u32 dsp_hact_st_end; 66 u32 dsp_vtotal_vs_end; 67 u32 dsp_vact_st_end; 68 u32 dsp_vs_st_end_f1; 69 u32 dsp_vact_st_end_f1; 70 }; 71 check_member(rk3288_vop, dsp_vact_st_end_f1, 0x19c); 72 73 enum rockchip_fb_data_format_t { 74 ARGB8888 = 0, 75 RGB888 = 1, 76 RGB565 = 2, 77 }; 78 79 enum { 80 LB_YUV_3840X5 = 0x0, 81 LB_YUV_2560X8 = 0x1, 82 LB_RGB_3840X2 = 0x2, 83 LB_RGB_2560X4 = 0x3, 84 LB_RGB_1920X5 = 0x4, 85 LB_RGB_1280X8 = 0x5 86 }; 87 88 #if defined(CONFIG_ROCKCHIP_RK3399) 89 enum vop_modes { 90 VOP_MODE_EDP = 0, 91 VOP_MODE_MIPI, 92 VOP_MODE_HDMI, 93 VOP_MODE_MIPI1, 94 VOP_MODE_DP, 95 VOP_MODE_NONE, 96 }; 97 #else 98 enum vop_modes { 99 VOP_MODE_EDP = 0, 100 VOP_MODE_HDMI, 101 VOP_MODE_LVDS, 102 VOP_MODE_MIPI, 103 VOP_MODE_NONE, 104 VOP_MODE_AUTO_DETECT, 105 VOP_MODE_UNKNOWN, 106 }; 107 #endif 108 109 /* VOP_VERSION_INFO */ 110 #define M_FPGA_VERSION (0xffff << 16) 111 #define M_RTL_VERSION (0xffff) 112 113 /* VOP_SYS_CTRL */ 114 #define M_AUTO_GATING_EN (1 << 23) 115 #define M_STANDBY_EN (1 << 22) 116 #define M_DMA_STOP (1 << 21) 117 #define M_MMU_EN (1 << 20) 118 #define M_DAM_BURST_LENGTH (0x3 << 18) 119 #define M_MIPI_OUT_EN (1 << 15) 120 #define M_EDP_OUT_EN (1 << 14) 121 #define M_HDMI_OUT_EN (1 << 13) 122 #define M_RGB_OUT_EN (1 << 12) 123 #define M_ALL_OUT_EN \ 124 (M_MIPI_OUT_EN | M_EDP_OUT_EN | M_HDMI_OUT_EN | M_RGB_OUT_EN) 125 #define M_EDPI_WMS_FS (1 << 10) 126 #define M_EDPI_WMS_MODE (1 << 9) 127 #define M_EDPI_HALT_EN (1 << 8) 128 #define M_DOUB_CH_OVERLAP_NUM (0xf << 4) 129 #define M_DOUB_CHANNEL_EN (1 << 3) 130 #define M_DIRECT_PATH_LAYER_SEL (0x3 << 1) 131 #define M_DIRECT_PATH_EN (1) 132 133 #define V_AUTO_GATING_EN(x) (((x) & 1) << 23) 134 #define V_STANDBY_EN(x) (((x) & 1) << 22) 135 #define V_DMA_STOP(x) (((x) & 1) << 21) 136 #define V_MMU_EN(x) (((x) & 1) << 20) 137 #define V_DMA_BURST_LENGTH(x) (((x) & 3) << 18) 138 #define V_MIPI_OUT_EN(x) (((x) & 1) << 15) 139 #define V_EDP_OUT_EN(x) (((x) & 1) << 14) 140 #define V_HDMI_OUT_EN(x) (((x) & 1) << 13) 141 #define V_RGB_OUT_EN(x) (((x) & 1) << 12) 142 #define V_EDPI_WMS_FS(x) (((x) & 1) << 10) 143 #define V_EDPI_WMS_MODE(x) (((x) & 1) << 9) 144 #define V_EDPI_HALT_EN(x) (((x)&1)<<8) 145 #define V_DOUB_CH_OVERLAP_NUM(x) (((x) & 0xf) << 4) 146 #define V_DOUB_CHANNEL_EN(x) (((x) & 1) << 3) 147 #define V_DIRECT_PATH_LAYER_SEL(x) (((x) & 3) << 1) 148 #define V_DIRECT_PATH_EN(x) ((x) & 1) 149 150 /* VOP_SYS_CTRL1 */ 151 #define M_AXI_OUTSTANDING_MAX_NUM (0x1f << 13) 152 #define M_AXI_MAX_OUTSTANDING_EN (1 << 12) 153 #define M_NOC_WIN_QOS (3 << 10) 154 #define M_NOC_QOS_EN (1 << 9) 155 #define M_NOC_HURRY_THRESHOLD (0x3f << 3) 156 #define M_NOC_HURRY_VALUE (0x3 << 1) 157 #define M_NOC_HURRY_EN (1) 158 159 #define V_AXI_OUTSTANDING_MAX_NUM(x) (((x) & 0x1f) << 13) 160 #define V_AXI_MAX_OUTSTANDING_EN(x) (((x) & 1) << 12) 161 #define V_NOC_WIN_QOS(x) (((x) & 3) << 10) 162 #define V_NOC_QOS_EN(x) (((x) & 1) << 9) 163 #define V_NOC_HURRY_THRESHOLD(x) (((x) & 0x3f) << 3) 164 #define V_NOC_HURRY_VALUE(x) (((x) & 3) << 1) 165 #define V_NOC_HURRY_EN(x) ((x) & 1) 166 167 /* VOP_DSP_CTRL0 */ 168 #define M_DSP_Y_MIR_EN (1 << 23) 169 #define M_DSP_X_MIR_EN (1 << 22) 170 #define M_DSP_YUV_CLIP (1 << 21) 171 #define M_DSP_CCIR656_AVG (1 << 20) 172 #define M_DSP_BLACK_EN (1 << 19) 173 #define M_DSP_BLANK_EN (1 << 18) 174 #define M_DSP_OUT_ZERO (1 << 17) 175 #define M_DSP_DUMMY_SWAP (1 << 16) 176 #define M_DSP_DELTA_SWAP (1 << 15) 177 #define M_DSP_RG_SWAP (1 << 14) 178 #define M_DSP_RB_SWAP (1 << 13) 179 #define M_DSP_BG_SWAP (1 << 12) 180 #define M_DSP_FIELD_POL (1 << 11) 181 #define M_DSP_INTERLACE (1 << 10) 182 #define M_DSP_DDR_PHASE (1 << 9) 183 #define M_DSP_DCLK_DDR (1 << 8) 184 #define M_DSP_DCLK_POL (1 << 7) 185 #define M_DSP_DEN_POL (1 << 6) 186 #define M_DSP_VSYNC_POL (1 << 5) 187 #define M_DSP_HSYNC_POL (1 << 4) 188 #define M_DSP_OUT_MODE (0xf) 189 190 #define V_DSP_Y_MIR_EN(x) (((x) & 1) << 23) 191 #define V_DSP_X_MIR_EN(x) (((x) & 1) << 22) 192 #define V_DSP_YUV_CLIP(x) (((x) & 1) << 21) 193 #define V_DSP_CCIR656_AVG(x) (((x) & 1) << 20) 194 #define V_DSP_BLACK_EN(x) (((x) & 1) << 19) 195 #define V_DSP_BLANK_EN(x) (((x) & 1) << 18) 196 #define V_DSP_OUT_ZERO(x) (((x) & 1) << 17) 197 #define V_DSP_DUMMY_SWAP(x) (((x) & 1) << 16) 198 #define V_DSP_DELTA_SWAP(x) (((x) & 1) << 15) 199 #define V_DSP_RG_SWAP(x) (((x) & 1) << 14) 200 #define V_DSP_RB_SWAP(x) (((x) & 1) << 13) 201 #define V_DSP_BG_SWAP(x) (((x) & 1) << 12) 202 #define V_DSP_FIELD_POL(x) (((x) & 1) << 11) 203 #define V_DSP_INTERLACE(x) (((x) & 1) << 10) 204 #define V_DSP_DDR_PHASE(x) (((x) & 1) << 9) 205 #define V_DSP_DCLK_DDR(x) (((x) & 1) << 8) 206 #define V_DSP_DCLK_POL(x) (((x) & 1) << 7) 207 #define V_DSP_DEN_POL(x) (((x) & 1) << 6) 208 #define V_DSP_VSYNC_POL(x) (((x) & 1) << 5) 209 #define V_DSP_HSYNC_POL(x) (((x) & 1) << 4) 210 #define V_DSP_PIN_POL(x) (((x) & 0xf) << 4) 211 #define V_DSP_OUT_MODE(x) ((x) & 0xf) 212 213 /* VOP_DSP_CTRL1 */ 214 #define V_RK3399_DSP_MIPI_POL(x) ((x) << 28) 215 #define V_RK3399_DSP_EDP_POL(x) ((x) << 24) 216 #define V_RK3399_DSP_HDMI_POL(x) ((x) << 20) 217 #define V_RK3399_DSP_LVDS_POL(x) ((x) << 16) 218 219 #define M_RK3399_DSP_MIPI_POL (V_RK3399_DSP_MIPI_POL(0xf)) 220 #define M_RK3399_DSP_EDP_POL (V_RK3399_DSP_EDP_POL(0xf)) 221 #define M_RK3399_DSP_HDMI_POL (V_RK3399_DSP_HDMI_POL(0xf)) 222 #define M_RK3399_DSP_LVDS_POL (V_RK3399_DSP_LVDS_POL(0xf)) 223 224 #define M_DSP_LAYER3_SEL (3 << 14) 225 #define M_DSP_LAYER2_SEL (3 << 12) 226 #define M_DSP_LAYER1_SEL (3 << 10) 227 #define M_DSP_LAYER0_SEL (3 << 8) 228 #define M_DITHER_UP_EN (1 << 6) 229 #define M_DITHER_DOWN_SEL (1 << 4) 230 #define M_DITHER_DOWN_MODE (1 << 3) 231 #define M_DITHER_DOWN_EN (1 << 2) 232 #define M_PRE_DITHER_DOWN_EN (1 << 1) 233 #define M_DSP_LUT_EN (1) 234 235 #define V_DSP_LAYER3_SEL(x) (((x) & 3) << 14) 236 #define V_DSP_LAYER2_SEL(x) (((x) & 3) << 12) 237 #define V_DSP_LAYER1_SEL(x) (((x) & 3) << 10) 238 #define V_DSP_LAYER0_SEL(x) (((x) & 3) << 8) 239 #define V_DITHER_UP_EN(x) (((x) & 1) << 6) 240 #define V_DITHER_DOWN_SEL(x) (((x) & 1) << 4) 241 #define V_DITHER_DOWN_MODE(x) (((x) & 1) << 3) 242 #define V_DITHER_DOWN_EN(x) (((x) & 1) << 2) 243 #define V_PRE_DITHER_DOWN_EN(x) (((x) & 1) << 1) 244 #define V_DSP_LUT_EN(x) ((x)&1) 245 246 /* VOP_DSP_BG */ 247 #define M_DSP_BG_RED (0x3f << 20) 248 #define M_DSP_BG_GREEN (0x3f << 10) 249 #define M_DSP_BG_BLUE (0x3f << 0) 250 251 #define V_DSP_BG_RED(x) (((x) & 0x3f) << 20) 252 #define V_DSP_BG_GREEN(x) (((x) & 0x3f) << 10) 253 #define V_DSP_BG_BLUE(x) (((x) & 0x3f) << 0) 254 255 /* VOP_WIN0_CTRL0 */ 256 #define M_WIN0_YUV_CLIP (1 << 20) 257 #define M_WIN0_CBR_DEFLICK (1 << 19) 258 #define M_WIN0_YRGB_DEFLICK (1 << 18) 259 #define M_WIN0_PPAS_ZERO_EN (1 << 16) 260 #define M_WIN0_UV_SWAP (1 << 15) 261 #define M_WIN0_MID_SWAP (1 << 14) 262 #define M_WIN0_ALPHA_SWAP (1 << 13) 263 #define M_WIN0_RB_SWAP (1 << 12) 264 #define M_WIN0_CSC_MODE (3 << 10) 265 #define M_WIN0_NO_OUTSTANDING (1 << 9) 266 #define M_WIN0_INTERLACE_READ (1 << 8) 267 #define M_WIN0_LB_MODE (7 << 5) 268 #define M_WIN0_FMT_10 (1 << 4) 269 #define M_WIN0_DATA_FMT (7 << 1) 270 #define M_WIN0_EN (1 << 0) 271 272 #define V_WIN0_YUV_CLIP(x) (((x) & 1) << 20) 273 #define V_WIN0_CBR_DEFLICK(x) (((x) & 1) << 19) 274 #define V_WIN0_YRGB_DEFLICK(x) (((x) & 1) << 18) 275 #define V_WIN0_PPAS_ZERO_EN(x) (((x) & 1) << 16) 276 #define V_WIN0_UV_SWAP(x) (((x) & 1) << 15) 277 #define V_WIN0_MID_SWAP(x) (((x) & 1) << 14) 278 #define V_WIN0_ALPHA_SWAP(x) (((x) & 1) << 13) 279 #define V_WIN0_RB_SWAP(x) (((x) & 1) << 12) 280 #define V_WIN0_CSC_MODE(x) (((x) & 3) << 10) 281 #define V_WIN0_NO_OUTSTANDING(x) (((x) & 1) << 9) 282 #define V_WIN0_INTERLACE_READ(x) (((x) & 1) << 8) 283 #define V_WIN0_LB_MODE(x) (((x) & 7) << 5) 284 #define V_WIN0_FMT_10(x) (((x) & 1) << 4) 285 #define V_WIN0_DATA_FMT(x) (((x) & 7) << 1) 286 #define V_WIN0_EN(x) ((x) & 1) 287 288 /* VOP_WIN0_CTRL1 */ 289 #define M_WIN0_CBR_VSD_MODE (1 << 31) 290 #define M_WIN0_CBR_VSU_MODE (1 << 30) 291 #define M_WIN0_CBR_HSD_MODE (3 << 28) 292 #define M_WIN0_CBR_VER_SCL_MODE (3 << 26) 293 #define M_WIN0_CBR_HOR_SCL_MODE (3 << 24) 294 #define M_WIN0_YRGB_VSD_MODE (1 << 23) 295 #define M_WIN0_YRGB_VSU_MODE (1 << 22) 296 #define M_WIN0_YRGB_HSD_MODE (3 << 20) 297 #define M_WIN0_YRGB_VER_SCL_MODE (3 << 18) 298 #define M_WIN0_YRGB_HOR_SCL_MODE (3 << 16) 299 #define M_WIN0_LINE_LOAD_MODE (1 << 15) 300 #define M_WIN0_CBR_AXI_GATHER_NUM (7 << 12) 301 #define M_WIN0_YRGB_AXI_GATHER_NUM (0xf << 8) 302 #define M_WIN0_VSD_CBR_GT2 (1 << 7) 303 #define M_WIN0_VSD_CBR_GT4 (1 << 6) 304 #define M_WIN0_VSD_YRGB_GT2 (1 << 5) 305 #define M_WIN0_VSD_YRGB_GT4 (1 << 4) 306 #define M_WIN0_BIC_COE_SEL (3 << 2) 307 #define M_WIN0_CBR_AXI_GATHER_EN (1 << 1) 308 #define M_WIN0_YRGB_AXI_GATHER_EN (1) 309 310 #define V_WIN0_CBR_VSD_MODE(x) (((x) & 1) << 31) 311 #define V_WIN0_CBR_VSU_MODE(x) (((x) & 1) << 30) 312 #define V_WIN0_CBR_HSD_MODE(x) (((x) & 3) << 28) 313 #define V_WIN0_CBR_VER_SCL_MODE(x) (((x) & 3) << 26) 314 #define V_WIN0_CBR_HOR_SCL_MODE(x) (((x) & 3) << 24) 315 #define V_WIN0_YRGB_VSD_MODE(x) (((x) & 1) << 23) 316 #define V_WIN0_YRGB_VSU_MODE(x) (((x) & 1) << 22) 317 #define V_WIN0_YRGB_HSD_MODE(x) (((x) & 3) << 20) 318 #define V_WIN0_YRGB_VER_SCL_MODE(x) (((x) & 3) << 18) 319 #define V_WIN0_YRGB_HOR_SCL_MODE(x) (((x) & 3) << 16) 320 #define V_WIN0_LINE_LOAD_MODE(x) (((x) & 1) << 15) 321 #define V_WIN0_CBR_AXI_GATHER_NUM(x) (((x) & 7) << 12) 322 #define V_WIN0_YRGB_AXI_GATHER_NUM(x) (((x) & 0xf) << 8) 323 #define V_WIN0_VSD_CBR_GT2(x) (((x) & 1) << 7) 324 #define V_WIN0_VSD_CBR_GT4(x) (((x) & 1) << 6) 325 #define V_WIN0_VSD_YRGB_GT2(x) (((x) & 1) << 5) 326 #define V_WIN0_VSD_YRGB_GT4(x) (((x) & 1) << 4) 327 #define V_WIN0_BIC_COE_SEL(x) (((x) & 3) << 2) 328 #define V_WIN0_CBR_AXI_GATHER_EN(x) (((x) & 1) << 1) 329 #define V_WIN0_YRGB_AXI_GATHER_EN(x) ((x) & 1) 330 331 /*VOP_WIN0_COLOR_KEY*/ 332 #define M_WIN0_KEY_EN (1 << 31) 333 #define M_WIN0_KEY_COLOR (0x3fffffff) 334 335 #define V_WIN0_KEY_EN(x) (((x) & 1) << 31) 336 #define V_WIN0_KEY_COLOR(x) ((x) & 0x3fffffff) 337 338 /* VOP_WIN0_VIR */ 339 #define V_ARGB888_VIRWIDTH(x) (((x) & 0x3fff) << 0) 340 #define V_RGB888_VIRWIDTH(x) (((((x * 3) >> 2)+((x) % 3)) & 0x3fff) << 0) 341 #define V_RGB565_VIRWIDTH(x) (((x / 2) & 0x3fff) << 0) 342 #define YUV_VIRWIDTH(x) (((x / 4) & 0x3fff) << 0) 343 344 /* VOP_WIN0_ACT_INFO */ 345 #define V_ACT_HEIGHT(x) (((x) & 0x1fff) << 16) 346 #define V_ACT_WIDTH(x) ((x) & 0x1fff) 347 348 /* VOP_WIN0_DSP_INFO */ 349 #define V_DSP_HEIGHT(x) (((x) & 0xfff) << 16) 350 #define V_DSP_WIDTH(x) ((x) & 0xfff) 351 352 /* VOP_WIN0_DSP_ST */ 353 #define V_DSP_YST(x) (((x) & 0x1fff) << 16) 354 #define V_DSP_XST(x) ((x) & 0x1fff) 355 356 /* VOP_WIN0_SCL_OFFSET */ 357 #define V_WIN0_VS_OFFSET_CBR(x) (((x) & 0xff) << 24) 358 #define V_WIN0_VS_OFFSET_YRGB(x) (((x) & 0xff) << 16) 359 #define V_WIN0_HS_OFFSET_CBR(x) (((x) & 0xff) << 8) 360 #define V_WIN0_HS_OFFSET_YRGB(x) ((x) & 0xff) 361 362 #define V_HSYNC(x) (((x)&0x1fff)<<0) /* hsync pulse width */ 363 #define V_HORPRD(x) (((x)&0x1fff)<<16) /* horizontal period */ 364 #define V_VSYNC(x) (((x)&0x1fff)<<0) 365 #define V_VERPRD(x) (((x)&0x1fff)<<16) 366 367 #define V_HEAP(x) (((x)&0x1fff)<<0)/* horizontal active end */ 368 #define V_HASP(x) (((x)&0x1fff)<<16)/* horizontal active start */ 369 #define V_VAEP(x) (((x)&0x1fff)<<0) 370 #define V_VASP(x) (((x)&0x1fff)<<16) 371 372 #endif 373