1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __SOC15_COMMON_H__ 25 #define __SOC15_COMMON_H__ 26 27 /* Register Access Macros */ 28 #define SOC15_REG_OFFSET(ip, inst, reg) (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) 29 30 #define __WREG32_SOC15_RLC__(reg, value, flag, hwip) \ 31 ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs && adev->gfx.rlc.funcs->sriov_wreg) ? \ 32 adev->gfx.rlc.funcs->sriov_wreg(adev, reg, value, flag, hwip) : \ 33 WREG32(reg, value)) 34 35 #define __RREG32_SOC15_RLC__(reg, flag, hwip) \ 36 ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs && adev->gfx.rlc.funcs->sriov_rreg) ? \ 37 adev->gfx.rlc.funcs->sriov_rreg(adev, reg, flag, hwip) : \ 38 RREG32(reg)) 39 40 #define WREG32_FIELD15(ip, idx, reg, field, val) \ 41 __WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \ 42 (__RREG32_SOC15_RLC__( \ 43 adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \ 44 0, ip##_HWIP) & \ 45 ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field), \ 46 0, ip##_HWIP) 47 48 #define RREG32_SOC15(ip, inst, reg) \ 49 __RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \ 50 0, ip##_HWIP) 51 52 #define RREG32_SOC15_IP(ip, reg) __RREG32_SOC15_RLC__(reg, 0, ip##_HWIP) 53 54 #define RREG32_SOC15_NO_KIQ(ip, inst, reg) \ 55 __RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \ 56 AMDGPU_REGS_NO_KIQ, ip##_HWIP) 57 58 #define RREG32_SOC15_OFFSET(ip, inst, reg, offset) \ 59 __RREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, 0, ip##_HWIP) 60 61 #define WREG32_SOC15(ip, inst, reg, value) \ 62 __WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), \ 63 value, 0, ip##_HWIP) 64 65 #define WREG32_SOC15_IP(ip, reg, value) \ 66 __WREG32_SOC15_RLC__(reg, value, 0, ip##_HWIP) 67 68 #define WREG32_SOC15_NO_KIQ(ip, inst, reg, value) \ 69 __WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, \ 70 value, AMDGPU_REGS_NO_KIQ, ip##_HWIP) 71 72 #define WREG32_SOC15_OFFSET(ip, inst, reg, offset, value) \ 73 __WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, \ 74 value, 0, ip##_HWIP) 75 76 #define SOC15_WAIT_ON_RREG(ip, inst, reg, expected_value, mask) \ 77 ({ int ret = 0; \ 78 do { \ 79 uint32_t old_ = 0; \ 80 uint32_t tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \ 81 uint32_t loop = adev->usec_timeout; \ 82 ret = 0; \ 83 while ((tmp_ & (mask)) != (expected_value)) { \ 84 if (old_ != tmp_) { \ 85 loop = adev->usec_timeout; \ 86 old_ = tmp_; \ 87 } else \ 88 udelay(1); \ 89 tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \ 90 loop--; \ 91 if (!loop) { \ 92 DRM_WARN("Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n", \ 93 inst, #reg, (unsigned)expected_value, (unsigned)(tmp_ & (mask))); \ 94 ret = -ETIMEDOUT; \ 95 break; \ 96 } \ 97 } \ 98 } while (0); \ 99 ret; \ 100 }) 101 102 #define WREG32_RLC(reg, value) \ 103 __WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_RLC, GC_HWIP) 104 105 #define WREG32_RLC_EX(prefix, reg, value) \ 106 do { \ 107 if (amdgpu_sriov_fullaccess(adev)) { \ 108 uint32_t i = 0; \ 109 uint32_t retries = 50000; \ 110 uint32_t r0 = adev->reg_offset[GC_HWIP][0][prefix##SCRATCH_REG0_BASE_IDX] + prefix##SCRATCH_REG0; \ 111 uint32_t r1 = adev->reg_offset[GC_HWIP][0][prefix##SCRATCH_REG1_BASE_IDX] + prefix##SCRATCH_REG1; \ 112 uint32_t spare_int = adev->reg_offset[GC_HWIP][0][prefix##RLC_SPARE_INT_BASE_IDX] + prefix##RLC_SPARE_INT; \ 113 WREG32(r0, value); \ 114 WREG32(r1, (reg | 0x80000000)); \ 115 WREG32(spare_int, 0x1); \ 116 for (i = 0; i < retries; i++) { \ 117 u32 tmp = RREG32(r1); \ 118 if (!(tmp & 0x80000000)) \ 119 break; \ 120 udelay(10); \ 121 } \ 122 if (i >= retries) \ 123 pr_err("timeout: rlcg program reg:0x%05x failed !\n", reg); \ 124 } else { \ 125 WREG32(reg, value); \ 126 } \ 127 } while (0) 128 129 /* shadow the registers in the callback function */ 130 #define WREG32_SOC15_RLC_SHADOW(ip, inst, reg, value) \ 131 __WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value, AMDGPU_REGS_RLC, GC_HWIP) 132 133 /* for GC only */ 134 #define RREG32_RLC(reg) \ 135 __RREG32_SOC15_RLC__(reg, AMDGPU_REGS_RLC, GC_HWIP) 136 137 #define WREG32_RLC_NO_KIQ(reg, value, hwip) \ 138 __WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_NO_KIQ | AMDGPU_REGS_RLC, hwip) 139 140 #define RREG32_RLC_NO_KIQ(reg, hwip) \ 141 __RREG32_SOC15_RLC__(reg, AMDGPU_REGS_NO_KIQ | AMDGPU_REGS_RLC, hwip) 142 143 #define WREG32_SOC15_RLC_SHADOW_EX(prefix, ip, inst, reg, value) \ 144 do { \ 145 uint32_t target_reg = adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg;\ 146 if (amdgpu_sriov_fullaccess(adev)) { \ 147 uint32_t r2 = adev->reg_offset[GC_HWIP][0][prefix##SCRATCH_REG1_BASE_IDX] + prefix##SCRATCH_REG2; \ 148 uint32_t r3 = adev->reg_offset[GC_HWIP][0][prefix##SCRATCH_REG1_BASE_IDX] + prefix##SCRATCH_REG3; \ 149 uint32_t grbm_cntl = adev->reg_offset[GC_HWIP][0][prefix##GRBM_GFX_CNTL_BASE_IDX] + prefix##GRBM_GFX_CNTL; \ 150 uint32_t grbm_idx = adev->reg_offset[GC_HWIP][0][prefix##GRBM_GFX_INDEX_BASE_IDX] + prefix##GRBM_GFX_INDEX; \ 151 if (target_reg == grbm_cntl) \ 152 WREG32(r2, value); \ 153 else if (target_reg == grbm_idx) \ 154 WREG32(r3, value); \ 155 WREG32(target_reg, value); \ 156 } else { \ 157 WREG32(target_reg, value); \ 158 } \ 159 } while (0) 160 161 #define RREG32_SOC15_RLC(ip, inst, reg) \ 162 __RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg, AMDGPU_REGS_RLC, ip##_HWIP) 163 164 #define WREG32_SOC15_RLC(ip, inst, reg, value) \ 165 do { \ 166 uint32_t target_reg = adev->reg_offset[ip##_HWIP][0][reg##_BASE_IDX] + reg;\ 167 __WREG32_SOC15_RLC__(target_reg, value, AMDGPU_REGS_RLC, ip##_HWIP); \ 168 } while (0) 169 170 #define WREG32_SOC15_RLC_EX(prefix, ip, inst, reg, value) \ 171 do { \ 172 uint32_t target_reg = adev->reg_offset[GC_HWIP][0][reg##_BASE_IDX] + reg;\ 173 WREG32_RLC_EX(prefix, target_reg, value); \ 174 } while (0) 175 176 #define WREG32_FIELD15_RLC(ip, idx, reg, field, val) \ 177 __WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg), \ 178 (__RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \ 179 AMDGPU_REGS_RLC, ip##_HWIP) & \ 180 ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field), \ 181 AMDGPU_REGS_RLC, ip##_HWIP) 182 183 #define WREG32_SOC15_OFFSET_RLC(ip, inst, reg, offset, value) \ 184 __WREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, value, AMDGPU_REGS_RLC, ip##_HWIP) 185 186 #define RREG32_SOC15_OFFSET_RLC(ip, inst, reg, offset) \ 187 __RREG32_SOC15_RLC__((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, AMDGPU_REGS_RLC, ip##_HWIP) 188 189 #endif 190