1 #ifndef __XEN_X86_DEFNS_H__ 2 #define __XEN_X86_DEFNS_H__ 3 4 /* 5 * EFLAGS bits 6 */ 7 #define X86_EFLAGS_CF 0x00000001 /* Carry Flag */ 8 #define X86_EFLAGS_MBS 0x00000002 /* Resvd bit */ 9 #define X86_EFLAGS_PF 0x00000004 /* Parity Flag */ 10 #define X86_EFLAGS_AF 0x00000010 /* Auxillary carry Flag */ 11 #define X86_EFLAGS_ZF 0x00000040 /* Zero Flag */ 12 #define X86_EFLAGS_SF 0x00000080 /* Sign Flag */ 13 #define X86_EFLAGS_TF 0x00000100 /* Trap Flag */ 14 #define X86_EFLAGS_IF 0x00000200 /* Interrupt Flag */ 15 #define X86_EFLAGS_DF 0x00000400 /* Direction Flag */ 16 #define X86_EFLAGS_OF 0x00000800 /* Overflow Flag */ 17 #define X86_EFLAGS_IOPL 0x00003000 /* IOPL mask */ 18 #define X86_EFLAGS_NT 0x00004000 /* Nested Task */ 19 #define X86_EFLAGS_RF 0x00010000 /* Resume Flag */ 20 #define X86_EFLAGS_VM 0x00020000 /* Virtual Mode */ 21 #define X86_EFLAGS_AC 0x00040000 /* Alignment Check */ 22 #define X86_EFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */ 23 #define X86_EFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */ 24 #define X86_EFLAGS_ID 0x00200000 /* CPUID detection flag */ 25 26 #define X86_EFLAGS_ARITH_MASK \ 27 (X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF | \ 28 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF) 29 30 /* 31 * Intel CPU flags in CR0 32 */ 33 #define X86_CR0_PE 0x00000001 /* Enable Protected Mode (RW) */ 34 #define X86_CR0_MP 0x00000002 /* Monitor Coprocessor (RW) */ 35 #define X86_CR0_EM 0x00000004 /* Require FPU Emulation (RO) */ 36 #define X86_CR0_TS 0x00000008 /* Task Switched (RW) */ 37 #define X86_CR0_ET 0x00000010 /* Extension type (RO) */ 38 #define X86_CR0_NE 0x00000020 /* Numeric Error Reporting (RW) */ 39 #define X86_CR0_WP 0x00010000 /* Supervisor Write Protect (RW) */ 40 #define X86_CR0_AM 0x00040000 /* Alignment Checking (RW) */ 41 #define X86_CR0_NW 0x20000000 /* Not Write-Through (RW) */ 42 #define X86_CR0_CD 0x40000000 /* Cache Disable (RW) */ 43 #define X86_CR0_PG 0x80000000 /* Paging (RW) */ 44 45 /* 46 * Intel CPU flags in CR3 47 */ 48 #define X86_CR3_NOFLUSH (_AC(1, ULL) << 63) 49 #define X86_CR3_ADDR_MASK (PAGE_MASK & PADDR_MASK) 50 #define X86_CR3_PCID_MASK _AC(0x0fff, ULL) /* Mask for PCID */ 51 52 /* 53 * Intel CPU features in CR4 54 */ 55 #define X86_CR4_VME 0x00000001 /* enable vm86 extensions */ 56 #define X86_CR4_PVI 0x00000002 /* virtual interrupts flag enable */ 57 #define X86_CR4_TSD 0x00000004 /* disable time stamp at ipl 3 */ 58 #define X86_CR4_DE 0x00000008 /* enable debugging extensions */ 59 #define X86_CR4_PSE 0x00000010 /* enable page size extensions */ 60 #define X86_CR4_PAE 0x00000020 /* enable physical address extensions */ 61 #define X86_CR4_MCE 0x00000040 /* Machine check enable */ 62 #define X86_CR4_PGE 0x00000080 /* enable global pages */ 63 #define X86_CR4_PCE 0x00000100 /* enable performance counters at ipl 3 */ 64 #define X86_CR4_OSFXSR 0x00000200 /* enable fast FPU save and restore */ 65 #define X86_CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */ 66 #define X86_CR4_UMIP 0x00000800 /* enable UMIP */ 67 #define X86_CR4_LA57 0x00001000 /* enable 5-level paging */ 68 #define X86_CR4_VMXE 0x00002000 /* enable VMX */ 69 #define X86_CR4_SMXE 0x00004000 /* enable SMX */ 70 #define X86_CR4_FSGSBASE 0x00010000 /* enable {rd,wr}{fs,gs}base */ 71 #define X86_CR4_PCIDE 0x00020000 /* enable PCID */ 72 #define X86_CR4_OSXSAVE 0x00040000 /* enable XSAVE/XRSTOR */ 73 #define X86_CR4_SMEP 0x00100000 /* enable SMEP */ 74 #define X86_CR4_SMAP 0x00200000 /* enable SMAP */ 75 #define X86_CR4_PKE 0x00400000 /* enable PKE */ 76 #define X86_CR4_CET 0x00800000 /* Control-flow Enforcement Technology */ 77 78 /* 79 * XSTATE component flags in XCR0 80 */ 81 #define X86_XCR0_FP_POS 0 82 #define X86_XCR0_FP (1ULL << X86_XCR0_FP_POS) 83 #define X86_XCR0_SSE_POS 1 84 #define X86_XCR0_SSE (1ULL << X86_XCR0_SSE_POS) 85 #define X86_XCR0_YMM_POS 2 86 #define X86_XCR0_YMM (1ULL << X86_XCR0_YMM_POS) 87 #define X86_XCR0_BNDREGS_POS 3 88 #define X86_XCR0_BNDREGS (1ULL << X86_XCR0_BNDREGS_POS) 89 #define X86_XCR0_BNDCSR_POS 4 90 #define X86_XCR0_BNDCSR (1ULL << X86_XCR0_BNDCSR_POS) 91 #define X86_XCR0_OPMASK_POS 5 92 #define X86_XCR0_OPMASK (1ULL << X86_XCR0_OPMASK_POS) 93 #define X86_XCR0_ZMM_POS 6 94 #define X86_XCR0_ZMM (1ULL << X86_XCR0_ZMM_POS) 95 #define X86_XCR0_HI_ZMM_POS 7 96 #define X86_XCR0_HI_ZMM (1ULL << X86_XCR0_HI_ZMM_POS) 97 #define X86_XCR0_PKRU_POS 9 98 #define X86_XCR0_PKRU (1ULL << X86_XCR0_PKRU_POS) 99 #define X86_XCR0_LWP_POS 62 100 #define X86_XCR0_LWP (1ULL << X86_XCR0_LWP_POS) 101 102 /* 103 * Debug status flags in DR6. 104 */ 105 #define X86_DR6_DEFAULT 0xffff0ff0 /* Default %dr6 value. */ 106 107 /* 108 * Debug control flags in DR7. 109 */ 110 #define X86_DR7_DEFAULT 0x00000400 /* Default %dr7 value. */ 111 112 /* 113 * Invalidation types for the INVPCID instruction. 114 */ 115 #define X86_INVPCID_INDIV_ADDR 0 116 #define X86_INVPCID_SINGLE_CTXT 1 117 #define X86_INVPCID_ALL_INCL_GLOBAL 2 118 #define X86_INVPCID_ALL_NON_GLOBAL 3 119 120 #define X86_NR_VECTORS 256 121 122 /* Exception Vectors */ 123 #define X86_EXC_DE 0 /* Divide Error */ 124 #define X86_EXC_DB 1 /* Debug Exception */ 125 #define X86_EXC_NMI 2 /* NMI */ 126 #define X86_EXC_BP 3 /* Breakpoint */ 127 #define X86_EXC_OF 4 /* Overflow */ 128 #define X86_EXC_BR 5 /* BOUND Range */ 129 #define X86_EXC_UD 6 /* Invalid Opcode */ 130 #define X86_EXC_NM 7 /* Device Not Available */ 131 #define X86_EXC_DF 8 /* Double Fault */ 132 #define X86_EXC_CSO 9 /* Coprocessor Segment Overrun */ 133 #define X86_EXC_TS 10 /* Invalid TSS */ 134 #define X86_EXC_NP 11 /* Segment Not Present */ 135 #define X86_EXC_SS 12 /* Stack-Segment Fault */ 136 #define X86_EXC_GP 13 /* General Porection Fault */ 137 #define X86_EXC_PF 14 /* Page Fault */ 138 #define X86_EXC_SPV 15 /* PIC Spurious Interrupt Vector */ 139 #define X86_EXC_MF 16 /* Maths fault (x87 FPU) */ 140 #define X86_EXC_AC 17 /* Alignment Check */ 141 #define X86_EXC_MC 18 /* Machine Check */ 142 #define X86_EXC_XM 19 /* SIMD Exception */ 143 #define X86_EXC_VE 20 /* Virtualisation Exception */ 144 #define X86_EXC_CP 21 /* Control-flow Protection */ 145 #define X86_EXC_HV 28 /* Hypervisor Injection */ 146 #define X86_EXC_VC 29 /* VMM Communication */ 147 #define X86_EXC_SX 30 /* Security Exception */ 148 149 /* Bitmap of exceptions which have error codes. */ 150 #define X86_EXC_HAVE_EC \ 151 ((1u << X86_EXC_DF) | (1u << X86_EXC_TS) | (1u << X86_EXC_NP) | \ 152 (1u << X86_EXC_SS) | (1u << X86_EXC_GP) | (1u << X86_EXC_PF) | \ 153 (1u << X86_EXC_AC) | (1u << X86_EXC_CP) | \ 154 (1u << X86_EXC_VC) | (1u << X86_EXC_SX)) 155 156 #endif /* __XEN_X86_DEFNS_H__ */ 157