1 // SPDX-License-Identifier: GPL-2.0
2 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
3 
4 #include <linux/errno.h>
5 #include <linux/kernel.h>
6 #include <linux/mm.h>
7 #include <linux/smp.h>
8 #include <linux/prctl.h>
9 #include <linux/slab.h>
10 #include <linux/sched.h>
11 #include <linux/sched/idle.h>
12 #include <linux/sched/debug.h>
13 #include <linux/sched/task.h>
14 #include <linux/sched/task_stack.h>
15 #include <linux/init.h>
16 #include <linux/export.h>
17 #include <linux/pm.h>
18 #include <linux/tick.h>
19 #include <linux/random.h>
20 #include <linux/user-return-notifier.h>
21 #include <linux/dmi.h>
22 #include <linux/utsname.h>
23 #include <linux/stackprotector.h>
24 #include <linux/cpuidle.h>
25 #include <linux/acpi.h>
26 #include <linux/elf-randomize.h>
27 #include <trace/events/power.h>
28 #include <linux/hw_breakpoint.h>
29 #include <asm/cpu.h>
30 #include <asm/apic.h>
31 #include <linux/uaccess.h>
32 #include <asm/mwait.h>
33 #include <asm/fpu/api.h>
34 #include <asm/fpu/sched.h>
35 #include <asm/fpu/xstate.h>
36 #include <asm/debugreg.h>
37 #include <asm/nmi.h>
38 #include <asm/tlbflush.h>
39 #include <asm/mce.h>
40 #include <asm/vm86.h>
41 #include <asm/switch_to.h>
42 #include <asm/desc.h>
43 #include <asm/prctl.h>
44 #include <asm/spec-ctrl.h>
45 #include <asm/io_bitmap.h>
46 #include <asm/proto.h>
47 #include <asm/frame.h>
48 #include <asm/unwind.h>
49 
50 #include "process.h"
51 
52 /*
53  * per-CPU TSS segments. Threads are completely 'soft' on Linux,
54  * no more per-task TSS's. The TSS size is kept cacheline-aligned
55  * so they are allowed to end up in the .data..cacheline_aligned
56  * section. Since TSS's are completely CPU-local, we want them
57  * on exact cacheline boundaries, to eliminate cacheline ping-pong.
58  */
59 __visible DEFINE_PER_CPU_PAGE_ALIGNED(struct tss_struct, cpu_tss_rw) = {
60 	.x86_tss = {
61 		/*
62 		 * .sp0 is only used when entering ring 0 from a lower
63 		 * privilege level.  Since the init task never runs anything
64 		 * but ring 0 code, there is no need for a valid value here.
65 		 * Poison it.
66 		 */
67 		.sp0 = (1UL << (BITS_PER_LONG-1)) + 1,
68 
69 #ifdef CONFIG_X86_32
70 		.sp1 = TOP_OF_INIT_STACK,
71 
72 		.ss0 = __KERNEL_DS,
73 		.ss1 = __KERNEL_CS,
74 #endif
75 		.io_bitmap_base	= IO_BITMAP_OFFSET_INVALID,
76 	 },
77 };
78 EXPORT_PER_CPU_SYMBOL(cpu_tss_rw);
79 
80 DEFINE_PER_CPU(bool, __tss_limit_invalid);
81 EXPORT_PER_CPU_SYMBOL_GPL(__tss_limit_invalid);
82 
83 /*
84  * this gets called so that we can store lazy state into memory and copy the
85  * current task into the new thread.
86  */
arch_dup_task_struct(struct task_struct * dst,struct task_struct * src)87 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
88 {
89 	memcpy(dst, src, arch_task_struct_size);
90 #ifdef CONFIG_VM86
91 	dst->thread.vm86 = NULL;
92 #endif
93 	/* Drop the copied pointer to current's fpstate */
94 	dst->thread.fpu.fpstate = NULL;
95 
96 	return 0;
97 }
98 
99 #ifdef CONFIG_X86_64
arch_release_task_struct(struct task_struct * tsk)100 void arch_release_task_struct(struct task_struct *tsk)
101 {
102 	if (fpu_state_size_dynamic())
103 		fpstate_free(&tsk->thread.fpu);
104 }
105 #endif
106 
107 /*
108  * Free thread data structures etc..
109  */
exit_thread(struct task_struct * tsk)110 void exit_thread(struct task_struct *tsk)
111 {
112 	struct thread_struct *t = &tsk->thread;
113 	struct fpu *fpu = &t->fpu;
114 
115 	if (test_thread_flag(TIF_IO_BITMAP))
116 		io_bitmap_exit(tsk);
117 
118 	free_vm86(t);
119 
120 	fpu__drop(fpu);
121 }
122 
set_new_tls(struct task_struct * p,unsigned long tls)123 static int set_new_tls(struct task_struct *p, unsigned long tls)
124 {
125 	struct user_desc __user *utls = (struct user_desc __user *)tls;
126 
127 	if (in_ia32_syscall())
128 		return do_set_thread_area(p, -1, utls, 0);
129 	else
130 		return do_set_thread_area_64(p, ARCH_SET_FS, tls);
131 }
132 
copy_thread(unsigned long clone_flags,unsigned long sp,unsigned long arg,struct task_struct * p,unsigned long tls)133 int copy_thread(unsigned long clone_flags, unsigned long sp, unsigned long arg,
134 		struct task_struct *p, unsigned long tls)
135 {
136 	struct inactive_task_frame *frame;
137 	struct fork_frame *fork_frame;
138 	struct pt_regs *childregs;
139 	int ret = 0;
140 
141 	childregs = task_pt_regs(p);
142 	fork_frame = container_of(childregs, struct fork_frame, regs);
143 	frame = &fork_frame->frame;
144 
145 	frame->bp = encode_frame_pointer(childregs);
146 	frame->ret_addr = (unsigned long) ret_from_fork;
147 	p->thread.sp = (unsigned long) fork_frame;
148 	p->thread.io_bitmap = NULL;
149 	p->thread.iopl_warn = 0;
150 	memset(p->thread.ptrace_bps, 0, sizeof(p->thread.ptrace_bps));
151 
152 #ifdef CONFIG_X86_64
153 	current_save_fsgs();
154 	p->thread.fsindex = current->thread.fsindex;
155 	p->thread.fsbase = current->thread.fsbase;
156 	p->thread.gsindex = current->thread.gsindex;
157 	p->thread.gsbase = current->thread.gsbase;
158 
159 	savesegment(es, p->thread.es);
160 	savesegment(ds, p->thread.ds);
161 #else
162 	p->thread.sp0 = (unsigned long) (childregs + 1);
163 	/*
164 	 * Clear all status flags including IF and set fixed bit. 64bit
165 	 * does not have this initialization as the frame does not contain
166 	 * flags. The flags consistency (especially vs. AC) is there
167 	 * ensured via objtool, which lacks 32bit support.
168 	 */
169 	frame->flags = X86_EFLAGS_FIXED;
170 #endif
171 
172 	fpu_clone(p, clone_flags);
173 
174 	/* Kernel thread ? */
175 	if (unlikely(p->flags & PF_KTHREAD)) {
176 		p->thread.pkru = pkru_get_init_value();
177 		memset(childregs, 0, sizeof(struct pt_regs));
178 		kthread_frame_init(frame, sp, arg);
179 		return 0;
180 	}
181 
182 	/*
183 	 * Clone current's PKRU value from hardware. tsk->thread.pkru
184 	 * is only valid when scheduled out.
185 	 */
186 	p->thread.pkru = read_pkru();
187 
188 	frame->bx = 0;
189 	*childregs = *current_pt_regs();
190 	childregs->ax = 0;
191 	if (sp)
192 		childregs->sp = sp;
193 
194 #ifdef CONFIG_X86_32
195 	task_user_gs(p) = get_user_gs(current_pt_regs());
196 #endif
197 
198 	if (unlikely(p->flags & PF_IO_WORKER)) {
199 		/*
200 		 * An IO thread is a user space thread, but it doesn't
201 		 * return to ret_after_fork().
202 		 *
203 		 * In order to indicate that to tools like gdb,
204 		 * we reset the stack and instruction pointers.
205 		 *
206 		 * It does the same kernel frame setup to return to a kernel
207 		 * function that a kernel thread does.
208 		 */
209 		childregs->sp = 0;
210 		childregs->ip = 0;
211 		kthread_frame_init(frame, sp, arg);
212 		return 0;
213 	}
214 
215 	/* Set a new TLS for the child thread? */
216 	if (clone_flags & CLONE_SETTLS)
217 		ret = set_new_tls(p, tls);
218 
219 	if (!ret && unlikely(test_tsk_thread_flag(current, TIF_IO_BITMAP)))
220 		io_bitmap_share(p);
221 
222 	return ret;
223 }
224 
pkru_flush_thread(void)225 static void pkru_flush_thread(void)
226 {
227 	/*
228 	 * If PKRU is enabled the default PKRU value has to be loaded into
229 	 * the hardware right here (similar to context switch).
230 	 */
231 	pkru_write_default();
232 }
233 
flush_thread(void)234 void flush_thread(void)
235 {
236 	struct task_struct *tsk = current;
237 
238 	flush_ptrace_hw_breakpoint(tsk);
239 	memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
240 
241 	fpu_flush_thread();
242 	pkru_flush_thread();
243 }
244 
disable_TSC(void)245 void disable_TSC(void)
246 {
247 	preempt_disable();
248 	if (!test_and_set_thread_flag(TIF_NOTSC))
249 		/*
250 		 * Must flip the CPU state synchronously with
251 		 * TIF_NOTSC in the current running context.
252 		 */
253 		cr4_set_bits(X86_CR4_TSD);
254 	preempt_enable();
255 }
256 
enable_TSC(void)257 static void enable_TSC(void)
258 {
259 	preempt_disable();
260 	if (test_and_clear_thread_flag(TIF_NOTSC))
261 		/*
262 		 * Must flip the CPU state synchronously with
263 		 * TIF_NOTSC in the current running context.
264 		 */
265 		cr4_clear_bits(X86_CR4_TSD);
266 	preempt_enable();
267 }
268 
get_tsc_mode(unsigned long adr)269 int get_tsc_mode(unsigned long adr)
270 {
271 	unsigned int val;
272 
273 	if (test_thread_flag(TIF_NOTSC))
274 		val = PR_TSC_SIGSEGV;
275 	else
276 		val = PR_TSC_ENABLE;
277 
278 	return put_user(val, (unsigned int __user *)adr);
279 }
280 
set_tsc_mode(unsigned int val)281 int set_tsc_mode(unsigned int val)
282 {
283 	if (val == PR_TSC_SIGSEGV)
284 		disable_TSC();
285 	else if (val == PR_TSC_ENABLE)
286 		enable_TSC();
287 	else
288 		return -EINVAL;
289 
290 	return 0;
291 }
292 
293 DEFINE_PER_CPU(u64, msr_misc_features_shadow);
294 
set_cpuid_faulting(bool on)295 static void set_cpuid_faulting(bool on)
296 {
297 	u64 msrval;
298 
299 	msrval = this_cpu_read(msr_misc_features_shadow);
300 	msrval &= ~MSR_MISC_FEATURES_ENABLES_CPUID_FAULT;
301 	msrval |= (on << MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT);
302 	this_cpu_write(msr_misc_features_shadow, msrval);
303 	wrmsrl(MSR_MISC_FEATURES_ENABLES, msrval);
304 }
305 
disable_cpuid(void)306 static void disable_cpuid(void)
307 {
308 	preempt_disable();
309 	if (!test_and_set_thread_flag(TIF_NOCPUID)) {
310 		/*
311 		 * Must flip the CPU state synchronously with
312 		 * TIF_NOCPUID in the current running context.
313 		 */
314 		set_cpuid_faulting(true);
315 	}
316 	preempt_enable();
317 }
318 
enable_cpuid(void)319 static void enable_cpuid(void)
320 {
321 	preempt_disable();
322 	if (test_and_clear_thread_flag(TIF_NOCPUID)) {
323 		/*
324 		 * Must flip the CPU state synchronously with
325 		 * TIF_NOCPUID in the current running context.
326 		 */
327 		set_cpuid_faulting(false);
328 	}
329 	preempt_enable();
330 }
331 
get_cpuid_mode(void)332 static int get_cpuid_mode(void)
333 {
334 	return !test_thread_flag(TIF_NOCPUID);
335 }
336 
set_cpuid_mode(struct task_struct * task,unsigned long cpuid_enabled)337 static int set_cpuid_mode(struct task_struct *task, unsigned long cpuid_enabled)
338 {
339 	if (!boot_cpu_has(X86_FEATURE_CPUID_FAULT))
340 		return -ENODEV;
341 
342 	if (cpuid_enabled)
343 		enable_cpuid();
344 	else
345 		disable_cpuid();
346 
347 	return 0;
348 }
349 
350 /*
351  * Called immediately after a successful exec.
352  */
arch_setup_new_exec(void)353 void arch_setup_new_exec(void)
354 {
355 	/* If cpuid was previously disabled for this task, re-enable it. */
356 	if (test_thread_flag(TIF_NOCPUID))
357 		enable_cpuid();
358 
359 	/*
360 	 * Don't inherit TIF_SSBD across exec boundary when
361 	 * PR_SPEC_DISABLE_NOEXEC is used.
362 	 */
363 	if (test_thread_flag(TIF_SSBD) &&
364 	    task_spec_ssb_noexec(current)) {
365 		clear_thread_flag(TIF_SSBD);
366 		task_clear_spec_ssb_disable(current);
367 		task_clear_spec_ssb_noexec(current);
368 		speculation_ctrl_update(task_thread_info(current)->flags);
369 	}
370 }
371 
372 #ifdef CONFIG_X86_IOPL_IOPERM
switch_to_bitmap(unsigned long tifp)373 static inline void switch_to_bitmap(unsigned long tifp)
374 {
375 	/*
376 	 * Invalidate I/O bitmap if the previous task used it. This prevents
377 	 * any possible leakage of an active I/O bitmap.
378 	 *
379 	 * If the next task has an I/O bitmap it will handle it on exit to
380 	 * user mode.
381 	 */
382 	if (tifp & _TIF_IO_BITMAP)
383 		tss_invalidate_io_bitmap();
384 }
385 
tss_copy_io_bitmap(struct tss_struct * tss,struct io_bitmap * iobm)386 static void tss_copy_io_bitmap(struct tss_struct *tss, struct io_bitmap *iobm)
387 {
388 	/*
389 	 * Copy at least the byte range of the incoming tasks bitmap which
390 	 * covers the permitted I/O ports.
391 	 *
392 	 * If the previous task which used an I/O bitmap had more bits
393 	 * permitted, then the copy needs to cover those as well so they
394 	 * get turned off.
395 	 */
396 	memcpy(tss->io_bitmap.bitmap, iobm->bitmap,
397 	       max(tss->io_bitmap.prev_max, iobm->max));
398 
399 	/*
400 	 * Store the new max and the sequence number of this bitmap
401 	 * and a pointer to the bitmap itself.
402 	 */
403 	tss->io_bitmap.prev_max = iobm->max;
404 	tss->io_bitmap.prev_sequence = iobm->sequence;
405 }
406 
407 /**
408  * tss_update_io_bitmap - Update I/O bitmap before exiting to usermode
409  */
native_tss_update_io_bitmap(void)410 void native_tss_update_io_bitmap(void)
411 {
412 	struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw);
413 	struct thread_struct *t = &current->thread;
414 	u16 *base = &tss->x86_tss.io_bitmap_base;
415 
416 	if (!test_thread_flag(TIF_IO_BITMAP)) {
417 		native_tss_invalidate_io_bitmap();
418 		return;
419 	}
420 
421 	if (IS_ENABLED(CONFIG_X86_IOPL_IOPERM) && t->iopl_emul == 3) {
422 		*base = IO_BITMAP_OFFSET_VALID_ALL;
423 	} else {
424 		struct io_bitmap *iobm = t->io_bitmap;
425 
426 		/*
427 		 * Only copy bitmap data when the sequence number differs. The
428 		 * update time is accounted to the incoming task.
429 		 */
430 		if (tss->io_bitmap.prev_sequence != iobm->sequence)
431 			tss_copy_io_bitmap(tss, iobm);
432 
433 		/* Enable the bitmap */
434 		*base = IO_BITMAP_OFFSET_VALID_MAP;
435 	}
436 
437 	/*
438 	 * Make sure that the TSS limit is covering the IO bitmap. It might have
439 	 * been cut down by a VMEXIT to 0x67 which would cause a subsequent I/O
440 	 * access from user space to trigger a #GP because tbe bitmap is outside
441 	 * the TSS limit.
442 	 */
443 	refresh_tss_limit();
444 }
445 #else /* CONFIG_X86_IOPL_IOPERM */
switch_to_bitmap(unsigned long tifp)446 static inline void switch_to_bitmap(unsigned long tifp) { }
447 #endif
448 
449 #ifdef CONFIG_SMP
450 
451 struct ssb_state {
452 	struct ssb_state	*shared_state;
453 	raw_spinlock_t		lock;
454 	unsigned int		disable_state;
455 	unsigned long		local_state;
456 };
457 
458 #define LSTATE_SSB	0
459 
460 static DEFINE_PER_CPU(struct ssb_state, ssb_state);
461 
speculative_store_bypass_ht_init(void)462 void speculative_store_bypass_ht_init(void)
463 {
464 	struct ssb_state *st = this_cpu_ptr(&ssb_state);
465 	unsigned int this_cpu = smp_processor_id();
466 	unsigned int cpu;
467 
468 	st->local_state = 0;
469 
470 	/*
471 	 * Shared state setup happens once on the first bringup
472 	 * of the CPU. It's not destroyed on CPU hotunplug.
473 	 */
474 	if (st->shared_state)
475 		return;
476 
477 	raw_spin_lock_init(&st->lock);
478 
479 	/*
480 	 * Go over HT siblings and check whether one of them has set up the
481 	 * shared state pointer already.
482 	 */
483 	for_each_cpu(cpu, topology_sibling_cpumask(this_cpu)) {
484 		if (cpu == this_cpu)
485 			continue;
486 
487 		if (!per_cpu(ssb_state, cpu).shared_state)
488 			continue;
489 
490 		/* Link it to the state of the sibling: */
491 		st->shared_state = per_cpu(ssb_state, cpu).shared_state;
492 		return;
493 	}
494 
495 	/*
496 	 * First HT sibling to come up on the core.  Link shared state of
497 	 * the first HT sibling to itself. The siblings on the same core
498 	 * which come up later will see the shared state pointer and link
499 	 * themselves to the state of this CPU.
500 	 */
501 	st->shared_state = st;
502 }
503 
504 /*
505  * Logic is: First HT sibling enables SSBD for both siblings in the core
506  * and last sibling to disable it, disables it for the whole core. This how
507  * MSR_SPEC_CTRL works in "hardware":
508  *
509  *  CORE_SPEC_CTRL = THREAD0_SPEC_CTRL | THREAD1_SPEC_CTRL
510  */
amd_set_core_ssb_state(unsigned long tifn)511 static __always_inline void amd_set_core_ssb_state(unsigned long tifn)
512 {
513 	struct ssb_state *st = this_cpu_ptr(&ssb_state);
514 	u64 msr = x86_amd_ls_cfg_base;
515 
516 	if (!static_cpu_has(X86_FEATURE_ZEN)) {
517 		msr |= ssbd_tif_to_amd_ls_cfg(tifn);
518 		wrmsrl(MSR_AMD64_LS_CFG, msr);
519 		return;
520 	}
521 
522 	if (tifn & _TIF_SSBD) {
523 		/*
524 		 * Since this can race with prctl(), block reentry on the
525 		 * same CPU.
526 		 */
527 		if (__test_and_set_bit(LSTATE_SSB, &st->local_state))
528 			return;
529 
530 		msr |= x86_amd_ls_cfg_ssbd_mask;
531 
532 		raw_spin_lock(&st->shared_state->lock);
533 		/* First sibling enables SSBD: */
534 		if (!st->shared_state->disable_state)
535 			wrmsrl(MSR_AMD64_LS_CFG, msr);
536 		st->shared_state->disable_state++;
537 		raw_spin_unlock(&st->shared_state->lock);
538 	} else {
539 		if (!__test_and_clear_bit(LSTATE_SSB, &st->local_state))
540 			return;
541 
542 		raw_spin_lock(&st->shared_state->lock);
543 		st->shared_state->disable_state--;
544 		if (!st->shared_state->disable_state)
545 			wrmsrl(MSR_AMD64_LS_CFG, msr);
546 		raw_spin_unlock(&st->shared_state->lock);
547 	}
548 }
549 #else
amd_set_core_ssb_state(unsigned long tifn)550 static __always_inline void amd_set_core_ssb_state(unsigned long tifn)
551 {
552 	u64 msr = x86_amd_ls_cfg_base | ssbd_tif_to_amd_ls_cfg(tifn);
553 
554 	wrmsrl(MSR_AMD64_LS_CFG, msr);
555 }
556 #endif
557 
amd_set_ssb_virt_state(unsigned long tifn)558 static __always_inline void amd_set_ssb_virt_state(unsigned long tifn)
559 {
560 	/*
561 	 * SSBD has the same definition in SPEC_CTRL and VIRT_SPEC_CTRL,
562 	 * so ssbd_tif_to_spec_ctrl() just works.
563 	 */
564 	wrmsrl(MSR_AMD64_VIRT_SPEC_CTRL, ssbd_tif_to_spec_ctrl(tifn));
565 }
566 
567 /*
568  * Update the MSRs managing speculation control, during context switch.
569  *
570  * tifp: Previous task's thread flags
571  * tifn: Next task's thread flags
572  */
__speculation_ctrl_update(unsigned long tifp,unsigned long tifn)573 static __always_inline void __speculation_ctrl_update(unsigned long tifp,
574 						      unsigned long tifn)
575 {
576 	unsigned long tif_diff = tifp ^ tifn;
577 	u64 msr = x86_spec_ctrl_base;
578 	bool updmsr = false;
579 
580 	lockdep_assert_irqs_disabled();
581 
582 	/* Handle change of TIF_SSBD depending on the mitigation method. */
583 	if (static_cpu_has(X86_FEATURE_VIRT_SSBD)) {
584 		if (tif_diff & _TIF_SSBD)
585 			amd_set_ssb_virt_state(tifn);
586 	} else if (static_cpu_has(X86_FEATURE_LS_CFG_SSBD)) {
587 		if (tif_diff & _TIF_SSBD)
588 			amd_set_core_ssb_state(tifn);
589 	} else if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD) ||
590 		   static_cpu_has(X86_FEATURE_AMD_SSBD)) {
591 		updmsr |= !!(tif_diff & _TIF_SSBD);
592 		msr |= ssbd_tif_to_spec_ctrl(tifn);
593 	}
594 
595 	/* Only evaluate TIF_SPEC_IB if conditional STIBP is enabled. */
596 	if (IS_ENABLED(CONFIG_SMP) &&
597 	    static_branch_unlikely(&switch_to_cond_stibp)) {
598 		updmsr |= !!(tif_diff & _TIF_SPEC_IB);
599 		msr |= stibp_tif_to_spec_ctrl(tifn);
600 	}
601 
602 	if (updmsr)
603 		wrmsrl(MSR_IA32_SPEC_CTRL, msr);
604 }
605 
speculation_ctrl_update_tif(struct task_struct * tsk)606 static unsigned long speculation_ctrl_update_tif(struct task_struct *tsk)
607 {
608 	if (test_and_clear_tsk_thread_flag(tsk, TIF_SPEC_FORCE_UPDATE)) {
609 		if (task_spec_ssb_disable(tsk))
610 			set_tsk_thread_flag(tsk, TIF_SSBD);
611 		else
612 			clear_tsk_thread_flag(tsk, TIF_SSBD);
613 
614 		if (task_spec_ib_disable(tsk))
615 			set_tsk_thread_flag(tsk, TIF_SPEC_IB);
616 		else
617 			clear_tsk_thread_flag(tsk, TIF_SPEC_IB);
618 	}
619 	/* Return the updated threadinfo flags*/
620 	return task_thread_info(tsk)->flags;
621 }
622 
speculation_ctrl_update(unsigned long tif)623 void speculation_ctrl_update(unsigned long tif)
624 {
625 	unsigned long flags;
626 
627 	/* Forced update. Make sure all relevant TIF flags are different */
628 	local_irq_save(flags);
629 	__speculation_ctrl_update(~tif, tif);
630 	local_irq_restore(flags);
631 }
632 
633 /* Called from seccomp/prctl update */
speculation_ctrl_update_current(void)634 void speculation_ctrl_update_current(void)
635 {
636 	preempt_disable();
637 	speculation_ctrl_update(speculation_ctrl_update_tif(current));
638 	preempt_enable();
639 }
640 
cr4_toggle_bits_irqsoff(unsigned long mask)641 static inline void cr4_toggle_bits_irqsoff(unsigned long mask)
642 {
643 	unsigned long newval, cr4 = this_cpu_read(cpu_tlbstate.cr4);
644 
645 	newval = cr4 ^ mask;
646 	if (newval != cr4) {
647 		this_cpu_write(cpu_tlbstate.cr4, newval);
648 		__write_cr4(newval);
649 	}
650 }
651 
__switch_to_xtra(struct task_struct * prev_p,struct task_struct * next_p)652 void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p)
653 {
654 	unsigned long tifp, tifn;
655 
656 	tifn = READ_ONCE(task_thread_info(next_p)->flags);
657 	tifp = READ_ONCE(task_thread_info(prev_p)->flags);
658 
659 	switch_to_bitmap(tifp);
660 
661 	propagate_user_return_notify(prev_p, next_p);
662 
663 	if ((tifp & _TIF_BLOCKSTEP || tifn & _TIF_BLOCKSTEP) &&
664 	    arch_has_block_step()) {
665 		unsigned long debugctl, msk;
666 
667 		rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
668 		debugctl &= ~DEBUGCTLMSR_BTF;
669 		msk = tifn & _TIF_BLOCKSTEP;
670 		debugctl |= (msk >> TIF_BLOCKSTEP) << DEBUGCTLMSR_BTF_SHIFT;
671 		wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
672 	}
673 
674 	if ((tifp ^ tifn) & _TIF_NOTSC)
675 		cr4_toggle_bits_irqsoff(X86_CR4_TSD);
676 
677 	if ((tifp ^ tifn) & _TIF_NOCPUID)
678 		set_cpuid_faulting(!!(tifn & _TIF_NOCPUID));
679 
680 	if (likely(!((tifp | tifn) & _TIF_SPEC_FORCE_UPDATE))) {
681 		__speculation_ctrl_update(tifp, tifn);
682 	} else {
683 		speculation_ctrl_update_tif(prev_p);
684 		tifn = speculation_ctrl_update_tif(next_p);
685 
686 		/* Enforce MSR update to ensure consistent state */
687 		__speculation_ctrl_update(~tifn, tifn);
688 	}
689 
690 	if ((tifp ^ tifn) & _TIF_SLD)
691 		switch_to_sld(tifn);
692 }
693 
694 /*
695  * Idle related variables and functions
696  */
697 unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE;
698 EXPORT_SYMBOL(boot_option_idle_override);
699 
700 static void (*x86_idle)(void);
701 
702 #ifndef CONFIG_SMP
play_dead(void)703 static inline void play_dead(void)
704 {
705 	BUG();
706 }
707 #endif
708 
arch_cpu_idle_enter(void)709 void arch_cpu_idle_enter(void)
710 {
711 	tsc_verify_tsc_adjust(false);
712 	local_touch_nmi();
713 }
714 
arch_cpu_idle_dead(void)715 void arch_cpu_idle_dead(void)
716 {
717 	play_dead();
718 }
719 
720 /*
721  * Called from the generic idle code.
722  */
arch_cpu_idle(void)723 void arch_cpu_idle(void)
724 {
725 	x86_idle();
726 }
727 
728 /*
729  * We use this if we don't have any better idle routine..
730  */
default_idle(void)731 void __cpuidle default_idle(void)
732 {
733 	raw_safe_halt();
734 }
735 #if defined(CONFIG_APM_MODULE) || defined(CONFIG_HALTPOLL_CPUIDLE_MODULE)
736 EXPORT_SYMBOL(default_idle);
737 #endif
738 
739 #ifdef CONFIG_XEN
xen_set_default_idle(void)740 bool xen_set_default_idle(void)
741 {
742 	bool ret = !!x86_idle;
743 
744 	x86_idle = default_idle;
745 
746 	return ret;
747 }
748 #endif
749 
stop_this_cpu(void * dummy)750 void stop_this_cpu(void *dummy)
751 {
752 	local_irq_disable();
753 	/*
754 	 * Remove this CPU:
755 	 */
756 	set_cpu_online(smp_processor_id(), false);
757 	disable_local_APIC();
758 	mcheck_cpu_clear(this_cpu_ptr(&cpu_info));
759 
760 	/*
761 	 * Use wbinvd on processors that support SME. This provides support
762 	 * for performing a successful kexec when going from SME inactive
763 	 * to SME active (or vice-versa). The cache must be cleared so that
764 	 * if there are entries with the same physical address, both with and
765 	 * without the encryption bit, they don't race each other when flushed
766 	 * and potentially end up with the wrong entry being committed to
767 	 * memory.
768 	 */
769 	if (boot_cpu_has(X86_FEATURE_SME))
770 		native_wbinvd();
771 	for (;;) {
772 		/*
773 		 * Use native_halt() so that memory contents don't change
774 		 * (stack usage and variables) after possibly issuing the
775 		 * native_wbinvd() above.
776 		 */
777 		native_halt();
778 	}
779 }
780 
781 /*
782  * AMD Erratum 400 aware idle routine. We handle it the same way as C3 power
783  * states (local apic timer and TSC stop).
784  *
785  * XXX this function is completely buggered vs RCU and tracing.
786  */
amd_e400_idle(void)787 static void amd_e400_idle(void)
788 {
789 	/*
790 	 * We cannot use static_cpu_has_bug() here because X86_BUG_AMD_APIC_C1E
791 	 * gets set after static_cpu_has() places have been converted via
792 	 * alternatives.
793 	 */
794 	if (!boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) {
795 		default_idle();
796 		return;
797 	}
798 
799 	tick_broadcast_enter();
800 
801 	default_idle();
802 
803 	/*
804 	 * The switch back from broadcast mode needs to be called with
805 	 * interrupts disabled.
806 	 */
807 	raw_local_irq_disable();
808 	tick_broadcast_exit();
809 	raw_local_irq_enable();
810 }
811 
812 /*
813  * Intel Core2 and older machines prefer MWAIT over HALT for C1.
814  * We can't rely on cpuidle installing MWAIT, because it will not load
815  * on systems that support only C1 -- so the boot default must be MWAIT.
816  *
817  * Some AMD machines are the opposite, they depend on using HALT.
818  *
819  * So for default C1, which is used during boot until cpuidle loads,
820  * use MWAIT-C1 on Intel HW that has it, else use HALT.
821  */
prefer_mwait_c1_over_halt(const struct cpuinfo_x86 * c)822 static int prefer_mwait_c1_over_halt(const struct cpuinfo_x86 *c)
823 {
824 	if (c->x86_vendor != X86_VENDOR_INTEL)
825 		return 0;
826 
827 	if (!cpu_has(c, X86_FEATURE_MWAIT) || boot_cpu_has_bug(X86_BUG_MONITOR))
828 		return 0;
829 
830 	return 1;
831 }
832 
833 /*
834  * MONITOR/MWAIT with no hints, used for default C1 state. This invokes MWAIT
835  * with interrupts enabled and no flags, which is backwards compatible with the
836  * original MWAIT implementation.
837  */
mwait_idle(void)838 static __cpuidle void mwait_idle(void)
839 {
840 	if (!current_set_polling_and_test()) {
841 		if (this_cpu_has(X86_BUG_CLFLUSH_MONITOR)) {
842 			mb(); /* quirk */
843 			clflush((void *)&current_thread_info()->flags);
844 			mb(); /* quirk */
845 		}
846 
847 		__monitor((void *)&current_thread_info()->flags, 0, 0);
848 		if (!need_resched())
849 			__sti_mwait(0, 0);
850 		else
851 			raw_local_irq_enable();
852 	} else {
853 		raw_local_irq_enable();
854 	}
855 	__current_clr_polling();
856 }
857 
select_idle_routine(const struct cpuinfo_x86 * c)858 void select_idle_routine(const struct cpuinfo_x86 *c)
859 {
860 #ifdef CONFIG_SMP
861 	if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1)
862 		pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n");
863 #endif
864 	if (x86_idle || boot_option_idle_override == IDLE_POLL)
865 		return;
866 
867 	if (boot_cpu_has_bug(X86_BUG_AMD_E400)) {
868 		pr_info("using AMD E400 aware idle routine\n");
869 		x86_idle = amd_e400_idle;
870 	} else if (prefer_mwait_c1_over_halt(c)) {
871 		pr_info("using mwait in idle threads\n");
872 		x86_idle = mwait_idle;
873 	} else
874 		x86_idle = default_idle;
875 }
876 
amd_e400_c1e_apic_setup(void)877 void amd_e400_c1e_apic_setup(void)
878 {
879 	if (boot_cpu_has_bug(X86_BUG_AMD_APIC_C1E)) {
880 		pr_info("Switch to broadcast mode on CPU%d\n", smp_processor_id());
881 		local_irq_disable();
882 		tick_broadcast_force();
883 		local_irq_enable();
884 	}
885 }
886 
arch_post_acpi_subsys_init(void)887 void __init arch_post_acpi_subsys_init(void)
888 {
889 	u32 lo, hi;
890 
891 	if (!boot_cpu_has_bug(X86_BUG_AMD_E400))
892 		return;
893 
894 	/*
895 	 * AMD E400 detection needs to happen after ACPI has been enabled. If
896 	 * the machine is affected K8_INTP_C1E_ACTIVE_MASK bits are set in
897 	 * MSR_K8_INT_PENDING_MSG.
898 	 */
899 	rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
900 	if (!(lo & K8_INTP_C1E_ACTIVE_MASK))
901 		return;
902 
903 	boot_cpu_set_bug(X86_BUG_AMD_APIC_C1E);
904 
905 	if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
906 		mark_tsc_unstable("TSC halt in AMD C1E");
907 	pr_info("System has AMD C1E enabled\n");
908 }
909 
idle_setup(char * str)910 static int __init idle_setup(char *str)
911 {
912 	if (!str)
913 		return -EINVAL;
914 
915 	if (!strcmp(str, "poll")) {
916 		pr_info("using polling idle threads\n");
917 		boot_option_idle_override = IDLE_POLL;
918 		cpu_idle_poll_ctrl(true);
919 	} else if (!strcmp(str, "halt")) {
920 		/*
921 		 * When the boot option of idle=halt is added, halt is
922 		 * forced to be used for CPU idle. In such case CPU C2/C3
923 		 * won't be used again.
924 		 * To continue to load the CPU idle driver, don't touch
925 		 * the boot_option_idle_override.
926 		 */
927 		x86_idle = default_idle;
928 		boot_option_idle_override = IDLE_HALT;
929 	} else if (!strcmp(str, "nomwait")) {
930 		/*
931 		 * If the boot option of "idle=nomwait" is added,
932 		 * it means that mwait will be disabled for CPU C2/C3
933 		 * states. In such case it won't touch the variable
934 		 * of boot_option_idle_override.
935 		 */
936 		boot_option_idle_override = IDLE_NOMWAIT;
937 	} else
938 		return -1;
939 
940 	return 0;
941 }
942 early_param("idle", idle_setup);
943 
arch_align_stack(unsigned long sp)944 unsigned long arch_align_stack(unsigned long sp)
945 {
946 	if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
947 		sp -= get_random_int() % 8192;
948 	return sp & ~0xf;
949 }
950 
arch_randomize_brk(struct mm_struct * mm)951 unsigned long arch_randomize_brk(struct mm_struct *mm)
952 {
953 	return randomize_page(mm->brk, 0x02000000);
954 }
955 
956 /*
957  * Called from fs/proc with a reference on @p to find the function
958  * which called into schedule(). This needs to be done carefully
959  * because the task might wake up and we might look at a stack
960  * changing under us.
961  */
__get_wchan(struct task_struct * p)962 unsigned long __get_wchan(struct task_struct *p)
963 {
964 	struct unwind_state state;
965 	unsigned long addr = 0;
966 
967 	if (!try_get_task_stack(p))
968 		return 0;
969 
970 	for (unwind_start(&state, p, NULL, NULL); !unwind_done(&state);
971 	     unwind_next_frame(&state)) {
972 		addr = unwind_get_return_address(&state);
973 		if (!addr)
974 			break;
975 		if (in_sched_functions(addr))
976 			continue;
977 		break;
978 	}
979 
980 	put_task_stack(p);
981 
982 	return addr;
983 }
984 
do_arch_prctl_common(struct task_struct * task,int option,unsigned long arg2)985 long do_arch_prctl_common(struct task_struct *task, int option,
986 			  unsigned long arg2)
987 {
988 	switch (option) {
989 	case ARCH_GET_CPUID:
990 		return get_cpuid_mode();
991 	case ARCH_SET_CPUID:
992 		return set_cpuid_mode(task, arg2);
993 	case ARCH_GET_XCOMP_SUPP:
994 	case ARCH_GET_XCOMP_PERM:
995 	case ARCH_REQ_XCOMP_PERM:
996 		return fpu_xstate_prctl(task, option, arg2);
997 	}
998 
999 	return -EINVAL;
1000 }
1001