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/linux/drivers/staging/rtl8723bs/hal/
A Dodm_interface.h16 #define _reg_all(_name) ODM_##_name argument
17 #define _reg_ic(_name, _ic) ODM_##_name##_ic argument
18 #define _bit_all(_name) BIT_##_name argument
19 #define _bit_ic(_name, _ic) BIT_##_name##_ic argument
29 #define _reg_11N(_name) ODM_REG_##_name##_11N argument
30 #define _bit_11N(_name) ODM_BIT_##_name##_11N argument
32 #define _cat(_name, _ic_type, _func) _func##_11N(_name) argument
37 #define ODM_REG(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _reg) argument
38 #define ODM_BIT(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _bit) argument
/linux/include/linux/
A Dhwmon-sysfs.h19 #define SENSOR_ATTR(_name, _mode, _show, _store, _index) \ argument
23 #define SENSOR_ATTR_RO(_name, _func, _index) \ argument
26 #define SENSOR_ATTR_RW(_name, _func, _index) \ argument
29 #define SENSOR_ATTR_WO(_name, _func, _index) \ argument
36 #define SENSOR_DEVICE_ATTR_RO(_name, _func, _index) \ argument
39 #define SENSOR_DEVICE_ATTR_RW(_name, _func, _index) \ argument
42 #define SENSOR_DEVICE_ATTR_WO(_name, _func, _index) \ argument
58 #define SENSOR_ATTR_2_RO(_name, _func, _nr, _index) \ argument
61 #define SENSOR_ATTR_2_RW(_name, _func, _nr, _index) \ argument
64 #define SENSOR_ATTR_2_WO(_name, _func, _nr, _index) \ argument
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A Dsysfs.h115 #define __ATTR_RO(_name) { \ argument
120 #define __ATTR_RO_MODE(_name, _mode) { \ argument
126 #define __ATTR_RW_MODE(_name, _mode) { \ argument
133 #define __ATTR_WO(_name) { \ argument
153 #define __ATTRIBUTE_GROUPS(_name) \ argument
159 #define ATTRIBUTE_GROUPS(_name) \ argument
165 #define BIN_ATTRIBUTE_GROUPS(_name) \ argument
220 #define __BIN_ATTR_RW(_name, _size) \ argument
229 #define BIN_ATTR_RO(_name, _size) \ argument
232 #define BIN_ATTR_WO(_name, _size) \ argument
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A Dcounter.h339 #define COUNTER_COMP_DEVICE_U8(_name, _read, _write) \ argument
346 #define COUNTER_COMP_COUNT_U8(_name, _read, _write) \ argument
353 #define COUNTER_COMP_SIGNAL_U8(_name, _read, _write) \ argument
361 #define COUNTER_COMP_DEVICE_U64(_name, _read, _write) \ argument
368 #define COUNTER_COMP_COUNT_U64(_name, _read, _write) \ argument
375 #define COUNTER_COMP_SIGNAL_U64(_name, _read, _write) \ argument
383 #define COUNTER_COMP_DEVICE_BOOL(_name, _read, _write) \ argument
390 #define COUNTER_COMP_COUNT_BOOL(_name, _read, _write) \ argument
397 #define COUNTER_COMP_SIGNAL_BOOL(_name, _read, _write) \ argument
413 #define DEFINE_COUNTER_AVAILABLE(_name, _enums) \ argument
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/linux/drivers/clk/mediatek/
A Dclk-mt8195-infra_ao.c43 #define GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, _flag) \ argument
47 #define GATE_INFRA_AO0(_id, _name, _parent, _shift) \ argument
50 #define GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, _flag) \ argument
54 #define GATE_INFRA_AO1(_id, _name, _parent, _shift) \ argument
57 #define GATE_INFRA_AO2(_id, _name, _parent, _shift) \ argument
60 #define GATE_INFRA_AO3_FLAGS(_id, _name, _parent, _shift, _flag) \ argument
64 #define GATE_INFRA_AO3(_id, _name, _parent, _shift) \ argument
67 #define GATE_INFRA_AO4_FLAGS(_id, _name, _parent, _shift, _flag) \ argument
71 #define GATE_INFRA_AO4(_id, _name, _parent, _shift) \ argument
A Dclk-mt8167.c657 #define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) { \ argument
738 #define GATE_TOP0(_id, _name, _parent, _shift) { \ argument
747 #define GATE_TOP0_I(_id, _name, _parent, _shift) { \ argument
756 #define GATE_TOP1(_id, _name, _parent, _shift) { \ argument
765 #define GATE_TOP2(_id, _name, _parent, _shift) { \ argument
774 #define GATE_TOP2_I(_id, _name, _parent, _shift) { \ argument
783 #define GATE_TOP3(_id, _name, _parent, _shift) { \ argument
792 #define GATE_TOP4_I(_id, _name, _parent, _shift) { \ argument
801 #define GATE_TOP5(_id, _name, _parent, _shift) { \ argument
982 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
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A Dclk-mt8183-ipu_conn.c44 #define GATE_IPU_CONN(_id, _name, _parent, _shift) \ argument
48 #define GATE_IPU_CONN_APB(_id, _name, _parent, _shift) \ argument
52 #define GATE_IPU_CONN_AXI_I(_id, _name, _parent, _shift) \ argument
56 #define GATE_IPU_CONN_AXI1_I(_id, _name, _parent, _shift) \ argument
60 #define GATE_IPU_CONN_AXI2_I(_id, _name, _parent, _shift) \ argument
A Dclk-mt8516.c467 #define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) { \ argument
527 #define GATE_TOP1(_id, _name, _parent, _shift) { \ argument
536 #define GATE_TOP2(_id, _name, _parent, _shift) { \ argument
545 #define GATE_TOP2_I(_id, _name, _parent, _shift) { \ argument
554 #define GATE_TOP3(_id, _name, _parent, _shift) { \ argument
563 #define GATE_TOP4_I(_id, _name, _parent, _shift) { \ argument
572 #define GATE_TOP5(_id, _name, _parent, _shift) { \ argument
736 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
756 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
A Dclk-mt8192.c880 #define GATE_APMIXED(_id, _name, _parent, _shift) \ argument
923 #define GATE_INFRA0(_id, _name, _parent, _shift) \ argument
930 #define GATE_INFRA1(_id, _name, _parent, _shift) \ argument
933 #define GATE_INFRA2(_id, _name, _parent, _shift) \ argument
940 #define GATE_INFRA3(_id, _name, _parent, _shift) \ argument
943 #define GATE_INFRA4(_id, _name, _parent, _shift) \ argument
950 #define GATE_INFRA5(_id, _name, _parent, _shift) \ argument
1095 #define GATE_PERI(_id, _name, _parent, _shift) \ argument
1108 #define GATE_TOP(_id, _name, _parent, _shift) \ argument
1120 #define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, \ argument
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A Dclk-mt2701-aud.c18 #define GATE_AUDIO0(_id, _name, _parent, _shift) { \ argument
27 #define GATE_AUDIO1(_id, _name, _parent, _shift) { \ argument
36 #define GATE_AUDIO2(_id, _name, _parent, _shift) { \ argument
45 #define GATE_AUDIO3(_id, _name, _parent, _shift) { \ argument
A Dclk-mt8195-vdo1.c37 #define GATE_VDO1_0(_id, _name, _parent, _shift) \ argument
40 #define GATE_VDO1_1(_id, _name, _parent, _shift) \ argument
43 #define GATE_VDO1_2(_id, _name, _parent, _shift) \ argument
46 #define GATE_VDO1_3(_id, _name, _parent, _shift) \ argument
A Dclk-mt8173.c622 #define GATE_ICG(_id, _name, _parent, _shift) { \ argument
661 #define GATE_PERI0(_id, _name, _parent, _shift) { \ argument
670 #define GATE_PERI1(_id, _name, _parent, _shift) { \ argument
737 #define GATE_IMG(_id, _name, _parent, _shift) { \ argument
768 #define GATE_VDEC0(_id, _name, _parent, _shift) { \ argument
777 #define GATE_VDEC1(_id, _name, _parent, _shift) { \ argument
791 #define GATE_VENC(_id, _name, _parent, _shift) { \ argument
807 #define GATE_VENCLT(_id, _name, _parent, _shift) { \ argument
923 #define APMIXED_USB(_id, _name, _parent, _reg_ofs) { \ argument
938 #define PLL_B(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, \ argument
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/linux/include/linux/iio/
A Dsysfs.h54 #define IIO_ATTR(_name, _mode, _show, _store, _addr) \ argument
58 #define IIO_ATTR_RO(_name, _addr) \ argument
62 #define IIO_ATTR_WO(_name, _addr) \ argument
66 #define IIO_ATTR_RW(_name, _addr) \ argument
70 #define IIO_DEVICE_ATTR(_name, _mode, _show, _store, _addr) \ argument
74 #define IIO_DEVICE_ATTR_RO(_name, _addr) \ argument
78 #define IIO_DEVICE_ATTR_WO(_name, _addr) \ argument
82 #define IIO_DEVICE_ATTR_RW(_name, _addr) \ argument
86 #define IIO_DEVICE_ATTR_NAMED(_vname, _name, _mode, _show, _store, _addr) \ argument
90 #define IIO_CONST_ATTR(_name, _string) \ argument
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/linux/drivers/clk/sprd/
A Dgate.h31 #define SPRD_SC_GATE_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \ argument
47 #define SPRD_SC_GATE_CLK_OPS_UDELAY(_struct, _name, _parent, _reg, \ argument
60 #define SPRD_SC_GATE_CLK(_struct, _name, _parent, _reg, _sc_offset, \ argument
66 #define SPRD_GATE_CLK(_struct, _name, _parent, _reg, \ argument
90 #define SPRD_SC_GATE_CLK_HW_OPS(_struct, _name, _parent, _reg, \ argument
97 #define SPRD_SC_GATE_CLK_HW(_struct, _name, _parent, _reg, \ argument
104 #define SPRD_GATE_CLK_HW(_struct, _name, _parent, _reg, \ argument
110 #define SPRD_PLL_SC_GATE_CLK_HW(_struct, _name, _parent, _reg, \ argument
127 #define SPRD_SC_GATE_CLK_FW_NAME_OPS(_struct, _name, _parent, _reg, \ argument
135 #define SPRD_SC_GATE_CLK_FW_NAME(_struct, _name, _parent, _reg, \ argument
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/linux/sound/soc/mediatek/mt8195/
A Dmt8195-audsys-clk.c28 #define GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, _flags, _cgflags) {\ argument
38 #define GATE_AFE(_id, _name, _parent, _reg, _bit) \ argument
42 #define GATE_AUD0(_id, _name, _parent, _bit) \ argument
45 #define GATE_AUD1(_id, _name, _parent, _bit) \ argument
48 #define GATE_AUD3(_id, _name, _parent, _bit) \ argument
51 #define GATE_AUD4(_id, _name, _parent, _bit) \ argument
54 #define GATE_AUD5(_id, _name, _parent, _bit) \ argument
57 #define GATE_AUD6(_id, _name, _parent, _bit) \ argument
/linux/drivers/clk/meson/
A Daxg-audio.c195 #define AUD_MST_MCLK_MUX(_name, _reg) \ argument
197 #define AUD_MST_MCLK_DIV(_name, _reg) \ argument
200 #define AUD_MST_SYS_MUX(_name, _reg) \ argument
202 #define AUD_MST_SYS_DIV(_name, _reg) \ argument
209 #define AUD_MST_SCLK_DIV(_name, _reg) \ argument
216 #define AUD_MST_SCLK(_name, _reg) \ argument
223 #define AUD_MST_LRCLK(_name, _reg) \ argument
267 #define AUD_TDM_SCLK_MUX(_name, _reg) \ argument
276 #define AUD_TDM_SCLK(_name, _reg) \ argument
280 #define AUD_TDM_SCLK_WS(_name, _reg) \ argument
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/linux/include/rdma/
A Dib_sysfs.h21 #define IB_PORT_ATTR_RW(_name) \ argument
24 #define IB_PORT_ATTR_ADMIN_RW(_name) \ argument
28 #define IB_PORT_ATTR_RO(_name) \ argument
31 #define IB_PORT_ATTR_WO(_name) \ argument
/linux/fs/ext4/
A Dsysfs.c138 #define EXT4_ATTR(_name,_mode,_id) \ argument
148 #define EXT4_ATTR_OFFSET(_name,_mode,_id,_struct,_elname) \ argument
158 #define EXT4_ATTR_STRING(_name,_mode,_size,_struct,_elname) \ argument
169 #define EXT4_RO_ATTR_ES_UI(_name,_elname) \ argument
172 #define EXT4_RO_ATTR_ES_U8(_name,_elname) \ argument
175 #define EXT4_RO_ATTR_ES_U64(_name,_elname) \ argument
178 #define EXT4_RO_ATTR_ES_STRING(_name,_elname,_size) \ argument
181 #define EXT4_RW_ATTR_SBI_UI(_name,_elname) \ argument
184 #define EXT4_RW_ATTR_SBI_UL(_name,_elname) \ argument
187 #define EXT4_RO_ATTR_SBI_ATOMIC(_name,_elname) \ argument
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/linux/drivers/clk/renesas/
A Drcar-gen3-cpg.h35 #define DEF_GEN3_SD(_name, _id, _parent, _offset) \ argument
38 #define DEF_GEN3_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \ argument
43 #define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \ argument
48 #define DEF_GEN3_OSC(_name, _id, _parent, _div) \ argument
51 #define DEF_GEN3_RCKSEL(_name, _id, _parent0, _div0, _parent1, _div1) \ argument
55 #define DEF_GEN3_Z(_name, _id, _type, _parent, _div, _offset) \ argument
58 #define DEF_FIXED_RPCSRC_E3(_name, _id, _parent0, _parent1) \ argument
A Drenesas-cpg-mssr.h44 #define DEF_TYPE(_name, _id, _type...) \ argument
46 #define DEF_BASE(_name, _id, _type, _parent...) \ argument
49 #define DEF_INPUT(_name, _id) \ argument
51 #define DEF_FIXED(_name, _id, _parent, _div, _mult) \ argument
53 #define DEF_DIV6P1(_name, _id, _parent, _offset) \ argument
55 #define DEF_DIV6_RO(_name, _id, _parent, _offset, _div) \ argument
57 #define DEF_RATE(_name, _id, _rate) \ argument
75 #define DEF_MOD(_name, _mod, _parent...) \ argument
83 #define DEF_MOD_STB(_name, _mod, _parent...) \ argument
A Drzg2l-cpg.h85 #define DEF_TYPE(_name, _id, _type...) \ argument
87 #define DEF_BASE(_name, _id, _type, _parent...) \ argument
89 #define DEF_SAMPLL(_name, _id, _parent, _conf) \ argument
91 #define DEF_INPUT(_name, _id) \ argument
93 #define DEF_FIXED(_name, _id, _parent, _mult, _div) \ argument
95 #define DEF_DIV(_name, _id, _parent, _conf, _dtable, _flag) \ argument
98 #define DEF_MUX(_name, _id, _conf, _parent_names, _num_parents, _flag, \ argument
103 #define DEF_SD_MUX(_name, _id, _conf, _parent_names, _num_parents) \ argument
126 #define DEF_MOD_BASE(_name, _id, _parent, _off, _bit, _is_coupled) \ argument
136 #define DEF_MOD(_name, _id, _parent, _off, _bit) \ argument
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/linux/drivers/clk/sunxi-ng/
A Dccu_gate.h19 #define SUNXI_CCU_GATE(_struct, _name, _parent, _reg, _gate, _flags) \ argument
31 #define SUNXI_CCU_GATE_HW(_struct, _name, _parent, _reg, _gate, _flags) \ argument
43 #define SUNXI_CCU_GATE_FW(_struct, _name, _parent, _reg, _gate, _flags) \ argument
59 #define SUNXI_CCU_GATE_HWS(_struct, _name, _parent, _reg, _gate, _flags) \ argument
71 #define SUNXI_CCU_GATE_DATA(_struct, _name, _data, _reg, _gate, _flags) \ argument
/linux/include/linux/mfd/
A Dcore.h17 #define MFD_CELL_ALL(_name, _res, _pdata, _pdsize, _id, _compat, _of_reg, _use_of_reg, _match) \ argument
31 #define MFD_CELL_OF_REG(_name, _res, _pdata, _pdsize, _id, _compat, _of_reg) \ argument
34 #define MFD_CELL_OF(_name, _res, _pdata, _pdsize, _id, _compat) \ argument
37 #define MFD_CELL_ACPI(_name, _res, _pdata, _pdsize, _id, _match) \ argument
40 #define MFD_CELL_BASIC(_name, _res, _pdata, _pdsize, _id) \ argument
43 #define MFD_CELL_RES(_name, _res) \ argument
46 #define MFD_CELL_NAME(_name) \ argument
/linux/drivers/clk/mvebu/
A Darmada-37xx-periph.c129 #define PERIPH_GATE(_name, _bit) \ argument
138 #define PERIPH_MUX(_name, _shift) \ argument
148 #define PERIPH_DOUBLEDIV(_name, _reg1, _reg2, _shift1, _shift2) \ argument
159 #define PERIPH_DIV(_name, _reg, _shift, _table) \ argument
169 #define PERIPH_PM_CPU(_name, _shift1, _reg, _shift2) \ argument
199 #define REF_CLK_FULL(_name) \ argument
209 #define REF_CLK_FULL_DD(_name) \ argument
220 #define REF_CLK_GATE(_name, _parent_name) \ argument
227 #define REF_CLK_GATE_DIV(_name, _parent_name) \ argument
235 #define REF_CLK_PM_CPU(_name) \ argument
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/linux/drivers/clk/actions/
A Dowl-composite.h37 #define OWL_COMP_DIV(_struct, _name, _parent, \ argument
52 #define OWL_COMP_DIV_FIXED(_struct, _name, _parent, \ argument
66 #define OWL_COMP_FACTOR(_struct, _name, _parent, \ argument
81 #define OWL_COMP_FIXED_FACTOR(_struct, _name, _parent, \ argument
97 #define OWL_COMP_PASS(_struct, _name, _parent, \ argument

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