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Searched defs:_offset (Results 1 – 10 of 10) sorted by relevance

/u-boot/include/fsl-mc/
A Dfsl_mc_cmd.h80 #define MC_PREP_OP(_ext, _param, _offset, _width, _type, _arg) \ argument
83 #define MC_EXT_OP(_ext, _param, _offset, _width, _type, _arg) \ argument
86 #define MC_CMD_OP(_cmd, _param, _offset, _width, _type, _arg) \ argument
89 #define MC_RSP_OP(_cmd, _param, _offset, _width, _type, _arg) \ argument
/u-boot/arch/arm/cpu/armv7/bcm235xx/
A Dclk-core.h175 #define HW_SW_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ argument
187 #define HW_SW_GATE_AUTO(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ argument
198 #define HW_ENABLE_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ argument
209 #define SW_ONLY_GATE(_offset, _status_bit, _en_bit) \ argument
219 #define HW_ONLY_GATE(_offset, _status_bit) \ argument
299 #define DIVIDER(_offset, _shift, _width) \ argument
309 #define FRAC_DIVIDER(_offset, _shift, _width, _frac_width) \ argument
350 #define SELECTOR(_offset, _shift, _width) \ argument
383 #define TRIGGER(_offset, _bit) \ argument
/u-boot/arch/arm/cpu/armv7/bcm281xx/
A Dclk-core.h175 #define HW_SW_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ argument
187 #define HW_SW_GATE_AUTO(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ argument
198 #define HW_ENABLE_GATE(_offset, _status_bit, _en_bit, _hw_sw_sel_bit) \ argument
209 #define SW_ONLY_GATE(_offset, _status_bit, _en_bit) \ argument
219 #define HW_ONLY_GATE(_offset, _status_bit) \ argument
299 #define DIVIDER(_offset, _shift, _width) \ argument
309 #define FRAC_DIVIDER(_offset, _shift, _width, _frac_width) \ argument
350 #define SELECTOR(_offset, _shift, _width) \ argument
383 #define TRIGGER(_offset, _bit) \ argument
/u-boot/drivers/clk/renesas/
A Drcar-gen3-cpg.h36 #define DEF_GEN3_SD(_name, _id, _parent, _offset) \ argument
39 #define DEF_GEN3_RPC(_name, _id, _parent, _offset) \ argument
59 #define DEF_GEN3_Z(_name, _id, _type, _parent, _div, _offset) \ argument
A Drenesas-cpg-mssr.h76 #define DEF_DIV6P1(_name, _id, _parent, _offset) \ argument
78 #define DEF_DIV6_RO(_name, _id, _parent, _offset, _div) \ argument
/u-boot/arch/arm/mach-socfpga/include/mach/
A Dreset_manager.h28 #define RSTMGR_DEFINE(_bank, _offset) \ argument
/u-boot/drivers/usb/musb-new/
A Dmusb_regs.h268 #define MUSB_INDEXED_OFFSET(_epnum, _offset) \ argument
272 #define MUSB_FLAT_OFFSET(_epnum, _offset) \ argument
278 #define MUSB_TUSB_OFFSET(_epnum, _offset) \ argument
294 #define MUSB_BUSCTL_OFFSET(_epnum, _offset) \ argument
358 #define MUSB_INDEXED_OFFSET(_epnum, _offset) (_offset) argument
372 #define MUSB_BUSCTL_OFFSET(_epnum, _offset) (_offset) argument
/u-boot/include/dm/
A Ddevice.h233 #define dev_set_dma_offset(_dev, _offset) _dev->dma_offset = _offset argument
236 #define dev_set_dma_offset(_dev, _offset) argument
/u-boot/arch/arm/mach-tegra/tegra124/
A Dxusb-padctl.c85 #define TEGRA124_LANE(_name, _offset, _shift, _mask, _iddq, _funcs) \ argument
/u-boot/arch/arm/mach-tegra/tegra210/
A Dxusb-padctl.c65 #define TEGRA210_LANE(_name, _offset, _shift, _mask, _iddq, _funcs) \ argument

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