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/linux/drivers/clk/mediatek/
A Dclk-mt8195-infra_ao.c43 #define GATE_INFRA_AO0_FLAGS(_id, _name, _parent, _shift, _flag) \ argument
47 #define GATE_INFRA_AO0(_id, _name, _parent, _shift) \ argument
50 #define GATE_INFRA_AO1_FLAGS(_id, _name, _parent, _shift, _flag) \ argument
54 #define GATE_INFRA_AO1(_id, _name, _parent, _shift) \ argument
57 #define GATE_INFRA_AO2(_id, _name, _parent, _shift) \ argument
60 #define GATE_INFRA_AO3_FLAGS(_id, _name, _parent, _shift, _flag) \ argument
64 #define GATE_INFRA_AO3(_id, _name, _parent, _shift) \ argument
67 #define GATE_INFRA_AO4_FLAGS(_id, _name, _parent, _shift, _flag) \ argument
71 #define GATE_INFRA_AO4(_id, _name, _parent, _shift) \ argument
A Dclk-mt8183-ipu_conn.c44 #define GATE_IPU_CONN(_id, _name, _parent, _shift) \ argument
48 #define GATE_IPU_CONN_APB(_id, _name, _parent, _shift) \ argument
52 #define GATE_IPU_CONN_AXI_I(_id, _name, _parent, _shift) \ argument
56 #define GATE_IPU_CONN_AXI1_I(_id, _name, _parent, _shift) \ argument
60 #define GATE_IPU_CONN_AXI2_I(_id, _name, _parent, _shift) \ argument
A Dclk-mt8167.c657 #define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) { \ argument
687 #define DIV_ADJ_FLAG(_id, _name, _parent, _reg, _shift, _width, _flag) { \ argument
738 #define GATE_TOP0(_id, _name, _parent, _shift) { \ argument
747 #define GATE_TOP0_I(_id, _name, _parent, _shift) { \ argument
756 #define GATE_TOP1(_id, _name, _parent, _shift) { \ argument
765 #define GATE_TOP2(_id, _name, _parent, _shift) { \ argument
774 #define GATE_TOP2_I(_id, _name, _parent, _shift) { \ argument
783 #define GATE_TOP3(_id, _name, _parent, _shift) { \ argument
792 #define GATE_TOP4_I(_id, _name, _parent, _shift) { \ argument
801 #define GATE_TOP5(_id, _name, _parent, _shift) { \ argument
A Dclk-mt2701-aud.c18 #define GATE_AUDIO0(_id, _name, _parent, _shift) { \ argument
27 #define GATE_AUDIO1(_id, _name, _parent, _shift) { \ argument
36 #define GATE_AUDIO2(_id, _name, _parent, _shift) { \ argument
45 #define GATE_AUDIO3(_id, _name, _parent, _shift) { \ argument
A Dclk-mt8195-vdo1.c37 #define GATE_VDO1_0(_id, _name, _parent, _shift) \ argument
40 #define GATE_VDO1_1(_id, _name, _parent, _shift) \ argument
43 #define GATE_VDO1_2(_id, _name, _parent, _shift) \ argument
46 #define GATE_VDO1_3(_id, _name, _parent, _shift) \ argument
A Dclk-mt7622-aud.c19 #define GATE_AUDIO0(_id, _name, _parent, _shift) { \ argument
28 #define GATE_AUDIO1(_id, _name, _parent, _shift) { \ argument
37 #define GATE_AUDIO2(_id, _name, _parent, _shift) { \ argument
46 #define GATE_AUDIO3(_id, _name, _parent, _shift) { \ argument
A Dclk-mt8192.c880 #define GATE_APMIXED(_id, _name, _parent, _shift) \ argument
923 #define GATE_INFRA0(_id, _name, _parent, _shift) \ argument
926 #define GATE_INFRA1_FLAGS(_id, _name, _parent, _shift, _flag) \ argument
930 #define GATE_INFRA1(_id, _name, _parent, _shift) \ argument
933 #define GATE_INFRA2(_id, _name, _parent, _shift) \ argument
936 #define GATE_INFRA3_FLAGS(_id, _name, _parent, _shift, _flag) \ argument
940 #define GATE_INFRA3(_id, _name, _parent, _shift) \ argument
943 #define GATE_INFRA4(_id, _name, _parent, _shift) \ argument
950 #define GATE_INFRA5(_id, _name, _parent, _shift) \ argument
1095 #define GATE_PERI(_id, _name, _parent, _shift) \ argument
[all …]
A Dclk-mt8195-vpp0.c31 #define GATE_VPP0_0(_id, _name, _parent, _shift) \ argument
34 #define GATE_VPP0_1(_id, _name, _parent, _shift) \ argument
37 #define GATE_VPP0_2(_id, _name, _parent, _shift) \ argument
A Dclk-mt8516.c467 #define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) { \ argument
527 #define GATE_TOP1(_id, _name, _parent, _shift) { \ argument
536 #define GATE_TOP2(_id, _name, _parent, _shift) { \ argument
545 #define GATE_TOP2_I(_id, _name, _parent, _shift) { \ argument
554 #define GATE_TOP3(_id, _name, _parent, _shift) { \ argument
563 #define GATE_TOP4_I(_id, _name, _parent, _shift) { \ argument
572 #define GATE_TOP5(_id, _name, _parent, _shift) { \ argument
A Dclk-mt8192-vdec.c33 #define GATE_VDEC0(_id, _name, _parent, _shift) \ argument
36 #define GATE_VDEC1(_id, _name, _parent, _shift) \ argument
39 #define GATE_VDEC2(_id, _name, _parent, _shift) \ argument
A Dclk-mt2712-mm.c33 #define GATE_MM0(_id, _name, _parent, _shift) { \ argument
42 #define GATE_MM1(_id, _name, _parent, _shift) { \ argument
51 #define GATE_MM2(_id, _name, _parent, _shift) { \ argument
A Dclk-mt8192-mm.c32 #define GATE_MM0(_id, _name, _parent, _shift) \ argument
35 #define GATE_MM1(_id, _name, _parent, _shift) \ argument
38 #define GATE_MM2(_id, _name, _parent, _shift) \ argument
A Dclk-mt8195-wpe.c31 #define GATE_WPE(_id, _name, _parent, _shift) \ argument
34 #define GATE_WPE_VPP0(_id, _name, _parent, _shift) \ argument
37 #define GATE_WPE_VPP1(_id, _name, _parent, _shift) \ argument
A Dclk-mt8192-aud.c33 #define GATE_AUD0(_id, _name, _parent, _shift) \ argument
36 #define GATE_AUD1(_id, _name, _parent, _shift) \ argument
39 #define GATE_AUD2(_id, _name, _parent, _shift) \ argument
A Dclk-mt8195-vdec.c31 #define GATE_VDEC0(_id, _name, _parent, _shift) \ argument
34 #define GATE_VDEC1(_id, _name, _parent, _shift) \ argument
37 #define GATE_VDEC2(_id, _name, _parent, _shift) \ argument
A Dclk-mt8195-vdo0.c31 #define GATE_VDO0_0(_id, _name, _parent, _shift) \ argument
34 #define GATE_VDO0_1(_id, _name, _parent, _shift) \ argument
37 #define GATE_VDO0_2(_id, _name, _parent, _shift) \ argument
A Dclk-mt8173.c622 #define GATE_ICG(_id, _name, _parent, _shift) { \ argument
661 #define GATE_PERI0(_id, _name, _parent, _shift) { \ argument
670 #define GATE_PERI1(_id, _name, _parent, _shift) { \ argument
737 #define GATE_IMG(_id, _name, _parent, _shift) { \ argument
768 #define GATE_VDEC0(_id, _name, _parent, _shift) { \ argument
777 #define GATE_VDEC1(_id, _name, _parent, _shift) { \ argument
791 #define GATE_VENC(_id, _name, _parent, _shift) { \ argument
807 #define GATE_VENCLT(_id, _name, _parent, _shift) { \ argument
923 #define APMIXED_USB(_id, _name, _parent, _reg_ofs) { \ argument
A Dclk-mt8183.c756 #define GATE_TOP(_id, _name, _parent, _shift) \ argument
790 #define GATE_INFRA0(_id, _name, _parent, _shift) \ argument
794 #define GATE_INFRA1(_id, _name, _parent, _shift) \ argument
798 #define GATE_INFRA2(_id, _name, _parent, _shift) \ argument
802 #define GATE_INFRA3(_id, _name, _parent, _shift) \ argument
1013 #define GATE_PERI(_id, _name, _parent, _shift) \ argument
1027 #define GATE_APMIXED_FLAGS(_id, _name, _parent, _shift, _flags) \ argument
1031 #define GATE_APMIXED(_id, _name, _parent, _shift) \ argument
/linux/drivers/clk/sprd/
A Dgate.h31 #define SPRD_SC_GATE_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, \ argument
47 #define SPRD_SC_GATE_CLK_OPS_UDELAY(_struct, _name, _parent, _reg, \ argument
60 #define SPRD_SC_GATE_CLK(_struct, _name, _parent, _reg, _sc_offset, \ argument
66 #define SPRD_GATE_CLK(_struct, _name, _parent, _reg, \ argument
90 #define SPRD_SC_GATE_CLK_HW_OPS(_struct, _name, _parent, _reg, \ argument
97 #define SPRD_SC_GATE_CLK_HW(_struct, _name, _parent, _reg, \ argument
104 #define SPRD_GATE_CLK_HW(_struct, _name, _parent, _reg, \ argument
110 #define SPRD_PLL_SC_GATE_CLK_HW(_struct, _name, _parent, _reg, \ argument
127 #define SPRD_SC_GATE_CLK_FW_NAME_OPS(_struct, _name, _parent, _reg, \ argument
135 #define SPRD_SC_GATE_CLK_FW_NAME(_struct, _name, _parent, _reg, \ argument
[all …]
A Dcomposite.h21 #define SPRD_COMP_CLK_HW_INIT_FN(_struct, _name, _parent, _reg, _table, \ argument
35 #define SPRD_COMP_CLK_TABLE(_struct, _name, _parent, _reg, _table, \ argument
41 #define SPRD_COMP_CLK(_struct, _name, _parent, _reg, _mshift, \ argument
46 #define SPRD_COMP_CLK_DATA_TABLE(_struct, _name, _parent, _reg, _table, \ argument
53 #define SPRD_COMP_CLK_DATA(_struct, _name, _parent, _reg, _mshift, \ argument
A Dpll.h64 #define SPRD_PLL_HW_INIT_FN(_struct, _name, _parent, _reg, \ argument
85 #define SPRD_PLL_WITH_ITABLE_K_FVCO(_struct, _name, _parent, _reg, \ argument
92 #define SPRD_PLL_WITH_ITABLE_K(_struct, _name, _parent, _reg, \ argument
99 #define SPRD_PLL_WITH_ITABLE_1K(_struct, _name, _parent, _reg, \ argument
105 #define SPRD_PLL_FW_NAME(_struct, _name, _parent, _reg, _regs_num, \ argument
112 #define SPRD_PLL_HW(_struct, _name, _parent, _reg, _regs_num, _itable, \ argument
/linux/sound/soc/mediatek/mt8195/
A Dmt8195-audsys-clk.c28 #define GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, _flags, _cgflags) {\ argument
38 #define GATE_AFE(_id, _name, _parent, _reg, _bit) \ argument
42 #define GATE_AUD0(_id, _name, _parent, _bit) \ argument
45 #define GATE_AUD1(_id, _name, _parent, _bit) \ argument
48 #define GATE_AUD3(_id, _name, _parent, _bit) \ argument
51 #define GATE_AUD4(_id, _name, _parent, _bit) \ argument
54 #define GATE_AUD5(_id, _name, _parent, _bit) \ argument
57 #define GATE_AUD6(_id, _name, _parent, _bit) \ argument
/linux/drivers/clk/actions/
A Dowl-composite.h37 #define OWL_COMP_DIV(_struct, _name, _parent, \ argument
52 #define OWL_COMP_DIV_FIXED(_struct, _name, _parent, \ argument
66 #define OWL_COMP_FACTOR(_struct, _name, _parent, \ argument
81 #define OWL_COMP_FIXED_FACTOR(_struct, _name, _parent, \ argument
97 #define OWL_COMP_PASS(_struct, _name, _parent, \ argument
/linux/drivers/clk/sunxi-ng/
A Dccu_gate.h19 #define SUNXI_CCU_GATE(_struct, _name, _parent, _reg, _gate, _flags) \ argument
31 #define SUNXI_CCU_GATE_HW(_struct, _name, _parent, _reg, _gate, _flags) \ argument
43 #define SUNXI_CCU_GATE_FW(_struct, _name, _parent, _reg, _gate, _flags) \ argument
59 #define SUNXI_CCU_GATE_HWS(_struct, _name, _parent, _reg, _gate, _flags) \ argument
/linux/drivers/clk/renesas/
A Drenesas-cpg-mssr.h46 #define DEF_BASE(_name, _id, _type, _parent...) \ argument
51 #define DEF_FIXED(_name, _id, _parent, _div, _mult) \ argument
53 #define DEF_DIV6P1(_name, _id, _parent, _offset) \ argument
55 #define DEF_DIV6_RO(_name, _id, _parent, _offset, _div) \ argument
75 #define DEF_MOD(_name, _mod, _parent...) \ argument
83 #define DEF_MOD_STB(_name, _mod, _parent...) \ argument

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