Searched defs:_width (Results 1 – 25 of 40) sorted by relevance

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/linux/drivers/clk/sunxi-ng/
A D	ccu_div.h	43 #define _SUNXI_CCU_DIV_TABLE_FLAGS(_shift, _width, _table, _flags) \ argument 51 #define _SUNXI_CCU_DIV_TABLE(_shift, _width, _table) \ argument 54 #define _SUNXI_CCU_DIV_OFFSET_MAX_FLAGS(_shift, _width, _off, _max, _flags) \ argument 63 #define _SUNXI_CCU_DIV_MAX_FLAGS(_shift, _width, _max, _flags) \ argument 66 #define _SUNXI_CCU_DIV_FLAGS(_shift, _width, _flags) \ argument 69 #define _SUNXI_CCU_DIV_MAX(_shift, _width, _max) \ argument 72 #define _SUNXI_CCU_DIV_OFFSET(_shift, _width, _offset) \ argument 75 #define _SUNXI_CCU_DIV(_shift, _width) \ argument 88 _shift, _width, \ argument 105 _shift, _width, \ argument
A D	ccu_mult.h	17 #define _SUNXI_CCU_MULT_OFFSET_MIN_MAX(_shift, _width, _offset, _min, _max) \ argument 26 #define _SUNXI_CCU_MULT_MIN(_shift, _width, _min) \ argument 29 #define _SUNXI_CCU_MULT_OFFSET(_shift, _width, _offset) \ argument 32 #define _SUNXI_CCU_MULT(_shift, _width) \ argument
A D	ccu_mux.h	32 #define _SUNXI_CCU_MUX_TABLE(_shift, _width, _table) \ argument 39 #define _SUNXI_CCU_MUX(_shift, _width) \ argument 50 _reg, _shift, _width, _gate, \ argument 65 _shift, _width, _gate, _flags) \ argument 70 #define SUNXI_CCU_MUX(_struct, _name, _parents, _reg, _shift, _width, \ argument
A D	ccu_phase.h	20 #define SUNXI_CCU_PHASE(_struct, _name, _parent, _reg, _shift, _width, _flags) \ argument
/linux/drivers/clk/sprd/
A D	mux.h	32 #define _SPRD_MUX_CLK(_shift, _width, _table) \ argument 40 _reg, _shift, _width, _flags, _fn) \ argument 52 _reg, _shift, _width, _flags) \ argument 58 _shift, _width, _flags) \ argument 63 _reg, _shift, _width, _flags) \ argument 69 _shift, _width, _flags) \ argument
A D	div.h	27 #define _SPRD_DIV_CLK(_shift, _width) \ argument 39 _shift, _width, _flags, _fn) \ argument 51 _shift, _width, _flags) \ argument 56 _shift, _width, _flags) \ argument
/linux/drivers/clk/actions/
A D	owl-pll.h	42 _width, _min_mul, _max_mul, _delay, _table) \ argument 56 _shift, _width, _min_mul, _max_mul, _table, _flags) \ argument 71 _shift, _width, _min_mul, _max_mul, _table, _flags) \ argument 85 _shift, _width, _min_mul, _max_mul, _delay, _table, \ argument
A D	owl-mux.h	27 #define OWL_MUX_HW(_reg, _shift, _width) \ argument 35 _shift, _width, _flags) \ argument
A D	owl-divider.h	29 #define OWL_DIVIDER_HW(_reg, _shift, _width, _div_flags, _table) \ argument 39 _shift, _width, _table, _div_flags, _flags) \ argument
A D	owl-factor.h	35 #define OWL_FACTOR_HW(_reg, _shift, _width, _fct_flags, _table) \ argument 45 _shift, _width, _table, _fct_flags, _flags) \ argument
/linux/drivers/clk/mediatek/
A D	clk-mux.h	41 _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ argument 63 _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ argument 71 _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ argument 79 _mux_set_ofs, _mux_clr_ofs, _shift, _width, \ argument
A D	clk-mtk.h	83 _width, _gate, _flags, _muxflags) { \ argument 102 #define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \ argument 111 #define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) \ argument 115 #define MUX(_id, _name, _parents, _reg, _shift, _width) \ argument 119 #define MUX_FLAGS(_id, _name, _parents, _reg, _shift, _width, _flags) { \ argument 191 #define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) { \ argument
A D	clk-mt8167.c	657 #define DIV_ADJ(_id, _name, _parent, _reg, _shift, _width) { \ argument 687 #define DIV_ADJ_FLAG(_id, _name, _parent, _reg, _shift, _width, _flag) { \ argument
/linux/drivers/clk/x86/
A D	clk-cgu.h	207 _shift, _width, _cf, _v) \ argument 222 #define LGM_DIV(_id, _name, _pname, _f, _reg, _shift, _width, \ argument 263 _shift, _width, _cf, _freq, _v) \ argument 283 _shift, _width, _cf, _v, _m, _d) \ argument
/linux/include/uapi/linux/
A D	v4l2-dv-timings.h	25 #define V4L2_INIT_BT_TIMINGS(_width, args...) \ argument 28 #define V4L2_INIT_BT_TIMINGS(_width, args...) \ argument
/linux/drivers/pinctrl/berlin/
A D	berlin.h	37 #define BERLIN_PINCTRL_GROUP(_name, _offset, _width, _lsb, ...) \ argument
/linux/drivers/clk/pistachio/
A D	clk.h	59 #define DIV(_id, _name, _pname, _reg, _width) \ argument 69 #define DIV_F(_id, _name, _pname, _reg, _width, _div_flags) \ argument
/linux/drivers/clk/bcm/
A D	clk-kona.h	299 #define DIVIDER(_offset, _shift, _width) \ argument 309 #define FRAC_DIVIDER(_offset, _shift, _width, _frac_width) \ argument 350 #define SELECTOR(_offset, _shift, _width) \ argument
/linux/drivers/clk/meson/
A D	axg-audio.c	53 #define AUD_DIV(_name, _reg, _shift, _width, _dflags, _pname, _iflags) { \ argument 105 #define AUD_TRIPHASE(_name, _reg, _width, _shift0, _shift1, _shift2, \ argument 133 #define AUD_PHASE(_name, _reg, _width, _shift, _pname, _iflags) { \ argument 150 #define AUD_SCLK_WS(_name, _reg, _width, _shift_ph, _shift_ws, _pname, \ argument
A D	clk-phase.c	13 #define phase_step(_width) (360 / (1 << (_width))) argument
/linux/drivers/net/ethernet/microchip/sparx5/
A D	sparx5_netdev.c	16 #define ifh_encode_bitfield(ifh, value, pos, _width) \ argument
/linux/drivers/clk/
A D	clk-stm32mp1.c	1182 #define DIV_TABLE(_id, _name, _parent, _flags, _offset, _shift, _width,\ argument 1199 #define DIV(_id, _name, _parent, _flags, _offset, _shift, _width, _div_flags)\ argument 1203 #define MUX(_id, _name, _parents, _flags, _offset, _shift, _width, _mux_flags)\ argument 1315 #define _STM32_MUX(_offset, _shift, _width, _mux_flags, _mmux, _ops)\ argument 1328 #define _MUX(_offset, _shift, _width, _mux_flags)\ argument 1666 #define _K_MUX(_id, _offset, _shift, _width, _mux_flags, _mmux, _ops)\ argument 1679 #define K_MUX(_id, _offset, _shift, _width, _mux_flags)\ argument 1683 #define K_MMUX(_id, _offset, _shift, _width, _mux_flags)\ argument
/linux/drivers/dma/fsl-dpaa2-qdma/
A D	dpdmai.h	45 #define MAKE_UMASK64(_width) \ argument
/linux/drivers/soc/sunxi/
A D	sunxi_sram.c	51 #define SUNXI_SRAM_DATA(_name, _reg, _off, _width, ...) \ argument
/linux/drivers/gpu/drm/gma500/
A D	framebuffer.c	38 #define CMAP_TOHW(_val, _width) ((((_val) << (_width)) + 0x7FFF - (_val)) >> 16) argument

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Last Index update Sat Jun 03 09:59:21 CST 2023