1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. */
3
4 #include <linux/clk.h>
5 #include <linux/interconnect.h>
6 #include <linux/pm_domain.h>
7 #include <linux/pm_opp.h>
8 #include <soc/qcom/cmd-db.h>
9 #include <drm/drm_gem.h>
10
11 #include "a6xx_gpu.h"
12 #include "a6xx_gmu.xml.h"
13 #include "msm_gem.h"
14 #include "msm_gpu_trace.h"
15 #include "msm_mmu.h"
16
a6xx_gmu_fault(struct a6xx_gmu * gmu)17 static void a6xx_gmu_fault(struct a6xx_gmu *gmu)
18 {
19 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
20 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
21 struct msm_gpu *gpu = &adreno_gpu->base;
22
23 /* FIXME: add a banner here */
24 gmu->hung = true;
25
26 /* Turn off the hangcheck timer while we are resetting */
27 del_timer(&gpu->hangcheck_timer);
28
29 /* Queue the GPU handler because we need to treat this as a recovery */
30 kthread_queue_work(gpu->worker, &gpu->recover_work);
31 }
32
a6xx_gmu_irq(int irq,void * data)33 static irqreturn_t a6xx_gmu_irq(int irq, void *data)
34 {
35 struct a6xx_gmu *gmu = data;
36 u32 status;
37
38 status = gmu_read(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_STATUS);
39 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, status);
40
41 if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_WDOG_BITE) {
42 dev_err_ratelimited(gmu->dev, "GMU watchdog expired\n");
43
44 a6xx_gmu_fault(gmu);
45 }
46
47 if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_HOST_AHB_BUS_ERROR)
48 dev_err_ratelimited(gmu->dev, "GMU AHB bus error\n");
49
50 if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_FENCE_ERR)
51 dev_err_ratelimited(gmu->dev, "GMU fence error: 0x%x\n",
52 gmu_read(gmu, REG_A6XX_GMU_AHB_FENCE_STATUS));
53
54 return IRQ_HANDLED;
55 }
56
a6xx_hfi_irq(int irq,void * data)57 static irqreturn_t a6xx_hfi_irq(int irq, void *data)
58 {
59 struct a6xx_gmu *gmu = data;
60 u32 status;
61
62 status = gmu_read(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO);
63 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, status);
64
65 if (status & A6XX_GMU_GMU2HOST_INTR_INFO_CM3_FAULT) {
66 dev_err_ratelimited(gmu->dev, "GMU firmware fault\n");
67
68 a6xx_gmu_fault(gmu);
69 }
70
71 return IRQ_HANDLED;
72 }
73
a6xx_gmu_sptprac_is_on(struct a6xx_gmu * gmu)74 bool a6xx_gmu_sptprac_is_on(struct a6xx_gmu *gmu)
75 {
76 u32 val;
77
78 /* This can be called from gpu state code so make sure GMU is valid */
79 if (!gmu->initialized)
80 return false;
81
82 val = gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS);
83
84 return !(val &
85 (A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWER_OFF |
86 A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SP_CLOCK_OFF));
87 }
88
89 /* Check to see if the GX rail is still powered */
a6xx_gmu_gx_is_on(struct a6xx_gmu * gmu)90 bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu)
91 {
92 u32 val;
93
94 /* This can be called from gpu state code so make sure GMU is valid */
95 if (!gmu->initialized)
96 return false;
97
98 val = gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS);
99
100 return !(val &
101 (A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_GDSC_POWER_OFF |
102 A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_CLK_OFF));
103 }
104
a6xx_gmu_set_freq(struct msm_gpu * gpu,struct dev_pm_opp * opp)105 void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp)
106 {
107 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
108 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
109 struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
110 u32 perf_index;
111 unsigned long gpu_freq;
112 int ret = 0;
113
114 gpu_freq = dev_pm_opp_get_freq(opp);
115
116 if (gpu_freq == gmu->freq)
117 return;
118
119 for (perf_index = 0; perf_index < gmu->nr_gpu_freqs - 1; perf_index++)
120 if (gpu_freq == gmu->gpu_freqs[perf_index])
121 break;
122
123 gmu->current_perf_index = perf_index;
124 gmu->freq = gmu->gpu_freqs[perf_index];
125
126 trace_msm_gmu_freq_change(gmu->freq, perf_index);
127
128 /*
129 * This can get called from devfreq while the hardware is idle. Don't
130 * bring up the power if it isn't already active
131 */
132 if (pm_runtime_get_if_in_use(gmu->dev) == 0)
133 return;
134
135 if (!gmu->legacy) {
136 a6xx_hfi_set_freq(gmu, perf_index);
137 dev_pm_opp_set_opp(&gpu->pdev->dev, opp);
138 pm_runtime_put(gmu->dev);
139 return;
140 }
141
142 gmu_write(gmu, REG_A6XX_GMU_DCVS_ACK_OPTION, 0);
143
144 gmu_write(gmu, REG_A6XX_GMU_DCVS_PERF_SETTING,
145 ((3 & 0xf) << 28) | perf_index);
146
147 /*
148 * Send an invalid index as a vote for the bus bandwidth and let the
149 * firmware decide on the right vote
150 */
151 gmu_write(gmu, REG_A6XX_GMU_DCVS_BW_SETTING, 0xff);
152
153 /* Set and clear the OOB for DCVS to trigger the GMU */
154 a6xx_gmu_set_oob(gmu, GMU_OOB_DCVS_SET);
155 a6xx_gmu_clear_oob(gmu, GMU_OOB_DCVS_SET);
156
157 ret = gmu_read(gmu, REG_A6XX_GMU_DCVS_RETURN);
158 if (ret)
159 dev_err(gmu->dev, "GMU set GPU frequency error: %d\n", ret);
160
161 dev_pm_opp_set_opp(&gpu->pdev->dev, opp);
162 pm_runtime_put(gmu->dev);
163 }
164
a6xx_gmu_get_freq(struct msm_gpu * gpu)165 unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu)
166 {
167 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
168 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
169 struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
170
171 return gmu->freq;
172 }
173
a6xx_gmu_check_idle_level(struct a6xx_gmu * gmu)174 static bool a6xx_gmu_check_idle_level(struct a6xx_gmu *gmu)
175 {
176 u32 val;
177 int local = gmu->idle_level;
178
179 /* SPTP and IFPC both report as IFPC */
180 if (gmu->idle_level == GMU_IDLE_STATE_SPTP)
181 local = GMU_IDLE_STATE_IFPC;
182
183 val = gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE);
184
185 if (val == local) {
186 if (gmu->idle_level != GMU_IDLE_STATE_IFPC ||
187 !a6xx_gmu_gx_is_on(gmu))
188 return true;
189 }
190
191 return false;
192 }
193
194 /* Wait for the GMU to get to its most idle state */
a6xx_gmu_wait_for_idle(struct a6xx_gmu * gmu)195 int a6xx_gmu_wait_for_idle(struct a6xx_gmu *gmu)
196 {
197 return spin_until(a6xx_gmu_check_idle_level(gmu));
198 }
199
a6xx_gmu_start(struct a6xx_gmu * gmu)200 static int a6xx_gmu_start(struct a6xx_gmu *gmu)
201 {
202 int ret;
203 u32 val;
204 u32 mask, reset_val;
205
206 val = gmu_read(gmu, REG_A6XX_GMU_CM3_DTCM_START + 0xff8);
207 if (val <= 0x20010004) {
208 mask = 0xffffffff;
209 reset_val = 0xbabeface;
210 } else {
211 mask = 0x1ff;
212 reset_val = 0x100;
213 }
214
215 gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 1);
216
217 /* Set the log wptr index
218 * note: downstream saves the value in poweroff and restores it here
219 */
220 gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_RESP, 0);
221
222 gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 0);
223
224 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_CM3_FW_INIT_RESULT, val,
225 (val & mask) == reset_val, 100, 10000);
226
227 if (ret)
228 DRM_DEV_ERROR(gmu->dev, "GMU firmware initialization timed out\n");
229
230 return ret;
231 }
232
a6xx_gmu_hfi_start(struct a6xx_gmu * gmu)233 static int a6xx_gmu_hfi_start(struct a6xx_gmu *gmu)
234 {
235 u32 val;
236 int ret;
237
238 gmu_write(gmu, REG_A6XX_GMU_HFI_CTRL_INIT, 1);
239
240 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_HFI_CTRL_STATUS, val,
241 val & 1, 100, 10000);
242 if (ret)
243 DRM_DEV_ERROR(gmu->dev, "Unable to start the HFI queues\n");
244
245 return ret;
246 }
247
248 struct a6xx_gmu_oob_bits {
249 int set, ack, set_new, ack_new, clear, clear_new;
250 const char *name;
251 };
252
253 /* These are the interrupt / ack bits for each OOB request that are set
254 * in a6xx_gmu_set_oob and a6xx_clear_oob
255 */
256 static const struct a6xx_gmu_oob_bits a6xx_gmu_oob_bits[] = {
257 [GMU_OOB_GPU_SET] = {
258 .name = "GPU_SET",
259 .set = 16,
260 .ack = 24,
261 .set_new = 30,
262 .ack_new = 31,
263 .clear = 24,
264 .clear_new = 31,
265 },
266
267 [GMU_OOB_PERFCOUNTER_SET] = {
268 .name = "PERFCOUNTER",
269 .set = 17,
270 .ack = 25,
271 .set_new = 28,
272 .ack_new = 30,
273 .clear = 25,
274 .clear_new = 29,
275 },
276
277 [GMU_OOB_BOOT_SLUMBER] = {
278 .name = "BOOT_SLUMBER",
279 .set = 22,
280 .ack = 30,
281 .clear = 30,
282 },
283
284 [GMU_OOB_DCVS_SET] = {
285 .name = "GPU_DCVS",
286 .set = 23,
287 .ack = 31,
288 .clear = 31,
289 },
290 };
291
292 /* Trigger a OOB (out of band) request to the GMU */
a6xx_gmu_set_oob(struct a6xx_gmu * gmu,enum a6xx_gmu_oob_state state)293 int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state)
294 {
295 int ret;
296 u32 val;
297 int request, ack;
298
299 WARN_ON_ONCE(!mutex_is_locked(&gmu->lock));
300
301 if (state >= ARRAY_SIZE(a6xx_gmu_oob_bits))
302 return -EINVAL;
303
304 if (gmu->legacy) {
305 request = a6xx_gmu_oob_bits[state].set;
306 ack = a6xx_gmu_oob_bits[state].ack;
307 } else {
308 request = a6xx_gmu_oob_bits[state].set_new;
309 ack = a6xx_gmu_oob_bits[state].ack_new;
310 if (!request || !ack) {
311 DRM_DEV_ERROR(gmu->dev,
312 "Invalid non-legacy GMU request %s\n",
313 a6xx_gmu_oob_bits[state].name);
314 return -EINVAL;
315 }
316 }
317
318 /* Trigger the equested OOB operation */
319 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 1 << request);
320
321 /* Wait for the acknowledge interrupt */
322 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO, val,
323 val & (1 << ack), 100, 10000);
324
325 if (ret)
326 DRM_DEV_ERROR(gmu->dev,
327 "Timeout waiting for GMU OOB set %s: 0x%x\n",
328 a6xx_gmu_oob_bits[state].name,
329 gmu_read(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO));
330
331 /* Clear the acknowledge interrupt */
332 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, 1 << ack);
333
334 return ret;
335 }
336
337 /* Clear a pending OOB state in the GMU */
a6xx_gmu_clear_oob(struct a6xx_gmu * gmu,enum a6xx_gmu_oob_state state)338 void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state)
339 {
340 int bit;
341
342 WARN_ON_ONCE(!mutex_is_locked(&gmu->lock));
343
344 if (state >= ARRAY_SIZE(a6xx_gmu_oob_bits))
345 return;
346
347 if (gmu->legacy)
348 bit = a6xx_gmu_oob_bits[state].clear;
349 else
350 bit = a6xx_gmu_oob_bits[state].clear_new;
351
352 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 1 << bit);
353 }
354
355 /* Enable CPU control of SPTP power power collapse */
a6xx_sptprac_enable(struct a6xx_gmu * gmu)356 static int a6xx_sptprac_enable(struct a6xx_gmu *gmu)
357 {
358 int ret;
359 u32 val;
360
361 if (!gmu->legacy)
362 return 0;
363
364 gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778000);
365
366 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS, val,
367 (val & 0x38) == 0x28, 1, 100);
368
369 if (ret) {
370 DRM_DEV_ERROR(gmu->dev, "Unable to power on SPTPRAC: 0x%x\n",
371 gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS));
372 }
373
374 return 0;
375 }
376
377 /* Disable CPU control of SPTP power power collapse */
a6xx_sptprac_disable(struct a6xx_gmu * gmu)378 static void a6xx_sptprac_disable(struct a6xx_gmu *gmu)
379 {
380 u32 val;
381 int ret;
382
383 if (!gmu->legacy)
384 return;
385
386 /* Make sure retention is on */
387 gmu_rmw(gmu, REG_A6XX_GPU_CC_GX_GDSCR, 0, (1 << 11));
388
389 gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778001);
390
391 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS, val,
392 (val & 0x04), 100, 10000);
393
394 if (ret)
395 DRM_DEV_ERROR(gmu->dev, "failed to power off SPTPRAC: 0x%x\n",
396 gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS));
397 }
398
399 /* Let the GMU know we are starting a boot sequence */
a6xx_gmu_gfx_rail_on(struct a6xx_gmu * gmu)400 static int a6xx_gmu_gfx_rail_on(struct a6xx_gmu *gmu)
401 {
402 u32 vote;
403
404 /* Let the GMU know we are getting ready for boot */
405 gmu_write(gmu, REG_A6XX_GMU_BOOT_SLUMBER_OPTION, 0);
406
407 /* Choose the "default" power level as the highest available */
408 vote = gmu->gx_arc_votes[gmu->nr_gpu_freqs - 1];
409
410 gmu_write(gmu, REG_A6XX_GMU_GX_VOTE_IDX, vote & 0xff);
411 gmu_write(gmu, REG_A6XX_GMU_MX_VOTE_IDX, (vote >> 8) & 0xff);
412
413 /* Let the GMU know the boot sequence has started */
414 return a6xx_gmu_set_oob(gmu, GMU_OOB_BOOT_SLUMBER);
415 }
416
417 /* Let the GMU know that we are about to go into slumber */
a6xx_gmu_notify_slumber(struct a6xx_gmu * gmu)418 static int a6xx_gmu_notify_slumber(struct a6xx_gmu *gmu)
419 {
420 int ret;
421
422 /* Disable the power counter so the GMU isn't busy */
423 gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 0);
424
425 /* Disable SPTP_PC if the CPU is responsible for it */
426 if (gmu->idle_level < GMU_IDLE_STATE_SPTP)
427 a6xx_sptprac_disable(gmu);
428
429 if (!gmu->legacy) {
430 ret = a6xx_hfi_send_prep_slumber(gmu);
431 goto out;
432 }
433
434 /* Tell the GMU to get ready to slumber */
435 gmu_write(gmu, REG_A6XX_GMU_BOOT_SLUMBER_OPTION, 1);
436
437 ret = a6xx_gmu_set_oob(gmu, GMU_OOB_BOOT_SLUMBER);
438 a6xx_gmu_clear_oob(gmu, GMU_OOB_BOOT_SLUMBER);
439
440 if (!ret) {
441 /* Check to see if the GMU really did slumber */
442 if (gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE)
443 != 0x0f) {
444 DRM_DEV_ERROR(gmu->dev, "The GMU did not go into slumber\n");
445 ret = -ETIMEDOUT;
446 }
447 }
448
449 out:
450 /* Put fence into allow mode */
451 gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0);
452 return ret;
453 }
454
a6xx_rpmh_start(struct a6xx_gmu * gmu)455 static int a6xx_rpmh_start(struct a6xx_gmu *gmu)
456 {
457 int ret;
458 u32 val;
459
460 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1 << 1);
461 /* Wait for the register to finish posting */
462 wmb();
463
464 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_RSCC_CONTROL_ACK, val,
465 val & (1 << 1), 100, 10000);
466 if (ret) {
467 DRM_DEV_ERROR(gmu->dev, "Unable to power on the GPU RSC\n");
468 return ret;
469 }
470
471 ret = gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_SEQ_BUSY_DRV0, val,
472 !val, 100, 10000);
473
474 if (ret) {
475 DRM_DEV_ERROR(gmu->dev, "GPU RSC sequence stuck while waking up the GPU\n");
476 return ret;
477 }
478
479 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0);
480
481 /* Set up CX GMU counter 0 to count busy ticks */
482 gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK, 0xff000000);
483 gmu_rmw(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0, 0xff, 0x20);
484
485 /* Enable the power counter */
486 gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 1);
487 return 0;
488 }
489
a6xx_rpmh_stop(struct a6xx_gmu * gmu)490 static void a6xx_rpmh_stop(struct a6xx_gmu *gmu)
491 {
492 int ret;
493 u32 val;
494
495 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1);
496
497 ret = gmu_poll_timeout_rscc(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0,
498 val, val & (1 << 16), 100, 10000);
499 if (ret)
500 DRM_DEV_ERROR(gmu->dev, "Unable to power off the GPU RSC\n");
501
502 gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0);
503 }
504
pdc_write(void __iomem * ptr,u32 offset,u32 value)505 static inline void pdc_write(void __iomem *ptr, u32 offset, u32 value)
506 {
507 return msm_writel(value, ptr + (offset << 2));
508 }
509
510 static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev,
511 const char *name);
512
a6xx_gmu_rpmh_init(struct a6xx_gmu * gmu)513 static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu)
514 {
515 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
516 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
517 struct platform_device *pdev = to_platform_device(gmu->dev);
518 void __iomem *pdcptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc");
519 void __iomem *seqptr = NULL;
520 uint32_t pdc_address_offset;
521 bool pdc_in_aop = false;
522
523 if (IS_ERR(pdcptr))
524 goto err;
525
526 if (adreno_is_a650(adreno_gpu) || adreno_is_a660_family(adreno_gpu))
527 pdc_in_aop = true;
528 else if (adreno_is_a618(adreno_gpu) || adreno_is_a640_family(adreno_gpu))
529 pdc_address_offset = 0x30090;
530 else
531 pdc_address_offset = 0x30080;
532
533 if (!pdc_in_aop) {
534 seqptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc_seq");
535 if (IS_ERR(seqptr))
536 goto err;
537 }
538
539 /* Disable SDE clock gating */
540 gmu_write_rscc(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0, BIT(24));
541
542 /* Setup RSC PDC handshake for sleep and wakeup */
543 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_SLAVE_ID_DRV0, 1);
544 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA, 0);
545 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR, 0);
546 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 2, 0);
547 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 2, 0);
548 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 4, 0x80000000);
549 gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 4, 0);
550 gmu_write_rscc(gmu, REG_A6XX_RSCC_OVERRIDE_START_ADDR, 0);
551 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_SEQ_START_ADDR, 0x4520);
552 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_LO, 0x4510);
553 gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_HI, 0x4514);
554
555 /* Load RSC sequencer uCode for sleep and wakeup */
556 if (adreno_is_a650_family(adreno_gpu)) {
557 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xeaaae5a0);
558 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xe1a1ebab);
559 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e0a581);
560 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xecac82e2);
561 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020edad);
562 } else {
563 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xa7a506a0);
564 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xa1e6a6e7);
565 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e081e1);
566 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xe9a982e2);
567 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020e8a8);
568 }
569
570 if (pdc_in_aop)
571 goto setup_pdc;
572
573 /* Load PDC sequencer uCode for power up and power down sequence */
574 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0, 0xfebea1e1);
575 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 1, 0xa5a4a3a2);
576 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 2, 0x8382a6e0);
577 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 3, 0xbce3e284);
578 pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 4, 0x002081fc);
579
580 /* Set TCS commands used by PDC sequence for low power modes */
581 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK, 7);
582 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK, 0);
583 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CONTROL, 0);
584 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID, 0x10108);
585 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR, 0x30010);
586 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA, 1);
587 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 4, 0x10108);
588 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 4, 0x30000);
589 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 4, 0x0);
590
591 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 8, 0x10108);
592 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 8, pdc_address_offset);
593 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 8, 0x0);
594
595 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK, 7);
596 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK, 0);
597 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CONTROL, 0);
598 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID, 0x10108);
599 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR, 0x30010);
600 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA, 2);
601
602 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 4, 0x10108);
603 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 4, 0x30000);
604 if (adreno_is_a618(adreno_gpu) || adreno_is_a650_family(adreno_gpu))
605 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x2);
606 else
607 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x3);
608 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 8, 0x10108);
609 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 8, pdc_address_offset);
610 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 8, 0x3);
611
612 /* Setup GPU PDC */
613 setup_pdc:
614 pdc_write(pdcptr, REG_A6XX_PDC_GPU_SEQ_START_ADDR, 0);
615 pdc_write(pdcptr, REG_A6XX_PDC_GPU_ENABLE_PDC, 0x80000001);
616
617 /* ensure no writes happen before the uCode is fully written */
618 wmb();
619
620 err:
621 if (!IS_ERR_OR_NULL(pdcptr))
622 iounmap(pdcptr);
623 if (!IS_ERR_OR_NULL(seqptr))
624 iounmap(seqptr);
625 }
626
627 /*
628 * The lowest 16 bits of this value are the number of XO clock cycles for main
629 * hysteresis which is set at 0x1680 cycles (300 us). The higher 16 bits are
630 * for the shorter hysteresis that happens after main - this is 0xa (.5 us)
631 */
632
633 #define GMU_PWR_COL_HYST 0x000a1680
634
635 /* Set up the idle state for the GMU */
a6xx_gmu_power_config(struct a6xx_gmu * gmu)636 static void a6xx_gmu_power_config(struct a6xx_gmu *gmu)
637 {
638 /* Disable GMU WB/RB buffer */
639 gmu_write(gmu, REG_A6XX_GMU_SYS_BUS_CONFIG, 0x1);
640 gmu_write(gmu, REG_A6XX_GMU_ICACHE_CONFIG, 0x1);
641 gmu_write(gmu, REG_A6XX_GMU_DCACHE_CONFIG, 0x1);
642
643 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0x9c40400);
644
645 switch (gmu->idle_level) {
646 case GMU_IDLE_STATE_IFPC:
647 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_HYST,
648 GMU_PWR_COL_HYST);
649 gmu_rmw(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0,
650 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_IFPC_ENABLE |
651 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_HM_POWER_COLLAPSE_ENABLE);
652 fallthrough;
653 case GMU_IDLE_STATE_SPTP:
654 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_SPTPRAC_HYST,
655 GMU_PWR_COL_HYST);
656 gmu_rmw(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0,
657 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_IFPC_ENABLE |
658 A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_SPTPRAC_POWER_CONTROL_ENABLE);
659 }
660
661 /* Enable RPMh GPU client */
662 gmu_rmw(gmu, REG_A6XX_GMU_RPMH_CTRL, 0,
663 A6XX_GMU_RPMH_CTRL_RPMH_INTERFACE_ENABLE |
664 A6XX_GMU_RPMH_CTRL_LLC_VOTE_ENABLE |
665 A6XX_GMU_RPMH_CTRL_DDR_VOTE_ENABLE |
666 A6XX_GMU_RPMH_CTRL_MX_VOTE_ENABLE |
667 A6XX_GMU_RPMH_CTRL_CX_VOTE_ENABLE |
668 A6XX_GMU_RPMH_CTRL_GFX_VOTE_ENABLE);
669 }
670
671 struct block_header {
672 u32 addr;
673 u32 size;
674 u32 type;
675 u32 value;
676 u32 data[];
677 };
678
679 /* this should be a general kernel helper */
in_range(u32 addr,u32 start,u32 size)680 static int in_range(u32 addr, u32 start, u32 size)
681 {
682 return addr >= start && addr < start + size;
683 }
684
fw_block_mem(struct a6xx_gmu_bo * bo,const struct block_header * blk)685 static bool fw_block_mem(struct a6xx_gmu_bo *bo, const struct block_header *blk)
686 {
687 if (!in_range(blk->addr, bo->iova, bo->size))
688 return false;
689
690 memcpy(bo->virt + blk->addr - bo->iova, blk->data, blk->size);
691 return true;
692 }
693
a6xx_gmu_fw_load(struct a6xx_gmu * gmu)694 static int a6xx_gmu_fw_load(struct a6xx_gmu *gmu)
695 {
696 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
697 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
698 const struct firmware *fw_image = adreno_gpu->fw[ADRENO_FW_GMU];
699 const struct block_header *blk;
700 u32 reg_offset;
701
702 u32 itcm_base = 0x00000000;
703 u32 dtcm_base = 0x00040000;
704
705 if (adreno_is_a650_family(adreno_gpu))
706 dtcm_base = 0x10004000;
707
708 if (gmu->legacy) {
709 /* Sanity check the size of the firmware that was loaded */
710 if (fw_image->size > 0x8000) {
711 DRM_DEV_ERROR(gmu->dev,
712 "GMU firmware is bigger than the available region\n");
713 return -EINVAL;
714 }
715
716 gmu_write_bulk(gmu, REG_A6XX_GMU_CM3_ITCM_START,
717 (u32*) fw_image->data, fw_image->size);
718 return 0;
719 }
720
721
722 for (blk = (const struct block_header *) fw_image->data;
723 (const u8*) blk < fw_image->data + fw_image->size;
724 blk = (const struct block_header *) &blk->data[blk->size >> 2]) {
725 if (blk->size == 0)
726 continue;
727
728 if (in_range(blk->addr, itcm_base, SZ_16K)) {
729 reg_offset = (blk->addr - itcm_base) >> 2;
730 gmu_write_bulk(gmu,
731 REG_A6XX_GMU_CM3_ITCM_START + reg_offset,
732 blk->data, blk->size);
733 } else if (in_range(blk->addr, dtcm_base, SZ_16K)) {
734 reg_offset = (blk->addr - dtcm_base) >> 2;
735 gmu_write_bulk(gmu,
736 REG_A6XX_GMU_CM3_DTCM_START + reg_offset,
737 blk->data, blk->size);
738 } else if (!fw_block_mem(&gmu->icache, blk) &&
739 !fw_block_mem(&gmu->dcache, blk) &&
740 !fw_block_mem(&gmu->dummy, blk)) {
741 DRM_DEV_ERROR(gmu->dev,
742 "failed to match fw block (addr=%.8x size=%d data[0]=%.8x)\n",
743 blk->addr, blk->size, blk->data[0]);
744 }
745 }
746
747 return 0;
748 }
749
a6xx_gmu_fw_start(struct a6xx_gmu * gmu,unsigned int state)750 static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state)
751 {
752 static bool rpmh_init;
753 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
754 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
755 int ret;
756 u32 chipid;
757
758 if (adreno_is_a650_family(adreno_gpu)) {
759 gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FALNEXT_INTF, 1);
760 gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FAL_INTF, 1);
761 }
762
763 if (state == GMU_WARM_BOOT) {
764 ret = a6xx_rpmh_start(gmu);
765 if (ret)
766 return ret;
767 } else {
768 if (WARN(!adreno_gpu->fw[ADRENO_FW_GMU],
769 "GMU firmware is not loaded\n"))
770 return -ENOENT;
771
772 /* Turn on register retention */
773 gmu_write(gmu, REG_A6XX_GMU_GENERAL_7, 1);
774
775 /* We only need to load the RPMh microcode once */
776 if (!rpmh_init) {
777 a6xx_gmu_rpmh_init(gmu);
778 rpmh_init = true;
779 } else {
780 ret = a6xx_rpmh_start(gmu);
781 if (ret)
782 return ret;
783 }
784
785 ret = a6xx_gmu_fw_load(gmu);
786 if (ret)
787 return ret;
788 }
789
790 gmu_write(gmu, REG_A6XX_GMU_CM3_FW_INIT_RESULT, 0);
791 gmu_write(gmu, REG_A6XX_GMU_CM3_BOOT_CONFIG, 0x02);
792
793 /* Write the iova of the HFI table */
794 gmu_write(gmu, REG_A6XX_GMU_HFI_QTBL_ADDR, gmu->hfi.iova);
795 gmu_write(gmu, REG_A6XX_GMU_HFI_QTBL_INFO, 1);
796
797 gmu_write(gmu, REG_A6XX_GMU_AHB_FENCE_RANGE_0,
798 (1 << 31) | (0xa << 18) | (0xa0));
799
800 chipid = adreno_gpu->rev.core << 24;
801 chipid |= adreno_gpu->rev.major << 16;
802 chipid |= adreno_gpu->rev.minor << 12;
803 chipid |= adreno_gpu->rev.patchid << 8;
804
805 gmu_write(gmu, REG_A6XX_GMU_HFI_SFR_ADDR, chipid);
806
807 gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_MSG,
808 gmu->log.iova | (gmu->log.size / SZ_4K - 1));
809
810 /* Set up the lowest idle level on the GMU */
811 a6xx_gmu_power_config(gmu);
812
813 ret = a6xx_gmu_start(gmu);
814 if (ret)
815 return ret;
816
817 if (gmu->legacy) {
818 ret = a6xx_gmu_gfx_rail_on(gmu);
819 if (ret)
820 return ret;
821 }
822
823 /* Enable SPTP_PC if the CPU is responsible for it */
824 if (gmu->idle_level < GMU_IDLE_STATE_SPTP) {
825 ret = a6xx_sptprac_enable(gmu);
826 if (ret)
827 return ret;
828 }
829
830 ret = a6xx_gmu_hfi_start(gmu);
831 if (ret)
832 return ret;
833
834 /* FIXME: Do we need this wmb() here? */
835 wmb();
836
837 return 0;
838 }
839
840 #define A6XX_HFI_IRQ_MASK \
841 (A6XX_GMU_GMU2HOST_INTR_INFO_CM3_FAULT)
842
843 #define A6XX_GMU_IRQ_MASK \
844 (A6XX_GMU_AO_HOST_INTERRUPT_STATUS_WDOG_BITE | \
845 A6XX_GMU_AO_HOST_INTERRUPT_STATUS_HOST_AHB_BUS_ERROR | \
846 A6XX_GMU_AO_HOST_INTERRUPT_STATUS_FENCE_ERR)
847
a6xx_gmu_irq_disable(struct a6xx_gmu * gmu)848 static void a6xx_gmu_irq_disable(struct a6xx_gmu *gmu)
849 {
850 disable_irq(gmu->gmu_irq);
851 disable_irq(gmu->hfi_irq);
852
853 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK, ~0);
854 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, ~0);
855 }
856
a6xx_gmu_rpmh_off(struct a6xx_gmu * gmu)857 static void a6xx_gmu_rpmh_off(struct a6xx_gmu *gmu)
858 {
859 u32 val;
860
861 /* Make sure there are no outstanding RPMh votes */
862 gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS0_DRV0_STATUS, val,
863 (val & 1), 100, 10000);
864 gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS1_DRV0_STATUS, val,
865 (val & 1), 100, 10000);
866 gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS2_DRV0_STATUS, val,
867 (val & 1), 100, 10000);
868 gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS3_DRV0_STATUS, val,
869 (val & 1), 100, 1000);
870 }
871
872 /* Force the GMU off in case it isn't responsive */
a6xx_gmu_force_off(struct a6xx_gmu * gmu)873 static void a6xx_gmu_force_off(struct a6xx_gmu *gmu)
874 {
875 /* Flush all the queues */
876 a6xx_hfi_stop(gmu);
877
878 /* Stop the interrupts */
879 a6xx_gmu_irq_disable(gmu);
880
881 /* Force off SPTP in case the GMU is managing it */
882 a6xx_sptprac_disable(gmu);
883
884 /* Make sure there are no outstanding RPMh votes */
885 a6xx_gmu_rpmh_off(gmu);
886 }
887
a6xx_gmu_set_initial_freq(struct msm_gpu * gpu,struct a6xx_gmu * gmu)888 static void a6xx_gmu_set_initial_freq(struct msm_gpu *gpu, struct a6xx_gmu *gmu)
889 {
890 struct dev_pm_opp *gpu_opp;
891 unsigned long gpu_freq = gmu->gpu_freqs[gmu->current_perf_index];
892
893 gpu_opp = dev_pm_opp_find_freq_exact(&gpu->pdev->dev, gpu_freq, true);
894 if (IS_ERR(gpu_opp))
895 return;
896
897 gmu->freq = 0; /* so a6xx_gmu_set_freq() doesn't exit early */
898 a6xx_gmu_set_freq(gpu, gpu_opp);
899 dev_pm_opp_put(gpu_opp);
900 }
901
a6xx_gmu_set_initial_bw(struct msm_gpu * gpu,struct a6xx_gmu * gmu)902 static void a6xx_gmu_set_initial_bw(struct msm_gpu *gpu, struct a6xx_gmu *gmu)
903 {
904 struct dev_pm_opp *gpu_opp;
905 unsigned long gpu_freq = gmu->gpu_freqs[gmu->current_perf_index];
906
907 gpu_opp = dev_pm_opp_find_freq_exact(&gpu->pdev->dev, gpu_freq, true);
908 if (IS_ERR(gpu_opp))
909 return;
910
911 dev_pm_opp_set_opp(&gpu->pdev->dev, gpu_opp);
912 dev_pm_opp_put(gpu_opp);
913 }
914
a6xx_gmu_resume(struct a6xx_gpu * a6xx_gpu)915 int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu)
916 {
917 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
918 struct msm_gpu *gpu = &adreno_gpu->base;
919 struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
920 int status, ret;
921
922 if (WARN(!gmu->initialized, "The GMU is not set up yet\n"))
923 return 0;
924
925 gmu->hung = false;
926
927 /* Turn on the resources */
928 pm_runtime_get_sync(gmu->dev);
929
930 /*
931 * "enable" the GX power domain which won't actually do anything but it
932 * will make sure that the refcounting is correct in case we need to
933 * bring down the GX after a GMU failure
934 */
935 if (!IS_ERR_OR_NULL(gmu->gxpd))
936 pm_runtime_get_sync(gmu->gxpd);
937
938 /* Use a known rate to bring up the GMU */
939 clk_set_rate(gmu->core_clk, 200000000);
940 clk_set_rate(gmu->hub_clk, 150000000);
941 ret = clk_bulk_prepare_enable(gmu->nr_clocks, gmu->clocks);
942 if (ret) {
943 pm_runtime_put(gmu->gxpd);
944 pm_runtime_put(gmu->dev);
945 return ret;
946 }
947
948 /* Set the bus quota to a reasonable value for boot */
949 a6xx_gmu_set_initial_bw(gpu, gmu);
950
951 /* Enable the GMU interrupt */
952 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, ~0);
953 gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK, ~A6XX_GMU_IRQ_MASK);
954 enable_irq(gmu->gmu_irq);
955
956 /* Check to see if we are doing a cold or warm boot */
957 status = gmu_read(gmu, REG_A6XX_GMU_GENERAL_7) == 1 ?
958 GMU_WARM_BOOT : GMU_COLD_BOOT;
959
960 /*
961 * Warm boot path does not work on newer GPUs
962 * Presumably this is because icache/dcache regions must be restored
963 */
964 if (!gmu->legacy)
965 status = GMU_COLD_BOOT;
966
967 ret = a6xx_gmu_fw_start(gmu, status);
968 if (ret)
969 goto out;
970
971 ret = a6xx_hfi_start(gmu, status);
972 if (ret)
973 goto out;
974
975 /*
976 * Turn on the GMU firmware fault interrupt after we know the boot
977 * sequence is successful
978 */
979 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, ~0);
980 gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, ~A6XX_HFI_IRQ_MASK);
981 enable_irq(gmu->hfi_irq);
982
983 /* Set the GPU to the current freq */
984 a6xx_gmu_set_initial_freq(gpu, gmu);
985
986 out:
987 /* On failure, shut down the GMU to leave it in a good state */
988 if (ret) {
989 disable_irq(gmu->gmu_irq);
990 a6xx_rpmh_stop(gmu);
991 pm_runtime_put(gmu->gxpd);
992 pm_runtime_put(gmu->dev);
993 }
994
995 return ret;
996 }
997
a6xx_gmu_isidle(struct a6xx_gmu * gmu)998 bool a6xx_gmu_isidle(struct a6xx_gmu *gmu)
999 {
1000 u32 reg;
1001
1002 if (!gmu->initialized)
1003 return true;
1004
1005 reg = gmu_read(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS);
1006
1007 if (reg & A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS_GPUBUSYIGNAHB)
1008 return false;
1009
1010 return true;
1011 }
1012
1013 #define GBIF_CLIENT_HALT_MASK BIT(0)
1014 #define GBIF_ARB_HALT_MASK BIT(1)
1015
a6xx_bus_clear_pending_transactions(struct adreno_gpu * adreno_gpu)1016 static void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu)
1017 {
1018 struct msm_gpu *gpu = &adreno_gpu->base;
1019
1020 if (!a6xx_has_gbif(adreno_gpu)) {
1021 gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0xf);
1022 spin_until((gpu_read(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL1) &
1023 0xf) == 0xf);
1024 gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0);
1025
1026 return;
1027 }
1028
1029 /* Halt new client requests on GBIF */
1030 gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_CLIENT_HALT_MASK);
1031 spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) &
1032 (GBIF_CLIENT_HALT_MASK)) == GBIF_CLIENT_HALT_MASK);
1033
1034 /* Halt all AXI requests on GBIF */
1035 gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_ARB_HALT_MASK);
1036 spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) &
1037 (GBIF_ARB_HALT_MASK)) == GBIF_ARB_HALT_MASK);
1038
1039 /* The GBIF halt needs to be explicitly cleared */
1040 gpu_write(gpu, REG_A6XX_GBIF_HALT, 0x0);
1041 }
1042
1043 /* Gracefully try to shut down the GMU and by extension the GPU */
a6xx_gmu_shutdown(struct a6xx_gmu * gmu)1044 static void a6xx_gmu_shutdown(struct a6xx_gmu *gmu)
1045 {
1046 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
1047 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
1048 u32 val;
1049
1050 /*
1051 * The GMU may still be in slumber unless the GPU started so check and
1052 * skip putting it back into slumber if so
1053 */
1054 val = gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE);
1055
1056 if (val != 0xf) {
1057 int ret = a6xx_gmu_wait_for_idle(gmu);
1058
1059 /* If the GMU isn't responding assume it is hung */
1060 if (ret) {
1061 a6xx_gmu_force_off(gmu);
1062 return;
1063 }
1064
1065 a6xx_bus_clear_pending_transactions(adreno_gpu);
1066
1067 /* tell the GMU we want to slumber */
1068 a6xx_gmu_notify_slumber(gmu);
1069
1070 ret = gmu_poll_timeout(gmu,
1071 REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS, val,
1072 !(val & A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS_GPUBUSYIGNAHB),
1073 100, 10000);
1074
1075 /*
1076 * Let the user know we failed to slumber but don't worry too
1077 * much because we are powering down anyway
1078 */
1079
1080 if (ret)
1081 DRM_DEV_ERROR(gmu->dev,
1082 "Unable to slumber GMU: status = 0%x/0%x\n",
1083 gmu_read(gmu,
1084 REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS),
1085 gmu_read(gmu,
1086 REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS2));
1087 }
1088
1089 /* Turn off HFI */
1090 a6xx_hfi_stop(gmu);
1091
1092 /* Stop the interrupts and mask the hardware */
1093 a6xx_gmu_irq_disable(gmu);
1094
1095 /* Tell RPMh to power off the GPU */
1096 a6xx_rpmh_stop(gmu);
1097 }
1098
1099
a6xx_gmu_stop(struct a6xx_gpu * a6xx_gpu)1100 int a6xx_gmu_stop(struct a6xx_gpu *a6xx_gpu)
1101 {
1102 struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
1103 struct msm_gpu *gpu = &a6xx_gpu->base.base;
1104
1105 if (!pm_runtime_active(gmu->dev))
1106 return 0;
1107
1108 /*
1109 * Force the GMU off if we detected a hang, otherwise try to shut it
1110 * down gracefully
1111 */
1112 if (gmu->hung)
1113 a6xx_gmu_force_off(gmu);
1114 else
1115 a6xx_gmu_shutdown(gmu);
1116
1117 /* Remove the bus vote */
1118 dev_pm_opp_set_opp(&gpu->pdev->dev, NULL);
1119
1120 /*
1121 * Make sure the GX domain is off before turning off the GMU (CX)
1122 * domain. Usually the GMU does this but only if the shutdown sequence
1123 * was successful
1124 */
1125 if (!IS_ERR_OR_NULL(gmu->gxpd))
1126 pm_runtime_put_sync(gmu->gxpd);
1127
1128 clk_bulk_disable_unprepare(gmu->nr_clocks, gmu->clocks);
1129
1130 pm_runtime_put_sync(gmu->dev);
1131
1132 return 0;
1133 }
1134
a6xx_gmu_memory_free(struct a6xx_gmu * gmu)1135 static void a6xx_gmu_memory_free(struct a6xx_gmu *gmu)
1136 {
1137 msm_gem_kernel_put(gmu->hfi.obj, gmu->aspace);
1138 msm_gem_kernel_put(gmu->debug.obj, gmu->aspace);
1139 msm_gem_kernel_put(gmu->icache.obj, gmu->aspace);
1140 msm_gem_kernel_put(gmu->dcache.obj, gmu->aspace);
1141 msm_gem_kernel_put(gmu->dummy.obj, gmu->aspace);
1142 msm_gem_kernel_put(gmu->log.obj, gmu->aspace);
1143
1144 gmu->aspace->mmu->funcs->detach(gmu->aspace->mmu);
1145 msm_gem_address_space_put(gmu->aspace);
1146 }
1147
a6xx_gmu_memory_alloc(struct a6xx_gmu * gmu,struct a6xx_gmu_bo * bo,size_t size,u64 iova)1148 static int a6xx_gmu_memory_alloc(struct a6xx_gmu *gmu, struct a6xx_gmu_bo *bo,
1149 size_t size, u64 iova)
1150 {
1151 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
1152 struct drm_device *dev = a6xx_gpu->base.base.dev;
1153 uint32_t flags = MSM_BO_WC;
1154 u64 range_start, range_end;
1155 int ret;
1156
1157 size = PAGE_ALIGN(size);
1158 if (!iova) {
1159 /* no fixed address - use GMU's uncached range */
1160 range_start = 0x60000000 + PAGE_SIZE; /* skip dummy page */
1161 range_end = 0x80000000;
1162 } else {
1163 /* range for fixed address */
1164 range_start = iova;
1165 range_end = iova + size;
1166 /* use IOMMU_PRIV for icache/dcache */
1167 flags |= MSM_BO_MAP_PRIV;
1168 }
1169
1170 bo->obj = msm_gem_new(dev, size, flags);
1171 if (IS_ERR(bo->obj))
1172 return PTR_ERR(bo->obj);
1173
1174 ret = msm_gem_get_and_pin_iova_range(bo->obj, gmu->aspace, &bo->iova,
1175 range_start >> PAGE_SHIFT, range_end >> PAGE_SHIFT);
1176 if (ret) {
1177 drm_gem_object_put(bo->obj);
1178 return ret;
1179 }
1180
1181 bo->virt = msm_gem_get_vaddr(bo->obj);
1182 bo->size = size;
1183
1184 return 0;
1185 }
1186
a6xx_gmu_memory_probe(struct a6xx_gmu * gmu)1187 static int a6xx_gmu_memory_probe(struct a6xx_gmu *gmu)
1188 {
1189 struct iommu_domain *domain;
1190 struct msm_mmu *mmu;
1191
1192 domain = iommu_domain_alloc(&platform_bus_type);
1193 if (!domain)
1194 return -ENODEV;
1195
1196 mmu = msm_iommu_new(gmu->dev, domain);
1197 gmu->aspace = msm_gem_address_space_create(mmu, "gmu", 0x0, 0x80000000);
1198 if (IS_ERR(gmu->aspace)) {
1199 iommu_domain_free(domain);
1200 return PTR_ERR(gmu->aspace);
1201 }
1202
1203 return 0;
1204 }
1205
1206 /* Return the 'arc-level' for the given frequency */
a6xx_gmu_get_arc_level(struct device * dev,unsigned long freq)1207 static unsigned int a6xx_gmu_get_arc_level(struct device *dev,
1208 unsigned long freq)
1209 {
1210 struct dev_pm_opp *opp;
1211 unsigned int val;
1212
1213 if (!freq)
1214 return 0;
1215
1216 opp = dev_pm_opp_find_freq_exact(dev, freq, true);
1217 if (IS_ERR(opp))
1218 return 0;
1219
1220 val = dev_pm_opp_get_level(opp);
1221
1222 dev_pm_opp_put(opp);
1223
1224 return val;
1225 }
1226
a6xx_gmu_rpmh_arc_votes_init(struct device * dev,u32 * votes,unsigned long * freqs,int freqs_count,const char * id)1227 static int a6xx_gmu_rpmh_arc_votes_init(struct device *dev, u32 *votes,
1228 unsigned long *freqs, int freqs_count, const char *id)
1229 {
1230 int i, j;
1231 const u16 *pri, *sec;
1232 size_t pri_count, sec_count;
1233
1234 pri = cmd_db_read_aux_data(id, &pri_count);
1235 if (IS_ERR(pri))
1236 return PTR_ERR(pri);
1237 /*
1238 * The data comes back as an array of unsigned shorts so adjust the
1239 * count accordingly
1240 */
1241 pri_count >>= 1;
1242 if (!pri_count)
1243 return -EINVAL;
1244
1245 sec = cmd_db_read_aux_data("mx.lvl", &sec_count);
1246 if (IS_ERR(sec))
1247 return PTR_ERR(sec);
1248
1249 sec_count >>= 1;
1250 if (!sec_count)
1251 return -EINVAL;
1252
1253 /* Construct a vote for each frequency */
1254 for (i = 0; i < freqs_count; i++) {
1255 u8 pindex = 0, sindex = 0;
1256 unsigned int level = a6xx_gmu_get_arc_level(dev, freqs[i]);
1257
1258 /* Get the primary index that matches the arc level */
1259 for (j = 0; j < pri_count; j++) {
1260 if (pri[j] >= level) {
1261 pindex = j;
1262 break;
1263 }
1264 }
1265
1266 if (j == pri_count) {
1267 DRM_DEV_ERROR(dev,
1268 "Level %u not found in the RPMh list\n",
1269 level);
1270 DRM_DEV_ERROR(dev, "Available levels:\n");
1271 for (j = 0; j < pri_count; j++)
1272 DRM_DEV_ERROR(dev, " %u\n", pri[j]);
1273
1274 return -EINVAL;
1275 }
1276
1277 /*
1278 * Look for a level in in the secondary list that matches. If
1279 * nothing fits, use the maximum non zero vote
1280 */
1281
1282 for (j = 0; j < sec_count; j++) {
1283 if (sec[j] >= level) {
1284 sindex = j;
1285 break;
1286 } else if (sec[j]) {
1287 sindex = j;
1288 }
1289 }
1290
1291 /* Construct the vote */
1292 votes[i] = ((pri[pindex] & 0xffff) << 16) |
1293 (sindex << 8) | pindex;
1294 }
1295
1296 return 0;
1297 }
1298
1299 /*
1300 * The GMU votes with the RPMh for itself and on behalf of the GPU but we need
1301 * to construct the list of votes on the CPU and send it over. Query the RPMh
1302 * voltage levels and build the votes
1303 */
1304
a6xx_gmu_rpmh_votes_init(struct a6xx_gmu * gmu)1305 static int a6xx_gmu_rpmh_votes_init(struct a6xx_gmu *gmu)
1306 {
1307 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
1308 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
1309 struct msm_gpu *gpu = &adreno_gpu->base;
1310 int ret;
1311
1312 /* Build the GX votes */
1313 ret = a6xx_gmu_rpmh_arc_votes_init(&gpu->pdev->dev, gmu->gx_arc_votes,
1314 gmu->gpu_freqs, gmu->nr_gpu_freqs, "gfx.lvl");
1315
1316 /* Build the CX votes */
1317 ret |= a6xx_gmu_rpmh_arc_votes_init(gmu->dev, gmu->cx_arc_votes,
1318 gmu->gmu_freqs, gmu->nr_gmu_freqs, "cx.lvl");
1319
1320 return ret;
1321 }
1322
a6xx_gmu_build_freq_table(struct device * dev,unsigned long * freqs,u32 size)1323 static int a6xx_gmu_build_freq_table(struct device *dev, unsigned long *freqs,
1324 u32 size)
1325 {
1326 int count = dev_pm_opp_get_opp_count(dev);
1327 struct dev_pm_opp *opp;
1328 int i, index = 0;
1329 unsigned long freq = 1;
1330
1331 /*
1332 * The OPP table doesn't contain the "off" frequency level so we need to
1333 * add 1 to the table size to account for it
1334 */
1335
1336 if (WARN(count + 1 > size,
1337 "The GMU frequency table is being truncated\n"))
1338 count = size - 1;
1339
1340 /* Set the "off" frequency */
1341 freqs[index++] = 0;
1342
1343 for (i = 0; i < count; i++) {
1344 opp = dev_pm_opp_find_freq_ceil(dev, &freq);
1345 if (IS_ERR(opp))
1346 break;
1347
1348 dev_pm_opp_put(opp);
1349 freqs[index++] = freq++;
1350 }
1351
1352 return index;
1353 }
1354
a6xx_gmu_pwrlevels_probe(struct a6xx_gmu * gmu)1355 static int a6xx_gmu_pwrlevels_probe(struct a6xx_gmu *gmu)
1356 {
1357 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
1358 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
1359 struct msm_gpu *gpu = &adreno_gpu->base;
1360
1361 int ret = 0;
1362
1363 /*
1364 * The GMU handles its own frequency switching so build a list of
1365 * available frequencies to send during initialization
1366 */
1367 ret = devm_pm_opp_of_add_table(gmu->dev);
1368 if (ret) {
1369 DRM_DEV_ERROR(gmu->dev, "Unable to set the OPP table for the GMU\n");
1370 return ret;
1371 }
1372
1373 gmu->nr_gmu_freqs = a6xx_gmu_build_freq_table(gmu->dev,
1374 gmu->gmu_freqs, ARRAY_SIZE(gmu->gmu_freqs));
1375
1376 /*
1377 * The GMU also handles GPU frequency switching so build a list
1378 * from the GPU OPP table
1379 */
1380 gmu->nr_gpu_freqs = a6xx_gmu_build_freq_table(&gpu->pdev->dev,
1381 gmu->gpu_freqs, ARRAY_SIZE(gmu->gpu_freqs));
1382
1383 gmu->current_perf_index = gmu->nr_gpu_freqs - 1;
1384
1385 /* Build the list of RPMh votes that we'll send to the GMU */
1386 return a6xx_gmu_rpmh_votes_init(gmu);
1387 }
1388
a6xx_gmu_clocks_probe(struct a6xx_gmu * gmu)1389 static int a6xx_gmu_clocks_probe(struct a6xx_gmu *gmu)
1390 {
1391 int ret = devm_clk_bulk_get_all(gmu->dev, &gmu->clocks);
1392
1393 if (ret < 1)
1394 return ret;
1395
1396 gmu->nr_clocks = ret;
1397
1398 gmu->core_clk = msm_clk_bulk_get_clock(gmu->clocks,
1399 gmu->nr_clocks, "gmu");
1400
1401 gmu->hub_clk = msm_clk_bulk_get_clock(gmu->clocks,
1402 gmu->nr_clocks, "hub");
1403
1404 return 0;
1405 }
1406
a6xx_gmu_get_mmio(struct platform_device * pdev,const char * name)1407 static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev,
1408 const char *name)
1409 {
1410 void __iomem *ret;
1411 struct resource *res = platform_get_resource_byname(pdev,
1412 IORESOURCE_MEM, name);
1413
1414 if (!res) {
1415 DRM_DEV_ERROR(&pdev->dev, "Unable to find the %s registers\n", name);
1416 return ERR_PTR(-EINVAL);
1417 }
1418
1419 ret = ioremap(res->start, resource_size(res));
1420 if (!ret) {
1421 DRM_DEV_ERROR(&pdev->dev, "Unable to map the %s registers\n", name);
1422 return ERR_PTR(-EINVAL);
1423 }
1424
1425 return ret;
1426 }
1427
a6xx_gmu_get_irq(struct a6xx_gmu * gmu,struct platform_device * pdev,const char * name,irq_handler_t handler)1428 static int a6xx_gmu_get_irq(struct a6xx_gmu *gmu, struct platform_device *pdev,
1429 const char *name, irq_handler_t handler)
1430 {
1431 int irq, ret;
1432
1433 irq = platform_get_irq_byname(pdev, name);
1434
1435 ret = request_irq(irq, handler, IRQF_TRIGGER_HIGH, name, gmu);
1436 if (ret) {
1437 DRM_DEV_ERROR(&pdev->dev, "Unable to get interrupt %s %d\n",
1438 name, ret);
1439 return ret;
1440 }
1441
1442 disable_irq(irq);
1443
1444 return irq;
1445 }
1446
a6xx_gmu_remove(struct a6xx_gpu * a6xx_gpu)1447 void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu)
1448 {
1449 struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
1450 struct platform_device *pdev = to_platform_device(gmu->dev);
1451
1452 if (!gmu->initialized)
1453 return;
1454
1455 pm_runtime_force_suspend(gmu->dev);
1456
1457 if (!IS_ERR_OR_NULL(gmu->gxpd)) {
1458 pm_runtime_disable(gmu->gxpd);
1459 dev_pm_domain_detach(gmu->gxpd, false);
1460 }
1461
1462 iounmap(gmu->mmio);
1463 if (platform_get_resource_byname(pdev, IORESOURCE_MEM, "rscc"))
1464 iounmap(gmu->rscc);
1465 gmu->mmio = NULL;
1466 gmu->rscc = NULL;
1467
1468 a6xx_gmu_memory_free(gmu);
1469
1470 free_irq(gmu->gmu_irq, gmu);
1471 free_irq(gmu->hfi_irq, gmu);
1472
1473 /* Drop reference taken in of_find_device_by_node */
1474 put_device(gmu->dev);
1475
1476 gmu->initialized = false;
1477 }
1478
a6xx_gmu_init(struct a6xx_gpu * a6xx_gpu,struct device_node * node)1479 int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
1480 {
1481 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
1482 struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
1483 struct platform_device *pdev = of_find_device_by_node(node);
1484 int ret;
1485
1486 if (!pdev)
1487 return -ENODEV;
1488
1489 mutex_init(&gmu->lock);
1490
1491 gmu->dev = &pdev->dev;
1492
1493 of_dma_configure(gmu->dev, node, true);
1494
1495 /* Fow now, don't do anything fancy until we get our feet under us */
1496 gmu->idle_level = GMU_IDLE_STATE_ACTIVE;
1497
1498 pm_runtime_enable(gmu->dev);
1499
1500 /* Get the list of clocks */
1501 ret = a6xx_gmu_clocks_probe(gmu);
1502 if (ret)
1503 goto err_put_device;
1504
1505 ret = a6xx_gmu_memory_probe(gmu);
1506 if (ret)
1507 goto err_put_device;
1508
1509
1510 /* A660 now requires handling "prealloc requests" in GMU firmware
1511 * For now just hardcode allocations based on the known firmware.
1512 * note: there is no indication that these correspond to "dummy" or
1513 * "debug" regions, but this "guess" allows reusing these BOs which
1514 * are otherwise unused by a660.
1515 */
1516 gmu->dummy.size = SZ_4K;
1517 if (adreno_is_a660_family(adreno_gpu)) {
1518 ret = a6xx_gmu_memory_alloc(gmu, &gmu->debug, SZ_4K * 7, 0x60400000);
1519 if (ret)
1520 goto err_memory;
1521
1522 gmu->dummy.size = SZ_8K;
1523 }
1524
1525 /* Allocate memory for the GMU dummy page */
1526 ret = a6xx_gmu_memory_alloc(gmu, &gmu->dummy, gmu->dummy.size, 0x60000000);
1527 if (ret)
1528 goto err_memory;
1529
1530 if (adreno_is_a650_family(adreno_gpu)) {
1531 ret = a6xx_gmu_memory_alloc(gmu, &gmu->icache,
1532 SZ_16M - SZ_16K, 0x04000);
1533 if (ret)
1534 goto err_memory;
1535 } else if (adreno_is_a640_family(adreno_gpu)) {
1536 ret = a6xx_gmu_memory_alloc(gmu, &gmu->icache,
1537 SZ_256K - SZ_16K, 0x04000);
1538 if (ret)
1539 goto err_memory;
1540
1541 ret = a6xx_gmu_memory_alloc(gmu, &gmu->dcache,
1542 SZ_256K - SZ_16K, 0x44000);
1543 if (ret)
1544 goto err_memory;
1545 } else {
1546 /* HFI v1, has sptprac */
1547 gmu->legacy = true;
1548
1549 /* Allocate memory for the GMU debug region */
1550 ret = a6xx_gmu_memory_alloc(gmu, &gmu->debug, SZ_16K, 0);
1551 if (ret)
1552 goto err_memory;
1553 }
1554
1555 /* Allocate memory for for the HFI queues */
1556 ret = a6xx_gmu_memory_alloc(gmu, &gmu->hfi, SZ_16K, 0);
1557 if (ret)
1558 goto err_memory;
1559
1560 /* Allocate memory for the GMU log region */
1561 ret = a6xx_gmu_memory_alloc(gmu, &gmu->log, SZ_4K, 0);
1562 if (ret)
1563 goto err_memory;
1564
1565 /* Map the GMU registers */
1566 gmu->mmio = a6xx_gmu_get_mmio(pdev, "gmu");
1567 if (IS_ERR(gmu->mmio)) {
1568 ret = PTR_ERR(gmu->mmio);
1569 goto err_memory;
1570 }
1571
1572 if (adreno_is_a650_family(adreno_gpu)) {
1573 gmu->rscc = a6xx_gmu_get_mmio(pdev, "rscc");
1574 if (IS_ERR(gmu->rscc))
1575 goto err_mmio;
1576 } else {
1577 gmu->rscc = gmu->mmio + 0x23000;
1578 }
1579
1580 /* Get the HFI and GMU interrupts */
1581 gmu->hfi_irq = a6xx_gmu_get_irq(gmu, pdev, "hfi", a6xx_hfi_irq);
1582 gmu->gmu_irq = a6xx_gmu_get_irq(gmu, pdev, "gmu", a6xx_gmu_irq);
1583
1584 if (gmu->hfi_irq < 0 || gmu->gmu_irq < 0)
1585 goto err_mmio;
1586
1587 /*
1588 * Get a link to the GX power domain to reset the GPU in case of GMU
1589 * crash
1590 */
1591 gmu->gxpd = dev_pm_domain_attach_by_name(gmu->dev, "gx");
1592
1593 /* Get the power levels for the GMU and GPU */
1594 a6xx_gmu_pwrlevels_probe(gmu);
1595
1596 /* Set up the HFI queues */
1597 a6xx_hfi_init(gmu);
1598
1599 gmu->initialized = true;
1600
1601 return 0;
1602
1603 err_mmio:
1604 iounmap(gmu->mmio);
1605 if (platform_get_resource_byname(pdev, IORESOURCE_MEM, "rscc"))
1606 iounmap(gmu->rscc);
1607 free_irq(gmu->gmu_irq, gmu);
1608 free_irq(gmu->hfi_irq, gmu);
1609
1610 ret = -ENODEV;
1611
1612 err_memory:
1613 a6xx_gmu_memory_free(gmu);
1614 err_put_device:
1615 /* Drop reference taken in of_find_device_by_node */
1616 put_device(gmu->dev);
1617
1618 return ret;
1619 }
1620