1 // SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only)
2 /* Copyright(c) 2015 - 2020 Intel Corporation */
3 #include <adf_accel_devices.h>
4 #include <adf_pf2vf_msg.h>
5 #include <adf_common_drv.h>
6 #include <adf_gen2_hw_data.h>
7 #include "adf_c3xxxvf_hw_data.h"
8 
9 static struct adf_hw_device_class c3xxxiov_class = {
10 	.name = ADF_C3XXXVF_DEVICE_NAME,
11 	.type = DEV_C3XXXVF,
12 	.instances = 0
13 };
14 
get_accel_mask(struct adf_hw_device_data * self)15 static u32 get_accel_mask(struct adf_hw_device_data *self)
16 {
17 	return ADF_C3XXXIOV_ACCELERATORS_MASK;
18 }
19 
get_ae_mask(struct adf_hw_device_data * self)20 static u32 get_ae_mask(struct adf_hw_device_data *self)
21 {
22 	return ADF_C3XXXIOV_ACCELENGINES_MASK;
23 }
24 
get_num_accels(struct adf_hw_device_data * self)25 static u32 get_num_accels(struct adf_hw_device_data *self)
26 {
27 	return ADF_C3XXXIOV_MAX_ACCELERATORS;
28 }
29 
get_num_aes(struct adf_hw_device_data * self)30 static u32 get_num_aes(struct adf_hw_device_data *self)
31 {
32 	return ADF_C3XXXIOV_MAX_ACCELENGINES;
33 }
34 
get_misc_bar_id(struct adf_hw_device_data * self)35 static u32 get_misc_bar_id(struct adf_hw_device_data *self)
36 {
37 	return ADF_C3XXXIOV_PMISC_BAR;
38 }
39 
get_etr_bar_id(struct adf_hw_device_data * self)40 static u32 get_etr_bar_id(struct adf_hw_device_data *self)
41 {
42 	return ADF_C3XXXIOV_ETR_BAR;
43 }
44 
get_sku(struct adf_hw_device_data * self)45 static enum dev_sku_info get_sku(struct adf_hw_device_data *self)
46 {
47 	return DEV_SKU_VF;
48 }
49 
get_pf2vf_offset(u32 i)50 static u32 get_pf2vf_offset(u32 i)
51 {
52 	return ADF_C3XXXIOV_PF2VF_OFFSET;
53 }
54 
adf_vf_int_noop(struct adf_accel_dev * accel_dev)55 static int adf_vf_int_noop(struct adf_accel_dev *accel_dev)
56 {
57 	return 0;
58 }
59 
adf_vf_void_noop(struct adf_accel_dev * accel_dev)60 static void adf_vf_void_noop(struct adf_accel_dev *accel_dev)
61 {
62 }
63 
adf_init_hw_data_c3xxxiov(struct adf_hw_device_data * hw_data)64 void adf_init_hw_data_c3xxxiov(struct adf_hw_device_data *hw_data)
65 {
66 	hw_data->dev_class = &c3xxxiov_class;
67 	hw_data->num_banks = ADF_C3XXXIOV_ETR_MAX_BANKS;
68 	hw_data->num_rings_per_bank = ADF_ETR_MAX_RINGS_PER_BANK;
69 	hw_data->num_accel = ADF_C3XXXIOV_MAX_ACCELERATORS;
70 	hw_data->num_logical_accel = 1;
71 	hw_data->num_engines = ADF_C3XXXIOV_MAX_ACCELENGINES;
72 	hw_data->tx_rx_gap = ADF_C3XXXIOV_RX_RINGS_OFFSET;
73 	hw_data->tx_rings_mask = ADF_C3XXXIOV_TX_RINGS_MASK;
74 	hw_data->alloc_irq = adf_vf_isr_resource_alloc;
75 	hw_data->free_irq = adf_vf_isr_resource_free;
76 	hw_data->enable_error_correction = adf_vf_void_noop;
77 	hw_data->init_admin_comms = adf_vf_int_noop;
78 	hw_data->exit_admin_comms = adf_vf_void_noop;
79 	hw_data->send_admin_init = adf_vf2pf_notify_init;
80 	hw_data->init_arb = adf_vf_int_noop;
81 	hw_data->exit_arb = adf_vf_void_noop;
82 	hw_data->disable_iov = adf_vf2pf_notify_shutdown;
83 	hw_data->get_accel_mask = get_accel_mask;
84 	hw_data->get_ae_mask = get_ae_mask;
85 	hw_data->get_num_accels = get_num_accels;
86 	hw_data->get_num_aes = get_num_aes;
87 	hw_data->get_etr_bar_id = get_etr_bar_id;
88 	hw_data->get_misc_bar_id = get_misc_bar_id;
89 	hw_data->get_pf2vf_offset = get_pf2vf_offset;
90 	hw_data->get_sku = get_sku;
91 	hw_data->enable_ints = adf_vf_void_noop;
92 	hw_data->enable_pfvf_comms = adf_enable_vf2pf_comms;
93 	hw_data->min_iov_compat_ver = ADF_PFVF_COMPAT_THIS_VERSION;
94 	hw_data->dev_class->instances++;
95 	adf_devmgr_update_class_index(hw_data);
96 	adf_gen2_init_hw_csr_ops(&hw_data->csr_ops);
97 }
98 
adf_clean_hw_data_c3xxxiov(struct adf_hw_device_data * hw_data)99 void adf_clean_hw_data_c3xxxiov(struct adf_hw_device_data *hw_data)
100 {
101 	hw_data->dev_class->instances--;
102 	adf_devmgr_update_class_index(hw_data);
103 }
104