1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */
2 /* Copyright(c) 2014 - 2020 Intel Corporation */
3 #ifndef ADF_ACCEL_DEVICES_H_
4 #define ADF_ACCEL_DEVICES_H_
5 #include <linux/interrupt.h>
6 #include <linux/module.h>
7 #include <linux/list.h>
8 #include <linux/io.h>
9 #include <linux/ratelimit.h>
10 #include "adf_cfg_common.h"
11
12 #define ADF_DH895XCC_DEVICE_NAME "dh895xcc"
13 #define ADF_DH895XCCVF_DEVICE_NAME "dh895xccvf"
14 #define ADF_C62X_DEVICE_NAME "c6xx"
15 #define ADF_C62XVF_DEVICE_NAME "c6xxvf"
16 #define ADF_C3XXX_DEVICE_NAME "c3xxx"
17 #define ADF_C3XXXVF_DEVICE_NAME "c3xxxvf"
18 #define ADF_4XXX_DEVICE_NAME "4xxx"
19 #define ADF_4XXX_PCI_DEVICE_ID 0x4940
20 #define ADF_4XXXIOV_PCI_DEVICE_ID 0x4941
21 #define ADF_DEVICE_FUSECTL_OFFSET 0x40
22 #define ADF_DEVICE_LEGFUSE_OFFSET 0x4C
23 #define ADF_DEVICE_FUSECTL_MASK 0x80000000
24 #define ADF_PCI_MAX_BARS 3
25 #define ADF_DEVICE_NAME_LENGTH 32
26 #define ADF_ETR_MAX_RINGS_PER_BANK 16
27 #define ADF_MAX_MSIX_VECTOR_NAME 16
28 #define ADF_DEVICE_NAME_PREFIX "qat_"
29
30 enum adf_accel_capabilities {
31 ADF_ACCEL_CAPABILITIES_NULL = 0,
32 ADF_ACCEL_CAPABILITIES_CRYPTO_SYMMETRIC = 1,
33 ADF_ACCEL_CAPABILITIES_CRYPTO_ASYMMETRIC = 2,
34 ADF_ACCEL_CAPABILITIES_CIPHER = 4,
35 ADF_ACCEL_CAPABILITIES_AUTHENTICATION = 8,
36 ADF_ACCEL_CAPABILITIES_COMPRESSION = 32,
37 ADF_ACCEL_CAPABILITIES_LZS_COMPRESSION = 64,
38 ADF_ACCEL_CAPABILITIES_RANDOM_NUMBER = 128
39 };
40
41 struct adf_bar {
42 resource_size_t base_addr;
43 void __iomem *virt_addr;
44 resource_size_t size;
45 };
46
47 struct adf_irq {
48 bool enabled;
49 char name[ADF_MAX_MSIX_VECTOR_NAME];
50 };
51
52 struct adf_accel_msix {
53 struct adf_irq *irqs;
54 u32 num_entries;
55 };
56
57 struct adf_accel_pci {
58 struct pci_dev *pci_dev;
59 struct adf_accel_msix msix_entries;
60 struct adf_bar pci_bars[ADF_PCI_MAX_BARS];
61 u8 revid;
62 u8 sku;
63 };
64
65 enum dev_state {
66 DEV_DOWN = 0,
67 DEV_UP
68 };
69
70 enum dev_sku_info {
71 DEV_SKU_1 = 0,
72 DEV_SKU_2,
73 DEV_SKU_3,
74 DEV_SKU_4,
75 DEV_SKU_VF,
76 DEV_SKU_UNKNOWN,
77 };
78
get_sku_info(enum dev_sku_info info)79 static inline const char *get_sku_info(enum dev_sku_info info)
80 {
81 switch (info) {
82 case DEV_SKU_1:
83 return "SKU1";
84 case DEV_SKU_2:
85 return "SKU2";
86 case DEV_SKU_3:
87 return "SKU3";
88 case DEV_SKU_4:
89 return "SKU4";
90 case DEV_SKU_VF:
91 return "SKUVF";
92 case DEV_SKU_UNKNOWN:
93 default:
94 break;
95 }
96 return "Unknown SKU";
97 }
98
99 struct adf_hw_device_class {
100 const char *name;
101 const enum adf_device_type type;
102 u32 instances;
103 };
104
105 struct arb_info {
106 u32 arb_cfg;
107 u32 arb_offset;
108 u32 wt2sam_offset;
109 };
110
111 struct admin_info {
112 u32 admin_msg_ur;
113 u32 admin_msg_lr;
114 u32 mailbox_offset;
115 };
116
117 struct adf_hw_csr_ops {
118 u64 (*build_csr_ring_base_addr)(dma_addr_t addr, u32 size);
119 u32 (*read_csr_ring_head)(void __iomem *csr_base_addr, u32 bank,
120 u32 ring);
121 void (*write_csr_ring_head)(void __iomem *csr_base_addr, u32 bank,
122 u32 ring, u32 value);
123 u32 (*read_csr_ring_tail)(void __iomem *csr_base_addr, u32 bank,
124 u32 ring);
125 void (*write_csr_ring_tail)(void __iomem *csr_base_addr, u32 bank,
126 u32 ring, u32 value);
127 u32 (*read_csr_e_stat)(void __iomem *csr_base_addr, u32 bank);
128 void (*write_csr_ring_config)(void __iomem *csr_base_addr, u32 bank,
129 u32 ring, u32 value);
130 void (*write_csr_ring_base)(void __iomem *csr_base_addr, u32 bank,
131 u32 ring, dma_addr_t addr);
132 void (*write_csr_int_flag)(void __iomem *csr_base_addr, u32 bank,
133 u32 value);
134 void (*write_csr_int_srcsel)(void __iomem *csr_base_addr, u32 bank);
135 void (*write_csr_int_col_en)(void __iomem *csr_base_addr, u32 bank,
136 u32 value);
137 void (*write_csr_int_col_ctl)(void __iomem *csr_base_addr, u32 bank,
138 u32 value);
139 void (*write_csr_int_flag_and_col)(void __iomem *csr_base_addr,
140 u32 bank, u32 value);
141 void (*write_csr_ring_srv_arb_en)(void __iomem *csr_base_addr, u32 bank,
142 u32 value);
143 };
144
145 struct adf_cfg_device_data;
146 struct adf_accel_dev;
147 struct adf_etr_data;
148 struct adf_etr_ring_data;
149
150 struct adf_hw_device_data {
151 struct adf_hw_device_class *dev_class;
152 u32 (*get_accel_mask)(struct adf_hw_device_data *self);
153 u32 (*get_ae_mask)(struct adf_hw_device_data *self);
154 u32 (*get_accel_cap)(struct adf_accel_dev *accel_dev);
155 u32 (*get_sram_bar_id)(struct adf_hw_device_data *self);
156 u32 (*get_misc_bar_id)(struct adf_hw_device_data *self);
157 u32 (*get_etr_bar_id)(struct adf_hw_device_data *self);
158 u32 (*get_num_aes)(struct adf_hw_device_data *self);
159 u32 (*get_num_accels)(struct adf_hw_device_data *self);
160 u32 (*get_pf2vf_offset)(u32 i);
161 void (*get_arb_info)(struct arb_info *arb_csrs_info);
162 void (*get_admin_info)(struct admin_info *admin_csrs_info);
163 enum dev_sku_info (*get_sku)(struct adf_hw_device_data *self);
164 int (*alloc_irq)(struct adf_accel_dev *accel_dev);
165 void (*free_irq)(struct adf_accel_dev *accel_dev);
166 void (*enable_error_correction)(struct adf_accel_dev *accel_dev);
167 int (*init_admin_comms)(struct adf_accel_dev *accel_dev);
168 void (*exit_admin_comms)(struct adf_accel_dev *accel_dev);
169 int (*send_admin_init)(struct adf_accel_dev *accel_dev);
170 int (*init_arb)(struct adf_accel_dev *accel_dev);
171 void (*exit_arb)(struct adf_accel_dev *accel_dev);
172 const u32 *(*get_arb_mapping)(void);
173 int (*init_device)(struct adf_accel_dev *accel_dev);
174 void (*disable_iov)(struct adf_accel_dev *accel_dev);
175 void (*configure_iov_threads)(struct adf_accel_dev *accel_dev,
176 bool enable);
177 void (*enable_ints)(struct adf_accel_dev *accel_dev);
178 void (*set_ssm_wdtimer)(struct adf_accel_dev *accel_dev);
179 int (*enable_pfvf_comms)(struct adf_accel_dev *accel_dev);
180 u32 (*get_vf2pf_sources)(void __iomem *pmisc_addr);
181 void (*enable_vf2pf_interrupts)(void __iomem *pmisc_bar_addr,
182 u32 vf_mask);
183 void (*disable_vf2pf_interrupts)(void __iomem *pmisc_bar_addr,
184 u32 vf_mask);
185 void (*reset_device)(struct adf_accel_dev *accel_dev);
186 void (*set_msix_rttable)(struct adf_accel_dev *accel_dev);
187 char *(*uof_get_name)(u32 obj_num);
188 u32 (*uof_get_num_objs)(void);
189 u32 (*uof_get_ae_mask)(u32 obj_num);
190 struct adf_hw_csr_ops csr_ops;
191 const char *fw_name;
192 const char *fw_mmp_name;
193 u32 fuses;
194 u32 straps;
195 u32 accel_capabilities_mask;
196 u32 instance_id;
197 u16 accel_mask;
198 u32 ae_mask;
199 u32 admin_ae_mask;
200 u16 tx_rings_mask;
201 u8 tx_rx_gap;
202 u8 num_banks;
203 u8 num_rings_per_bank;
204 u8 num_accel;
205 u8 num_logical_accel;
206 u8 num_engines;
207 u8 min_iov_compat_ver;
208 };
209
210 /* CSR write macro */
211 #define ADF_CSR_WR(csr_base, csr_offset, val) \
212 __raw_writel(val, csr_base + csr_offset)
213
214 /* CSR read macro */
215 #define ADF_CSR_RD(csr_base, csr_offset) __raw_readl(csr_base + csr_offset)
216
217 #define GET_DEV(accel_dev) ((accel_dev)->accel_pci_dev.pci_dev->dev)
218 #define GET_BARS(accel_dev) ((accel_dev)->accel_pci_dev.pci_bars)
219 #define GET_HW_DATA(accel_dev) (accel_dev->hw_device)
220 #define GET_MAX_BANKS(accel_dev) (GET_HW_DATA(accel_dev)->num_banks)
221 #define GET_NUM_RINGS_PER_BANK(accel_dev) \
222 GET_HW_DATA(accel_dev)->num_rings_per_bank
223 #define GET_MAX_ACCELENGINES(accel_dev) (GET_HW_DATA(accel_dev)->num_engines)
224 #define GET_CSR_OPS(accel_dev) (&(accel_dev)->hw_device->csr_ops)
225 #define accel_to_pci_dev(accel_ptr) accel_ptr->accel_pci_dev.pci_dev
226
227 struct adf_admin_comms;
228 struct icp_qat_fw_loader_handle;
229 struct adf_fw_loader_data {
230 struct icp_qat_fw_loader_handle *fw_loader;
231 const struct firmware *uof_fw;
232 const struct firmware *mmp_fw;
233 };
234
235 struct adf_accel_vf_info {
236 struct adf_accel_dev *accel_dev;
237 struct mutex pf2vf_lock; /* protect CSR access for PF2VF messages */
238 struct ratelimit_state vf2pf_ratelimit;
239 u32 vf_nr;
240 bool init;
241 };
242
243 struct adf_accel_dev {
244 struct adf_etr_data *transport;
245 struct adf_hw_device_data *hw_device;
246 struct adf_cfg_device_data *cfg;
247 struct adf_fw_loader_data *fw_loader;
248 struct adf_admin_comms *admin;
249 struct list_head crypto_list;
250 unsigned long status;
251 atomic_t ref_count;
252 struct dentry *debugfs_dir;
253 struct list_head list;
254 struct module *owner;
255 struct adf_accel_pci accel_pci_dev;
256 union {
257 struct {
258 /* protects VF2PF interrupts access */
259 spinlock_t vf2pf_ints_lock;
260 /* vf_info is non-zero when SR-IOV is init'ed */
261 struct adf_accel_vf_info *vf_info;
262 } pf;
263 struct {
264 bool irq_enabled;
265 char irq_name[ADF_MAX_MSIX_VECTOR_NAME];
266 struct tasklet_struct pf2vf_bh_tasklet;
267 struct mutex vf2pf_lock; /* protect CSR access */
268 struct completion iov_msg_completion;
269 u8 compatible;
270 u8 pf_version;
271 } vf;
272 };
273 bool is_vf;
274 u32 accel_id;
275 };
276 #endif
277