1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) Freescale Semiconductor, Inc. 2006.
4 * Author: Jason Jin<Jason.jin@freescale.com>
5 * Zhang Wei<wei.zhang@freescale.com>
6 *
7 * with the reference on libata and ahci drvier in kernel
8 *
9 * This driver provides a SCSI interface to SATA.
10 */
11 #include <common.h>
12 #include <blk.h>
13 #include <cpu_func.h>
14 #include <log.h>
15 #include <linux/bitops.h>
16 #include <linux/delay.h>
17
18 #include <command.h>
19 #include <dm.h>
20 #include <pci.h>
21 #include <asm/processor.h>
22 #include <linux/errno.h>
23 #include <asm/io.h>
24 #include <malloc.h>
25 #include <memalign.h>
26 #include <pci.h>
27 #include <scsi.h>
28 #include <libata.h>
29 #include <linux/ctype.h>
30 #include <ahci.h>
31 #include <dm/device-internal.h>
32 #include <dm/lists.h>
33
34 static int ata_io_flush(struct ahci_uc_priv *uc_priv, u8 port);
35
36 #ifndef CONFIG_DM_SCSI
37 struct ahci_uc_priv *probe_ent = NULL;
38 #endif
39
40 #define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0)
41
42 /*
43 * Some controllers limit number of blocks they can read/write at once.
44 * Contemporary SSD devices work much faster if the read/write size is aligned
45 * to a power of 2. Let's set default to 128 and allowing to be overwritten if
46 * needed.
47 */
48 #ifndef MAX_SATA_BLOCKS_READ_WRITE
49 #define MAX_SATA_BLOCKS_READ_WRITE 0x80
50 #endif
51
52 /* Maximum timeouts for each event */
53 #define WAIT_MS_SPINUP 20000
54 #define WAIT_MS_DATAIO 10000
55 #define WAIT_MS_FLUSH 5000
56 #define WAIT_MS_LINKUP 200
57
58 #define AHCI_CAP_S64A BIT(31)
59
ahci_port_base(void __iomem * base,u32 port)60 __weak void __iomem *ahci_port_base(void __iomem *base, u32 port)
61 {
62 return base + 0x100 + (port * 0x80);
63 }
64
65 #define msleep(a) udelay(a * 1000)
66
ahci_dcache_flush_range(unsigned long begin,unsigned long len)67 static void ahci_dcache_flush_range(unsigned long begin, unsigned long len)
68 {
69 const unsigned long start = begin;
70 const unsigned long end = start + len;
71
72 debug("%s: flush dcache: [%#lx, %#lx)\n", __func__, start, end);
73 flush_dcache_range(start, end);
74 }
75
76 /*
77 * SATA controller DMAs to physical RAM. Ensure data from the
78 * controller is invalidated from dcache; next access comes from
79 * physical RAM.
80 */
ahci_dcache_invalidate_range(unsigned long begin,unsigned long len)81 static void ahci_dcache_invalidate_range(unsigned long begin, unsigned long len)
82 {
83 const unsigned long start = begin;
84 const unsigned long end = start + len;
85
86 debug("%s: invalidate dcache: [%#lx, %#lx)\n", __func__, start, end);
87 invalidate_dcache_range(start, end);
88 }
89
90 /*
91 * Ensure data for SATA controller is flushed out of dcache and
92 * written to physical memory.
93 */
ahci_dcache_flush_sata_cmd(struct ahci_ioports * pp)94 static void ahci_dcache_flush_sata_cmd(struct ahci_ioports *pp)
95 {
96 ahci_dcache_flush_range((unsigned long)pp->cmd_slot,
97 AHCI_PORT_PRIV_DMA_SZ);
98 }
99
waiting_for_cmd_completed(void __iomem * offset,int timeout_msec,u32 sign)100 static int waiting_for_cmd_completed(void __iomem *offset,
101 int timeout_msec,
102 u32 sign)
103 {
104 int i;
105 u32 status;
106
107 for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++)
108 msleep(1);
109
110 return (i < timeout_msec) ? 0 : -1;
111 }
112
ahci_link_up(struct ahci_uc_priv * uc_priv,u8 port)113 int __weak ahci_link_up(struct ahci_uc_priv *uc_priv, u8 port)
114 {
115 u32 tmp;
116 int j = 0;
117 void __iomem *port_mmio = uc_priv->port[port].port_mmio;
118
119 /*
120 * Bring up SATA link.
121 * SATA link bringup time is usually less than 1 ms; only very
122 * rarely has it taken between 1-2 ms. Never seen it above 2 ms.
123 */
124 while (j < WAIT_MS_LINKUP) {
125 tmp = readl(port_mmio + PORT_SCR_STAT);
126 tmp &= PORT_SCR_STAT_DET_MASK;
127 if (tmp == PORT_SCR_STAT_DET_PHYRDY)
128 return 0;
129 udelay(1000);
130 j++;
131 }
132 return 1;
133 }
134
135 #ifdef CONFIG_SUNXI_AHCI
136 /* The sunxi AHCI controller requires this undocumented setup */
sunxi_dma_init(void __iomem * port_mmio)137 static void sunxi_dma_init(void __iomem *port_mmio)
138 {
139 clrsetbits_le32(port_mmio + PORT_P0DMACR, 0x0000ff00, 0x00004400);
140 }
141 #endif
142
ahci_reset(void __iomem * base)143 int ahci_reset(void __iomem *base)
144 {
145 int i = 1000;
146 u32 __iomem *host_ctl_reg = base + HOST_CTL;
147 u32 tmp = readl(host_ctl_reg); /* global controller reset */
148
149 if ((tmp & HOST_RESET) == 0)
150 writel_with_flush(tmp | HOST_RESET, host_ctl_reg);
151
152 /*
153 * reset must complete within 1 second, or
154 * the hardware should be considered fried.
155 */
156 do {
157 udelay(1000);
158 tmp = readl(host_ctl_reg);
159 i--;
160 } while ((i > 0) && (tmp & HOST_RESET));
161
162 if (i == 0) {
163 printf("controller reset failed (0x%x)\n", tmp);
164 return -1;
165 }
166
167 return 0;
168 }
169
ahci_host_init(struct ahci_uc_priv * uc_priv)170 static int ahci_host_init(struct ahci_uc_priv *uc_priv)
171 {
172 #if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
173 # ifdef CONFIG_DM_PCI
174 struct udevice *dev = uc_priv->dev;
175 struct pci_child_plat *pplat = dev_get_parent_plat(dev);
176 # else
177 pci_dev_t pdev = uc_priv->dev;
178 unsigned short vendor;
179 # endif
180 u16 tmp16;
181 #endif
182 void __iomem *mmio = uc_priv->mmio_base;
183 u32 tmp, cap_save, cmd;
184 int i, j, ret;
185 void __iomem *port_mmio;
186 u32 port_map;
187
188 debug("ahci_host_init: start\n");
189
190 cap_save = readl(mmio + HOST_CAP);
191 cap_save &= ((1 << 28) | (1 << 17));
192 cap_save |= (1 << 27); /* Staggered Spin-up. Not needed. */
193
194 ret = ahci_reset(uc_priv->mmio_base);
195 if (ret)
196 return ret;
197
198 writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL);
199 writel(cap_save, mmio + HOST_CAP);
200 writel_with_flush(0xf, mmio + HOST_PORTS_IMPL);
201
202 #if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
203 # ifdef CONFIG_DM_PCI
204 if (pplat->vendor == PCI_VENDOR_ID_INTEL) {
205 u16 tmp16;
206
207 dm_pci_read_config16(dev, 0x92, &tmp16);
208 dm_pci_write_config16(dev, 0x92, tmp16 | 0xf);
209 }
210 # else
211 pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
212
213 if (vendor == PCI_VENDOR_ID_INTEL) {
214 u16 tmp16;
215 pci_read_config_word(pdev, 0x92, &tmp16);
216 tmp16 |= 0xf;
217 pci_write_config_word(pdev, 0x92, tmp16);
218 }
219 # endif
220 #endif
221 uc_priv->cap = readl(mmio + HOST_CAP);
222 uc_priv->port_map = readl(mmio + HOST_PORTS_IMPL);
223 port_map = uc_priv->port_map;
224 uc_priv->n_ports = (uc_priv->cap & 0x1f) + 1;
225
226 debug("cap 0x%x port_map 0x%x n_ports %d\n",
227 uc_priv->cap, uc_priv->port_map, uc_priv->n_ports);
228
229 #if !defined(CONFIG_DM_SCSI)
230 if (uc_priv->n_ports > CONFIG_SYS_SCSI_MAX_SCSI_ID)
231 uc_priv->n_ports = CONFIG_SYS_SCSI_MAX_SCSI_ID;
232 #endif
233
234 for (i = 0; i < uc_priv->n_ports; i++) {
235 if (!(port_map & (1 << i)))
236 continue;
237 uc_priv->port[i].port_mmio = ahci_port_base(mmio, i);
238 port_mmio = (u8 *)uc_priv->port[i].port_mmio;
239
240 /* make sure port is not active */
241 tmp = readl(port_mmio + PORT_CMD);
242 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
243 PORT_CMD_FIS_RX | PORT_CMD_START)) {
244 debug("Port %d is active. Deactivating.\n", i);
245 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
246 PORT_CMD_FIS_RX | PORT_CMD_START);
247 writel_with_flush(tmp, port_mmio + PORT_CMD);
248
249 /* spec says 500 msecs for each bit, so
250 * this is slightly incorrect.
251 */
252 msleep(500);
253 }
254
255 #ifdef CONFIG_SUNXI_AHCI
256 sunxi_dma_init(port_mmio);
257 #endif
258
259 /* Add the spinup command to whatever mode bits may
260 * already be on in the command register.
261 */
262 cmd = readl(port_mmio + PORT_CMD);
263 cmd |= PORT_CMD_SPIN_UP;
264 writel_with_flush(cmd, port_mmio + PORT_CMD);
265
266 /* Bring up SATA link. */
267 ret = ahci_link_up(uc_priv, i);
268 if (ret) {
269 printf("SATA link %d timeout.\n", i);
270 continue;
271 } else {
272 debug("SATA link ok.\n");
273 }
274
275 /* Clear error status */
276 tmp = readl(port_mmio + PORT_SCR_ERR);
277 if (tmp)
278 writel(tmp, port_mmio + PORT_SCR_ERR);
279
280 debug("Spinning up device on SATA port %d... ", i);
281
282 j = 0;
283 while (j < WAIT_MS_SPINUP) {
284 tmp = readl(port_mmio + PORT_TFDATA);
285 if (!(tmp & (ATA_BUSY | ATA_DRQ)))
286 break;
287 udelay(1000);
288 tmp = readl(port_mmio + PORT_SCR_STAT);
289 tmp &= PORT_SCR_STAT_DET_MASK;
290 if (tmp == PORT_SCR_STAT_DET_PHYRDY)
291 break;
292 j++;
293 }
294
295 tmp = readl(port_mmio + PORT_SCR_STAT) & PORT_SCR_STAT_DET_MASK;
296 if (tmp == PORT_SCR_STAT_DET_COMINIT) {
297 debug("SATA link %d down (COMINIT received), retrying...\n", i);
298 i--;
299 continue;
300 }
301
302 printf("Target spinup took %d ms.\n", j);
303 if (j == WAIT_MS_SPINUP)
304 debug("timeout.\n");
305 else
306 debug("ok.\n");
307
308 tmp = readl(port_mmio + PORT_SCR_ERR);
309 debug("PORT_SCR_ERR 0x%x\n", tmp);
310 writel(tmp, port_mmio + PORT_SCR_ERR);
311
312 /* ack any pending irq events for this port */
313 tmp = readl(port_mmio + PORT_IRQ_STAT);
314 debug("PORT_IRQ_STAT 0x%x\n", tmp);
315 if (tmp)
316 writel(tmp, port_mmio + PORT_IRQ_STAT);
317
318 writel(1 << i, mmio + HOST_IRQ_STAT);
319
320 /* register linkup ports */
321 tmp = readl(port_mmio + PORT_SCR_STAT);
322 debug("SATA port %d status: 0x%x\n", i, tmp);
323 if ((tmp & PORT_SCR_STAT_DET_MASK) == PORT_SCR_STAT_DET_PHYRDY)
324 uc_priv->link_port_map |= (0x01 << i);
325 }
326
327 tmp = readl(mmio + HOST_CTL);
328 debug("HOST_CTL 0x%x\n", tmp);
329 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
330 tmp = readl(mmio + HOST_CTL);
331 debug("HOST_CTL 0x%x\n", tmp);
332 #if !defined(CONFIG_DM_SCSI)
333 #ifndef CONFIG_SCSI_AHCI_PLAT
334 # ifdef CONFIG_DM_PCI
335 dm_pci_read_config16(dev, PCI_COMMAND, &tmp16);
336 tmp |= PCI_COMMAND_MASTER;
337 dm_pci_write_config16(dev, PCI_COMMAND, tmp16);
338 # else
339 pci_read_config_word(pdev, PCI_COMMAND, &tmp16);
340 tmp |= PCI_COMMAND_MASTER;
341 pci_write_config_word(pdev, PCI_COMMAND, tmp16);
342 # endif
343 #endif
344 #endif
345 return 0;
346 }
347
348
ahci_print_info(struct ahci_uc_priv * uc_priv)349 static void ahci_print_info(struct ahci_uc_priv *uc_priv)
350 {
351 #if !defined(CONFIG_SCSI_AHCI_PLAT) && !defined(CONFIG_DM_SCSI)
352 # if defined(CONFIG_DM_PCI)
353 struct udevice *dev = uc_priv->dev;
354 # else
355 pci_dev_t pdev = uc_priv->dev;
356 # endif
357 u16 cc;
358 #endif
359 void __iomem *mmio = uc_priv->mmio_base;
360 u32 vers, cap, cap2, impl, speed;
361 const char *speed_s;
362 const char *scc_s;
363
364 vers = readl(mmio + HOST_VERSION);
365 cap = uc_priv->cap;
366 cap2 = readl(mmio + HOST_CAP2);
367 impl = uc_priv->port_map;
368
369 speed = (cap >> 20) & 0xf;
370 if (speed == 1)
371 speed_s = "1.5";
372 else if (speed == 2)
373 speed_s = "3";
374 else if (speed == 3)
375 speed_s = "6";
376 else
377 speed_s = "?";
378
379 #if defined(CONFIG_SCSI_AHCI_PLAT) || defined(CONFIG_DM_SCSI)
380 scc_s = "SATA";
381 #else
382 # ifdef CONFIG_DM_PCI
383 dm_pci_read_config16(dev, 0x0a, &cc);
384 # else
385 pci_read_config_word(pdev, 0x0a, &cc);
386 # endif
387 if (cc == 0x0101)
388 scc_s = "IDE";
389 else if (cc == 0x0106)
390 scc_s = "SATA";
391 else if (cc == 0x0104)
392 scc_s = "RAID";
393 else
394 scc_s = "unknown";
395 #endif
396 printf("AHCI %02x%02x.%02x%02x "
397 "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
398 (vers >> 24) & 0xff,
399 (vers >> 16) & 0xff,
400 (vers >> 8) & 0xff,
401 vers & 0xff,
402 ((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s);
403
404 printf("flags: "
405 "%s%s%s%s%s%s%s"
406 "%s%s%s%s%s%s%s"
407 "%s%s%s%s%s%s\n",
408 cap & (1 << 31) ? "64bit " : "",
409 cap & (1 << 30) ? "ncq " : "",
410 cap & (1 << 28) ? "ilck " : "",
411 cap & (1 << 27) ? "stag " : "",
412 cap & (1 << 26) ? "pm " : "",
413 cap & (1 << 25) ? "led " : "",
414 cap & (1 << 24) ? "clo " : "",
415 cap & (1 << 19) ? "nz " : "",
416 cap & (1 << 18) ? "only " : "",
417 cap & (1 << 17) ? "pmp " : "",
418 cap & (1 << 16) ? "fbss " : "",
419 cap & (1 << 15) ? "pio " : "",
420 cap & (1 << 14) ? "slum " : "",
421 cap & (1 << 13) ? "part " : "",
422 cap & (1 << 7) ? "ccc " : "",
423 cap & (1 << 6) ? "ems " : "",
424 cap & (1 << 5) ? "sxs " : "",
425 cap2 & (1 << 2) ? "apst " : "",
426 cap2 & (1 << 1) ? "nvmp " : "",
427 cap2 & (1 << 0) ? "boh " : "");
428 }
429
430 #if defined(CONFIG_DM_SCSI) || !defined(CONFIG_SCSI_AHCI_PLAT)
431 # if defined(CONFIG_DM_PCI) || defined(CONFIG_DM_SCSI)
ahci_init_one(struct ahci_uc_priv * uc_priv,struct udevice * dev)432 static int ahci_init_one(struct ahci_uc_priv *uc_priv, struct udevice *dev)
433 # else
434 static int ahci_init_one(struct ahci_uc_priv *uc_priv, pci_dev_t dev)
435 # endif
436 {
437 #if !defined(CONFIG_DM_SCSI)
438 u16 vendor;
439 #endif
440 int rc;
441
442 uc_priv->dev = dev;
443
444 uc_priv->host_flags = ATA_FLAG_SATA
445 | ATA_FLAG_NO_LEGACY
446 | ATA_FLAG_MMIO
447 | ATA_FLAG_PIO_DMA
448 | ATA_FLAG_NO_ATAPI;
449 uc_priv->pio_mask = 0x1f;
450 uc_priv->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
451
452 #if !defined(CONFIG_DM_SCSI)
453 #ifdef CONFIG_DM_PCI
454 uc_priv->mmio_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_5,
455 PCI_REGION_MEM);
456
457 /* Take from kernel:
458 * JMicron-specific fixup:
459 * make sure we're in AHCI mode
460 */
461 dm_pci_read_config16(dev, PCI_VENDOR_ID, &vendor);
462 if (vendor == 0x197b)
463 dm_pci_write_config8(dev, 0x41, 0xa1);
464 #else
465 uc_priv->mmio_base = pci_map_bar(dev, PCI_BASE_ADDRESS_5,
466 PCI_REGION_MEM);
467
468 /* Take from kernel:
469 * JMicron-specific fixup:
470 * make sure we're in AHCI mode
471 */
472 pci_read_config_word(dev, PCI_VENDOR_ID, &vendor);
473 if (vendor == 0x197b)
474 pci_write_config_byte(dev, 0x41, 0xa1);
475 #endif
476 #else
477 struct scsi_plat *plat = dev_get_uclass_plat(dev);
478 uc_priv->mmio_base = (void *)plat->base;
479 #endif
480
481 debug("ahci mmio_base=0x%p\n", uc_priv->mmio_base);
482 /* initialize adapter */
483 rc = ahci_host_init(uc_priv);
484 if (rc)
485 goto err_out;
486
487 ahci_print_info(uc_priv);
488
489 return 0;
490
491 err_out:
492 return rc;
493 }
494 #endif
495
496 #define MAX_DATA_BYTE_COUNT (4*1024*1024)
497
ahci_fill_sg(struct ahci_uc_priv * uc_priv,u8 port,unsigned char * buf,int buf_len)498 static int ahci_fill_sg(struct ahci_uc_priv *uc_priv, u8 port,
499 unsigned char *buf, int buf_len)
500 {
501 struct ahci_ioports *pp = &(uc_priv->port[port]);
502 struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
503 u32 sg_count;
504 int i;
505
506 sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1;
507 if (sg_count > AHCI_MAX_SG) {
508 printf("Error:Too much sg!\n");
509 return -1;
510 }
511
512 for (i = 0; i < sg_count; i++) {
513 /* We assume virt=phys */
514 phys_addr_t pa = (unsigned long)buf + i * MAX_DATA_BYTE_COUNT;
515
516 ahci_sg->addr = cpu_to_le32(lower_32_bits(pa));
517 ahci_sg->addr_hi = cpu_to_le32(upper_32_bits(pa));
518 if (ahci_sg->addr_hi && !(uc_priv->cap & AHCI_CAP_S64A)) {
519 printf("Error: DMA address too high\n");
520 return -1;
521 }
522 ahci_sg->flags_size = cpu_to_le32(0x3fffff &
523 (buf_len < MAX_DATA_BYTE_COUNT
524 ? (buf_len - 1)
525 : (MAX_DATA_BYTE_COUNT - 1)));
526 ahci_sg++;
527 buf_len -= MAX_DATA_BYTE_COUNT;
528 }
529
530 return sg_count;
531 }
532
533
ahci_fill_cmd_slot(struct ahci_ioports * pp,u32 opts)534 static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts)
535 {
536 pp->cmd_slot->opts = cpu_to_le32(opts);
537 pp->cmd_slot->status = 0;
538 pp->cmd_slot->tbl_addr = cpu_to_le32((u32)pp->cmd_tbl & 0xffffffff);
539 #ifdef CONFIG_PHYS_64BIT
540 pp->cmd_slot->tbl_addr_hi =
541 cpu_to_le32((u32)(((pp->cmd_tbl) >> 16) >> 16));
542 #endif
543 }
544
wait_spinup(void __iomem * port_mmio)545 static int wait_spinup(void __iomem *port_mmio)
546 {
547 ulong start;
548 u32 tf_data;
549
550 start = get_timer(0);
551 do {
552 tf_data = readl(port_mmio + PORT_TFDATA);
553 if (!(tf_data & ATA_BUSY))
554 return 0;
555 } while (get_timer(start) < WAIT_MS_SPINUP);
556
557 return -ETIMEDOUT;
558 }
559
ahci_port_start(struct ahci_uc_priv * uc_priv,u8 port)560 static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port)
561 {
562 struct ahci_ioports *pp = &(uc_priv->port[port]);
563 void __iomem *port_mmio = pp->port_mmio;
564 u64 dma_addr;
565 u32 port_status;
566 void __iomem *mem;
567
568 debug("Enter start port: %d\n", port);
569 port_status = readl(port_mmio + PORT_SCR_STAT);
570 debug("Port %d status: %x\n", port, port_status);
571 if ((port_status & 0xf) != 0x03) {
572 printf("No Link on this port!\n");
573 return -1;
574 }
575
576 mem = memalign(2048, AHCI_PORT_PRIV_DMA_SZ);
577 if (!mem) {
578 free(pp);
579 printf("%s: No mem for table!\n", __func__);
580 return -ENOMEM;
581 }
582 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
583
584 /*
585 * First item in chunk of DMA memory: 32-slot command table,
586 * 32 bytes each in size
587 */
588 pp->cmd_slot =
589 (struct ahci_cmd_hdr *)(uintptr_t)virt_to_phys((void *)mem);
590 debug("cmd_slot = %p\n", pp->cmd_slot);
591 mem += (AHCI_CMD_SLOT_SZ + 224);
592
593 /*
594 * Second item: Received-FIS area
595 */
596 pp->rx_fis = virt_to_phys((void *)mem);
597 mem += AHCI_RX_FIS_SZ;
598
599 /*
600 * Third item: data area for storing a single command
601 * and its scatter-gather table
602 */
603 pp->cmd_tbl = virt_to_phys((void *)mem);
604 debug("cmd_tbl_dma = %lx\n", pp->cmd_tbl);
605
606 mem += AHCI_CMD_TBL_HDR;
607 pp->cmd_tbl_sg =
608 (struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem);
609
610 dma_addr = (ulong)pp->cmd_slot;
611 writel_with_flush(dma_addr, port_mmio + PORT_LST_ADDR);
612 writel_with_flush(dma_addr >> 32, port_mmio + PORT_LST_ADDR_HI);
613 dma_addr = (ulong)pp->rx_fis;
614 writel_with_flush(dma_addr, port_mmio + PORT_FIS_ADDR);
615 writel_with_flush(dma_addr >> 32, port_mmio + PORT_FIS_ADDR_HI);
616
617 #ifdef CONFIG_SUNXI_AHCI
618 sunxi_dma_init(port_mmio);
619 #endif
620
621 writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
622 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
623 PORT_CMD_START, port_mmio + PORT_CMD);
624
625 debug("Exit start port %d\n", port);
626
627 /*
628 * Make sure interface is not busy based on error and status
629 * information from task file data register before proceeding
630 */
631 return wait_spinup(port_mmio);
632 }
633
634
ahci_device_data_io(struct ahci_uc_priv * uc_priv,u8 port,u8 * fis,int fis_len,u8 * buf,int buf_len,u8 is_write)635 static int ahci_device_data_io(struct ahci_uc_priv *uc_priv, u8 port, u8 *fis,
636 int fis_len, u8 *buf, int buf_len, u8 is_write)
637 {
638
639 struct ahci_ioports *pp = &(uc_priv->port[port]);
640 void __iomem *port_mmio = pp->port_mmio;
641 u32 opts;
642 u32 port_status;
643 int sg_count;
644
645 debug("Enter %s: for port %d\n", __func__, port);
646
647 if (port > uc_priv->n_ports) {
648 printf("Invalid port number %d\n", port);
649 return -1;
650 }
651
652 port_status = readl(port_mmio + PORT_SCR_STAT);
653 if ((port_status & 0xf) != 0x03) {
654 debug("No Link on port %d!\n", port);
655 return -1;
656 }
657
658 memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len);
659
660 sg_count = ahci_fill_sg(uc_priv, port, buf, buf_len);
661 opts = (fis_len >> 2) | (sg_count << 16) | (is_write << 6);
662 ahci_fill_cmd_slot(pp, opts);
663
664 ahci_dcache_flush_sata_cmd(pp);
665 ahci_dcache_flush_range((unsigned long)buf, (unsigned long)buf_len);
666
667 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
668
669 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
670 WAIT_MS_DATAIO, 0x1)) {
671 printf("timeout exit!\n");
672 return -1;
673 }
674
675 ahci_dcache_invalidate_range((unsigned long)buf,
676 (unsigned long)buf_len);
677 debug("%s: %d byte transferred.\n", __func__, pp->cmd_slot->status);
678
679 return 0;
680 }
681
682
ata_id_strcpy(u16 * target,u16 * src,int len)683 static char *ata_id_strcpy(u16 *target, u16 *src, int len)
684 {
685 int i;
686 for (i = 0; i < len / 2; i++)
687 target[i] = swab16(src[i]);
688 return (char *)target;
689 }
690
691 /*
692 * SCSI INQUIRY command operation.
693 */
ata_scsiop_inquiry(struct ahci_uc_priv * uc_priv,struct scsi_cmd * pccb)694 static int ata_scsiop_inquiry(struct ahci_uc_priv *uc_priv,
695 struct scsi_cmd *pccb)
696 {
697 static const u8 hdr[] = {
698 0,
699 0,
700 0x5, /* claim SPC-3 version compatibility */
701 2,
702 95 - 4,
703 };
704 u8 fis[20];
705 u16 *idbuf;
706 ALLOC_CACHE_ALIGN_BUFFER(u16, tmpid, ATA_ID_WORDS);
707 u8 port;
708
709 /* Clean ccb data buffer */
710 memset(pccb->pdata, 0, pccb->datalen);
711
712 memcpy(pccb->pdata, hdr, sizeof(hdr));
713
714 if (pccb->datalen <= 35)
715 return 0;
716
717 memset(fis, 0, sizeof(fis));
718 /* Construct the FIS */
719 fis[0] = 0x27; /* Host to device FIS. */
720 fis[1] = 1 << 7; /* Command FIS. */
721 fis[2] = ATA_CMD_ID_ATA; /* Command byte. */
722
723 /* Read id from sata */
724 port = pccb->target;
725
726 if (ahci_device_data_io(uc_priv, port, (u8 *)&fis, sizeof(fis),
727 (u8 *)tmpid, ATA_ID_WORDS * 2, 0)) {
728 debug("scsi_ahci: SCSI inquiry command failure.\n");
729 return -EIO;
730 }
731
732 if (!uc_priv->ataid[port]) {
733 uc_priv->ataid[port] = malloc(ATA_ID_WORDS * 2);
734 if (!uc_priv->ataid[port]) {
735 printf("%s: No memory for ataid[port]\n", __func__);
736 return -ENOMEM;
737 }
738 }
739
740 idbuf = uc_priv->ataid[port];
741
742 memcpy(idbuf, tmpid, ATA_ID_WORDS * 2);
743 ata_swap_buf_le16(idbuf, ATA_ID_WORDS);
744
745 memcpy(&pccb->pdata[8], "ATA ", 8);
746 ata_id_strcpy((u16 *)&pccb->pdata[16], &idbuf[ATA_ID_PROD], 16);
747 ata_id_strcpy((u16 *)&pccb->pdata[32], &idbuf[ATA_ID_FW_REV], 4);
748
749 #ifdef DEBUG
750 ata_dump_id(idbuf);
751 #endif
752 return 0;
753 }
754
755
756 /*
757 * SCSI READ10/WRITE10 command operation.
758 */
ata_scsiop_read_write(struct ahci_uc_priv * uc_priv,struct scsi_cmd * pccb,u8 is_write)759 static int ata_scsiop_read_write(struct ahci_uc_priv *uc_priv,
760 struct scsi_cmd *pccb, u8 is_write)
761 {
762 lbaint_t lba = 0;
763 u16 blocks = 0;
764 u8 fis[20];
765 u8 *user_buffer = pccb->pdata;
766 u32 user_buffer_size = pccb->datalen;
767
768 /* Retrieve the base LBA number from the ccb structure. */
769 if (pccb->cmd[0] == SCSI_READ16) {
770 memcpy(&lba, pccb->cmd + 2, 8);
771 lba = be64_to_cpu(lba);
772 } else {
773 u32 temp;
774 memcpy(&temp, pccb->cmd + 2, 4);
775 lba = be32_to_cpu(temp);
776 }
777
778 /*
779 * Retrieve the base LBA number and the block count from
780 * the ccb structure.
781 *
782 * For 10-byte and 16-byte SCSI R/W commands, transfer
783 * length 0 means transfer 0 block of data.
784 * However, for ATA R/W commands, sector count 0 means
785 * 256 or 65536 sectors, not 0 sectors as in SCSI.
786 *
787 * WARNING: one or two older ATA drives treat 0 as 0...
788 */
789 if (pccb->cmd[0] == SCSI_READ16)
790 blocks = (((u16)pccb->cmd[13]) << 8) | ((u16) pccb->cmd[14]);
791 else
792 blocks = (((u16)pccb->cmd[7]) << 8) | ((u16) pccb->cmd[8]);
793
794 debug("scsi_ahci: %s %u blocks starting from lba 0x" LBAFU "\n",
795 is_write ? "write" : "read", blocks, lba);
796
797 /* Preset the FIS */
798 memset(fis, 0, sizeof(fis));
799 fis[0] = 0x27; /* Host to device FIS. */
800 fis[1] = 1 << 7; /* Command FIS. */
801 /* Command byte (read/write). */
802 fis[2] = is_write ? ATA_CMD_WRITE_EXT : ATA_CMD_READ_EXT;
803
804 while (blocks) {
805 u16 now_blocks; /* number of blocks per iteration */
806 u32 transfer_size; /* number of bytes per iteration */
807
808 now_blocks = min((u16)MAX_SATA_BLOCKS_READ_WRITE, blocks);
809
810 transfer_size = ATA_SECT_SIZE * now_blocks;
811 if (transfer_size > user_buffer_size) {
812 printf("scsi_ahci: Error: buffer too small.\n");
813 return -EIO;
814 }
815
816 /*
817 * LBA48 SATA command but only use 32bit address range within
818 * that (unless we've enabled 64bit LBA support). The next
819 * smaller command range (28bit) is too small.
820 */
821 fis[4] = (lba >> 0) & 0xff;
822 fis[5] = (lba >> 8) & 0xff;
823 fis[6] = (lba >> 16) & 0xff;
824 fis[7] = 1 << 6; /* device reg: set LBA mode */
825 fis[8] = ((lba >> 24) & 0xff);
826 #ifdef CONFIG_SYS_64BIT_LBA
827 if (pccb->cmd[0] == SCSI_READ16) {
828 fis[9] = ((lba >> 32) & 0xff);
829 fis[10] = ((lba >> 40) & 0xff);
830 }
831 #endif
832
833 fis[3] = 0xe0; /* features */
834
835 /* Block (sector) count */
836 fis[12] = (now_blocks >> 0) & 0xff;
837 fis[13] = (now_blocks >> 8) & 0xff;
838
839 /* Read/Write from ahci */
840 if (ahci_device_data_io(uc_priv, pccb->target, (u8 *)&fis,
841 sizeof(fis), user_buffer, transfer_size,
842 is_write)) {
843 debug("scsi_ahci: SCSI %s10 command failure.\n",
844 is_write ? "WRITE" : "READ");
845 return -EIO;
846 }
847
848 /* If this transaction is a write, do a following flush.
849 * Writes in u-boot are so rare, and the logic to know when is
850 * the last write and do a flush only there is sufficiently
851 * difficult. Just do a flush after every write. This incurs,
852 * usually, one extra flush when the rare writes do happen.
853 */
854 if (is_write) {
855 if (-EIO == ata_io_flush(uc_priv, pccb->target))
856 return -EIO;
857 }
858 user_buffer += transfer_size;
859 user_buffer_size -= transfer_size;
860 blocks -= now_blocks;
861 lba += now_blocks;
862 }
863
864 return 0;
865 }
866
867
868 /*
869 * SCSI READ CAPACITY10 command operation.
870 */
ata_scsiop_read_capacity10(struct ahci_uc_priv * uc_priv,struct scsi_cmd * pccb)871 static int ata_scsiop_read_capacity10(struct ahci_uc_priv *uc_priv,
872 struct scsi_cmd *pccb)
873 {
874 u32 cap;
875 u64 cap64;
876 u32 block_size;
877
878 if (!uc_priv->ataid[pccb->target]) {
879 printf("scsi_ahci: SCSI READ CAPACITY10 command failure. "
880 "\tNo ATA info!\n"
881 "\tPlease run SCSI command INQUIRY first!\n");
882 return -EPERM;
883 }
884
885 cap64 = ata_id_n_sectors(uc_priv->ataid[pccb->target]);
886 if (cap64 > 0x100000000ULL)
887 cap64 = 0xffffffff;
888
889 cap = cpu_to_be32(cap64);
890 memcpy(pccb->pdata, &cap, sizeof(cap));
891
892 block_size = cpu_to_be32((u32)512);
893 memcpy(&pccb->pdata[4], &block_size, 4);
894
895 return 0;
896 }
897
898
899 /*
900 * SCSI READ CAPACITY16 command operation.
901 */
ata_scsiop_read_capacity16(struct ahci_uc_priv * uc_priv,struct scsi_cmd * pccb)902 static int ata_scsiop_read_capacity16(struct ahci_uc_priv *uc_priv,
903 struct scsi_cmd *pccb)
904 {
905 u64 cap;
906 u64 block_size;
907
908 if (!uc_priv->ataid[pccb->target]) {
909 printf("scsi_ahci: SCSI READ CAPACITY16 command failure. "
910 "\tNo ATA info!\n"
911 "\tPlease run SCSI command INQUIRY first!\n");
912 return -EPERM;
913 }
914
915 cap = ata_id_n_sectors(uc_priv->ataid[pccb->target]);
916 cap = cpu_to_be64(cap);
917 memcpy(pccb->pdata, &cap, sizeof(cap));
918
919 block_size = cpu_to_be64((u64)512);
920 memcpy(&pccb->pdata[8], &block_size, 8);
921
922 return 0;
923 }
924
925
926 /*
927 * SCSI TEST UNIT READY command operation.
928 */
ata_scsiop_test_unit_ready(struct ahci_uc_priv * uc_priv,struct scsi_cmd * pccb)929 static int ata_scsiop_test_unit_ready(struct ahci_uc_priv *uc_priv,
930 struct scsi_cmd *pccb)
931 {
932 return (uc_priv->ataid[pccb->target]) ? 0 : -EPERM;
933 }
934
935
ahci_scsi_exec(struct udevice * dev,struct scsi_cmd * pccb)936 static int ahci_scsi_exec(struct udevice *dev, struct scsi_cmd *pccb)
937 {
938 struct ahci_uc_priv *uc_priv;
939 #ifdef CONFIG_DM_SCSI
940 uc_priv = dev_get_uclass_priv(dev->parent);
941 #else
942 uc_priv = probe_ent;
943 #endif
944 int ret;
945
946 switch (pccb->cmd[0]) {
947 case SCSI_READ16:
948 case SCSI_READ10:
949 ret = ata_scsiop_read_write(uc_priv, pccb, 0);
950 break;
951 case SCSI_WRITE10:
952 ret = ata_scsiop_read_write(uc_priv, pccb, 1);
953 break;
954 case SCSI_RD_CAPAC10:
955 ret = ata_scsiop_read_capacity10(uc_priv, pccb);
956 break;
957 case SCSI_RD_CAPAC16:
958 ret = ata_scsiop_read_capacity16(uc_priv, pccb);
959 break;
960 case SCSI_TST_U_RDY:
961 ret = ata_scsiop_test_unit_ready(uc_priv, pccb);
962 break;
963 case SCSI_INQUIRY:
964 ret = ata_scsiop_inquiry(uc_priv, pccb);
965 break;
966 default:
967 printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]);
968 return -ENOTSUPP;
969 }
970
971 if (ret) {
972 debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret);
973 return ret;
974 }
975 return 0;
976
977 }
978
ahci_start_ports(struct ahci_uc_priv * uc_priv)979 static int ahci_start_ports(struct ahci_uc_priv *uc_priv)
980 {
981 u32 linkmap;
982 int i;
983
984 linkmap = uc_priv->link_port_map;
985
986 for (i = 0; i < uc_priv->n_ports; i++) {
987 if (((linkmap >> i) & 0x01)) {
988 if (ahci_port_start(uc_priv, (u8) i)) {
989 printf("Can not start port %d\n", i);
990 continue;
991 }
992 }
993 }
994
995 return 0;
996 }
997
998 #ifndef CONFIG_DM_SCSI
scsi_low_level_init(int busdevfunc)999 void scsi_low_level_init(int busdevfunc)
1000 {
1001 struct ahci_uc_priv *uc_priv;
1002
1003 #ifndef CONFIG_SCSI_AHCI_PLAT
1004 probe_ent = calloc(1, sizeof(struct ahci_uc_priv));
1005 if (!probe_ent) {
1006 printf("%s: No memory for uc_priv\n", __func__);
1007 return;
1008 }
1009 uc_priv = probe_ent;
1010 # if defined(CONFIG_DM_PCI)
1011 struct udevice *dev;
1012 int ret;
1013
1014 ret = dm_pci_bus_find_bdf(busdevfunc, &dev);
1015 if (ret)
1016 return;
1017 ahci_init_one(uc_priv, dev);
1018 # else
1019 ahci_init_one(uc_priv, busdevfunc);
1020 # endif
1021 #else
1022 uc_priv = probe_ent;
1023 #endif
1024
1025 ahci_start_ports(uc_priv);
1026 }
1027 #endif
1028
1029 #ifndef CONFIG_SCSI_AHCI_PLAT
1030 # if defined(CONFIG_DM_PCI) || defined(CONFIG_DM_SCSI)
ahci_init_one_dm(struct udevice * dev)1031 int ahci_init_one_dm(struct udevice *dev)
1032 {
1033 struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
1034
1035 return ahci_init_one(uc_priv, dev);
1036 }
1037 #endif
1038 #endif
1039
ahci_start_ports_dm(struct udevice * dev)1040 int ahci_start_ports_dm(struct udevice *dev)
1041 {
1042 struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
1043
1044 return ahci_start_ports(uc_priv);
1045 }
1046
1047 #ifdef CONFIG_SCSI_AHCI_PLAT
ahci_init_common(struct ahci_uc_priv * uc_priv,void __iomem * base)1048 static int ahci_init_common(struct ahci_uc_priv *uc_priv, void __iomem *base)
1049 {
1050 int rc;
1051
1052 uc_priv->host_flags = ATA_FLAG_SATA
1053 | ATA_FLAG_NO_LEGACY
1054 | ATA_FLAG_MMIO
1055 | ATA_FLAG_PIO_DMA
1056 | ATA_FLAG_NO_ATAPI;
1057 uc_priv->pio_mask = 0x1f;
1058 uc_priv->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
1059
1060 uc_priv->mmio_base = base;
1061
1062 /* initialize adapter */
1063 rc = ahci_host_init(uc_priv);
1064 if (rc)
1065 goto err_out;
1066
1067 ahci_print_info(uc_priv);
1068
1069 rc = ahci_start_ports(uc_priv);
1070
1071 err_out:
1072 return rc;
1073 }
1074
1075 #ifndef CONFIG_DM_SCSI
ahci_init(void __iomem * base)1076 int ahci_init(void __iomem *base)
1077 {
1078 struct ahci_uc_priv *uc_priv;
1079
1080 probe_ent = malloc(sizeof(struct ahci_uc_priv));
1081 if (!probe_ent) {
1082 printf("%s: No memory for uc_priv\n", __func__);
1083 return -ENOMEM;
1084 }
1085
1086 uc_priv = probe_ent;
1087 memset(uc_priv, 0, sizeof(struct ahci_uc_priv));
1088
1089 return ahci_init_common(uc_priv, base);
1090 }
1091 #endif
1092
ahci_init_dm(struct udevice * dev,void __iomem * base)1093 int ahci_init_dm(struct udevice *dev, void __iomem *base)
1094 {
1095 struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
1096
1097 return ahci_init_common(uc_priv, base);
1098 }
1099
scsi_init(void)1100 void __weak scsi_init(void)
1101 {
1102 }
1103
1104 #endif /* CONFIG_SCSI_AHCI_PLAT */
1105
1106 /*
1107 * In the general case of generic rotating media it makes sense to have a
1108 * flush capability. It probably even makes sense in the case of SSDs because
1109 * one cannot always know for sure what kind of internal cache/flush mechanism
1110 * is embodied therein. At first it was planned to invoke this after the last
1111 * write to disk and before rebooting. In practice, knowing, a priori, which
1112 * is the last write is difficult. Because writing to the disk in u-boot is
1113 * very rare, this flush command will be invoked after every block write.
1114 */
ata_io_flush(struct ahci_uc_priv * uc_priv,u8 port)1115 static int ata_io_flush(struct ahci_uc_priv *uc_priv, u8 port)
1116 {
1117 u8 fis[20];
1118 struct ahci_ioports *pp = &(uc_priv->port[port]);
1119 void __iomem *port_mmio = pp->port_mmio;
1120 u32 cmd_fis_len = 5; /* five dwords */
1121
1122 /* Preset the FIS */
1123 memset(fis, 0, 20);
1124 fis[0] = 0x27; /* Host to device FIS. */
1125 fis[1] = 1 << 7; /* Command FIS. */
1126 fis[2] = ATA_CMD_FLUSH_EXT;
1127
1128 memcpy((unsigned char *)pp->cmd_tbl, fis, 20);
1129 ahci_fill_cmd_slot(pp, cmd_fis_len);
1130 ahci_dcache_flush_sata_cmd(pp);
1131 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
1132
1133 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
1134 WAIT_MS_FLUSH, 0x1)) {
1135 debug("scsi_ahci: flush command timeout on port %d.\n", port);
1136 return -EIO;
1137 }
1138
1139 return 0;
1140 }
1141
ahci_scsi_bus_reset(struct udevice * dev)1142 static int ahci_scsi_bus_reset(struct udevice *dev)
1143 {
1144 /* Not implemented */
1145
1146 return 0;
1147 }
1148
1149 #ifdef CONFIG_DM_SCSI
ahci_bind_scsi(struct udevice * ahci_dev,struct udevice ** devp)1150 int ahci_bind_scsi(struct udevice *ahci_dev, struct udevice **devp)
1151 {
1152 struct udevice *dev;
1153 int ret;
1154
1155 ret = device_bind_driver(ahci_dev, "ahci_scsi", "ahci_scsi", &dev);
1156 if (ret)
1157 return ret;
1158 *devp = dev;
1159
1160 return 0;
1161 }
1162
ahci_probe_scsi(struct udevice * ahci_dev,ulong base)1163 int ahci_probe_scsi(struct udevice *ahci_dev, ulong base)
1164 {
1165 struct ahci_uc_priv *uc_priv;
1166 struct scsi_plat *uc_plat;
1167 struct udevice *dev;
1168 int ret;
1169
1170 device_find_first_child(ahci_dev, &dev);
1171 if (!dev)
1172 return -ENODEV;
1173 uc_plat = dev_get_uclass_plat(dev);
1174 uc_plat->base = base;
1175 uc_plat->max_lun = 1;
1176 uc_plat->max_id = 2;
1177
1178 uc_priv = dev_get_uclass_priv(ahci_dev);
1179 ret = ahci_init_one(uc_priv, dev);
1180 if (ret)
1181 return ret;
1182 ret = ahci_start_ports(uc_priv);
1183 if (ret)
1184 return ret;
1185
1186 /*
1187 * scsi_scan_dev() scans devices up-to the number of max_id.
1188 * Update max_id if the number of detected ports exceeds max_id.
1189 * This allows SCSI to scan all detected ports.
1190 */
1191 uc_plat->max_id = max_t(unsigned long, uc_priv->n_ports,
1192 uc_plat->max_id);
1193
1194 return 0;
1195 }
1196
1197 #ifdef CONFIG_DM_PCI
ahci_probe_scsi_pci(struct udevice * ahci_dev)1198 int ahci_probe_scsi_pci(struct udevice *ahci_dev)
1199 {
1200 ulong base;
1201 u16 vendor, device;
1202
1203 base = (ulong)dm_pci_map_bar(ahci_dev, PCI_BASE_ADDRESS_5,
1204 PCI_REGION_MEM);
1205
1206 /*
1207 * Note:
1208 * Right now, we have only one quirk here, which is not enough to
1209 * introduce a new Kconfig option to select this. Once we have more
1210 * quirks in this AHCI code, we should add a Kconfig option for
1211 * this though.
1212 */
1213 dm_pci_read_config16(ahci_dev, PCI_VENDOR_ID, &vendor);
1214 dm_pci_read_config16(ahci_dev, PCI_DEVICE_ID, &device);
1215
1216 if (vendor == PCI_VENDOR_ID_CAVIUM &&
1217 device == PCI_DEVICE_ID_CAVIUM_SATA)
1218 base = (uintptr_t)dm_pci_map_bar(ahci_dev, PCI_BASE_ADDRESS_0,
1219 PCI_REGION_MEM);
1220 return ahci_probe_scsi(ahci_dev, base);
1221 }
1222 #endif
1223
1224 struct scsi_ops scsi_ops = {
1225 .exec = ahci_scsi_exec,
1226 .bus_reset = ahci_scsi_bus_reset,
1227 };
1228
1229 U_BOOT_DRIVER(ahci_scsi) = {
1230 .name = "ahci_scsi",
1231 .id = UCLASS_SCSI,
1232 .ops = &scsi_ops,
1233 };
1234 #else
scsi_exec(struct udevice * dev,struct scsi_cmd * pccb)1235 int scsi_exec(struct udevice *dev, struct scsi_cmd *pccb)
1236 {
1237 return ahci_scsi_exec(dev, pccb);
1238 }
1239
scsi_bus_reset(struct udevice * dev)1240 __weak int scsi_bus_reset(struct udevice *dev)
1241 {
1242 return ahci_scsi_bus_reset(dev);
1243
1244 return 0;
1245 }
1246 #endif
1247