| /tf-a-ffa_el3_spmc/include/drivers/marvell/ |
| A D | cache_llc.h | 15 #define LLC_CTRL(ap) (MVEBU_LLC_BASE(ap) + 0x100) argument
16 #define LLC_SECURE_CTRL(ap) (MVEBU_LLC_BASE(ap) + 0x10C) argument
17 #define LLC_SYNC(ap) (MVEBU_LLC_BASE(ap) + 0x700) argument
18 #define LLC_BANKED_MNT_AHR(ap) (MVEBU_LLC_BASE(ap) + 0x724) argument
19 #define LLC_INV_WAY(ap) (MVEBU_LLC_BASE(ap) + 0x77C) argument
20 #define LLC_BLK_ALOC(ap) (MVEBU_LLC_BASE(ap) + 0x78c) argument
21 #define LLC_CLEAN_WAY(ap) (MVEBU_LLC_BASE(ap) + 0x7BC) argument
22 #define LLC_CLEAN_INV_WAY(ap) (MVEBU_LLC_BASE(ap) + 0x7FC) argument
23 #define LLC_TCN_LOCK(ap, tc) (MVEBU_LLC_BASE(ap) + 0x920 + 4 * (tc)) argument
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| A D | ccu.h | 18 #define CCU_WIN_CR_OFFSET(ap, win) (MVEBU_CCU_BASE(ap) + 0x0 + \ argument
23 #define CCU_WIN_SCR_OFFSET(ap, win) (MVEBU_CCU_BASE(ap) + 0x4 + \ argument
28 #define CCU_WIN_ALR_OFFSET(ap, win) (MVEBU_CCU_BASE(ap) + 0x8 + \ argument
30 #define CCU_WIN_AHR_OFFSET(ap, win) (MVEBU_CCU_BASE(ap) + 0xC + \ argument
33 #define CCU_WIN_GCR_OFFSET(ap) (MVEBU_CCU_BASE(ap) + 0xD0) argument
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| /tf-a-ffa_el3_spmc/include/lib/libc/ |
| A D | stdarg.h | 15 #define va_start(ap, last) __builtin_va_start(ap, last) argument
16 #define va_end(ap) __builtin_va_end(ap) argument
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| /tf-a-ffa_el3_spmc/drivers/marvell/ |
| A D | gwin.c | 37 #define GWIN_CR_OFFSET(ap, win) (MVEBU_GWIN_BASE(ap) + 0x0 + \ argument
39 #define GWIN_ALR_OFFSET(ap, win) (MVEBU_GWIN_BASE(ap) + 0x8 + \ argument
41 #define GWIN_AHR_OFFSET(ap, win) (MVEBU_GWIN_BASE(ap) + 0xc + \ argument
44 #define CCU_GRU_CR_OFFSET(ap) (MVEBU_CCU_GRU_BASE(ap)) argument
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| A D | io_win.c | 31 #define IO_WIN_ALR_OFFSET(ap, win) (MVEBU_IO_WIN_BASE(ap) + 0x0 + \ argument
33 #define IO_WIN_AHR_OFFSET(ap, win) (MVEBU_IO_WIN_BASE(ap) + 0x8 + \ argument
35 #define IO_WIN_CR_OFFSET(ap, win) (MVEBU_IO_WIN_BASE(ap) + 0xC + \ argument
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| /tf-a-ffa_el3_spmc/plat/marvell/armada/a8k/a80x0/board/ |
| A D | marvell_plat_config.c | 146 uint32_t marvell_get_ccu_gcr_target(int ap) in marvell_get_ccu_gcr_target()
151 int marvell_get_ccu_memory_map(int ap, struct addr_map_win **win, in marvell_get_ccu_memory_map()
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| /tf-a-ffa_el3_spmc/plat/marvell/armada/a8k/common/include/ |
| A D | a8k_plat_def.h | 30 #define MVEBU_REGS_BASE_AP(ap) MVEBU_REGS_BASE argument
31 #define MVEBU_AP_IO_BASE(ap) 0xF2000000 argument
70 #define MVEBU_AP_MC_TRUSTZONE_REG_LOW(ap, win) (MVEBU_REGS_BASE_AP(ap) + \ argument
72 #define MVEBU_AP_MC_TRUSTZONE_REG_HIGH(ap, win) (MVEBU_REGS_BASE_AP(ap) + \ argument
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| /tf-a-ffa_el3_spmc/plat/marvell/armada/a8k/a70x0/board/ |
| A D | marvell_plat_config.c | 117 uint32_t marvell_get_ccu_gcr_target(int ap) in marvell_get_ccu_gcr_target()
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| /tf-a-ffa_el3_spmc/plat/marvell/octeontx/otx2/t91/t9130/board/ |
| A D | marvell_plat_config.c | 168 uint32_t marvell_get_ccu_gcr_target(int ap) in marvell_get_ccu_gcr_target()
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| /tf-a-ffa_el3_spmc/plat/marvell/armada/a8k/a70x0_amc/board/ |
| A D | marvell_plat_config.c | 108 uint32_t marvell_get_ccu_gcr_target(int ap) in marvell_get_ccu_gcr_target()
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| /tf-a-ffa_el3_spmc/plat/marvell/octeontx/otx2/t91/t9130_cex7_eval/board/ |
| A D | marvell_plat_config.c | 200 uint32_t marvell_get_ccu_gcr_target(int ap) in marvell_get_ccu_gcr_target()
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| /tf-a-ffa_el3_spmc/plat/rockchip/rk3399/drivers/dram/ |
| A D | dfs.h | 15 unsigned char ap; member
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| A D | dram_spec_timing.h | 190 uint32_t ap; member
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| /tf-a-ffa_el3_spmc/plat/marvell/armada/a8k/a80x0_mcbin/board/ |
| A D | marvell_plat_config.c | 176 uint32_t marvell_get_ccu_gcr_target(int ap) in marvell_get_ccu_gcr_target()
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| /tf-a-ffa_el3_spmc/plat/marvell/armada/a8k/a80x0_puzzle/board/ |
| A D | marvell_plat_config.c | 177 uint32_t marvell_get_ccu_gcr_target(int ap) in marvell_get_ccu_gcr_target()
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| /tf-a-ffa_el3_spmc/tools/fiptool/ |
| A D | fiptool.c | 57 static void vlog(int prio, const char *msg, va_list ap) in vlog()
68 va_list ap; in log_dbgx() local
77 va_list ap; in log_warnx() local
87 va_list ap; in log_err() local
98 va_list ap; in log_errx() local
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