1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4 */
5
6 #include "debug.h"
7 #include "hal.h"
8 #include "hal_tx.h"
9 #include "hal_rx.h"
10 #include "hal_desc.h"
11 #include "hif.h"
12
ath11k_hal_reo_set_desc_hdr(struct hal_desc_header * hdr,u8 owner,u8 buffer_type,u32 magic)13 static void ath11k_hal_reo_set_desc_hdr(struct hal_desc_header *hdr,
14 u8 owner, u8 buffer_type, u32 magic)
15 {
16 hdr->info0 = FIELD_PREP(HAL_DESC_HDR_INFO0_OWNER, owner) |
17 FIELD_PREP(HAL_DESC_HDR_INFO0_BUF_TYPE, buffer_type);
18
19 /* Magic pattern in reserved bits for debugging */
20 hdr->info0 |= FIELD_PREP(HAL_DESC_HDR_INFO0_DBG_RESERVED, magic);
21 }
22
ath11k_hal_reo_cmd_queue_stats(struct hal_tlv_hdr * tlv,struct ath11k_hal_reo_cmd * cmd)23 static int ath11k_hal_reo_cmd_queue_stats(struct hal_tlv_hdr *tlv,
24 struct ath11k_hal_reo_cmd *cmd)
25 {
26 struct hal_reo_get_queue_stats *desc;
27
28 tlv->tl = FIELD_PREP(HAL_TLV_HDR_TAG, HAL_REO_GET_QUEUE_STATS) |
29 FIELD_PREP(HAL_TLV_HDR_LEN, sizeof(*desc));
30
31 desc = (struct hal_reo_get_queue_stats *)tlv->value;
32 memset(&desc->queue_addr_lo, 0,
33 (sizeof(*desc) - sizeof(struct hal_reo_cmd_hdr)));
34
35 desc->cmd.info0 &= ~HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED;
36 if (cmd->flag & HAL_REO_CMD_FLG_NEED_STATUS)
37 desc->cmd.info0 |= HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED;
38
39 desc->queue_addr_lo = cmd->addr_lo;
40 desc->info0 = FIELD_PREP(HAL_REO_GET_QUEUE_STATS_INFO0_QUEUE_ADDR_HI,
41 cmd->addr_hi);
42 if (cmd->flag & HAL_REO_CMD_FLG_STATS_CLEAR)
43 desc->info0 |= HAL_REO_GET_QUEUE_STATS_INFO0_CLEAR_STATS;
44
45 return FIELD_GET(HAL_REO_CMD_HDR_INFO0_CMD_NUMBER, desc->cmd.info0);
46 }
47
ath11k_hal_reo_cmd_flush_cache(struct ath11k_hal * hal,struct hal_tlv_hdr * tlv,struct ath11k_hal_reo_cmd * cmd)48 static int ath11k_hal_reo_cmd_flush_cache(struct ath11k_hal *hal, struct hal_tlv_hdr *tlv,
49 struct ath11k_hal_reo_cmd *cmd)
50 {
51 struct hal_reo_flush_cache *desc;
52 u8 avail_slot = ffz(hal->avail_blk_resource);
53
54 if (cmd->flag & HAL_REO_CMD_FLG_FLUSH_BLOCK_LATER) {
55 if (avail_slot >= HAL_MAX_AVAIL_BLK_RES)
56 return -ENOSPC;
57
58 hal->current_blk_index = avail_slot;
59 }
60
61 tlv->tl = FIELD_PREP(HAL_TLV_HDR_TAG, HAL_REO_FLUSH_CACHE) |
62 FIELD_PREP(HAL_TLV_HDR_LEN, sizeof(*desc));
63
64 desc = (struct hal_reo_flush_cache *)tlv->value;
65 memset(&desc->cache_addr_lo, 0,
66 (sizeof(*desc) - sizeof(struct hal_reo_cmd_hdr)));
67
68 desc->cmd.info0 &= ~HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED;
69 if (cmd->flag & HAL_REO_CMD_FLG_NEED_STATUS)
70 desc->cmd.info0 |= HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED;
71
72 desc->cache_addr_lo = cmd->addr_lo;
73 desc->info0 = FIELD_PREP(HAL_REO_FLUSH_CACHE_INFO0_CACHE_ADDR_HI,
74 cmd->addr_hi);
75
76 if (cmd->flag & HAL_REO_CMD_FLG_FLUSH_FWD_ALL_MPDUS)
77 desc->info0 |= HAL_REO_FLUSH_CACHE_INFO0_FWD_ALL_MPDUS;
78
79 if (cmd->flag & HAL_REO_CMD_FLG_FLUSH_BLOCK_LATER) {
80 desc->info0 |= HAL_REO_FLUSH_CACHE_INFO0_BLOCK_CACHE_USAGE;
81 desc->info0 |=
82 FIELD_PREP(HAL_REO_FLUSH_CACHE_INFO0_BLOCK_RESRC_IDX,
83 avail_slot);
84 }
85
86 if (cmd->flag & HAL_REO_CMD_FLG_FLUSH_NO_INVAL)
87 desc->info0 |= HAL_REO_FLUSH_CACHE_INFO0_FLUSH_WO_INVALIDATE;
88
89 if (cmd->flag & HAL_REO_CMD_FLG_FLUSH_ALL)
90 desc->info0 |= HAL_REO_FLUSH_CACHE_INFO0_FLUSH_ALL;
91
92 return FIELD_GET(HAL_REO_CMD_HDR_INFO0_CMD_NUMBER, desc->cmd.info0);
93 }
94
ath11k_hal_reo_cmd_update_rx_queue(struct hal_tlv_hdr * tlv,struct ath11k_hal_reo_cmd * cmd)95 static int ath11k_hal_reo_cmd_update_rx_queue(struct hal_tlv_hdr *tlv,
96 struct ath11k_hal_reo_cmd *cmd)
97 {
98 struct hal_reo_update_rx_queue *desc;
99
100 tlv->tl = FIELD_PREP(HAL_TLV_HDR_TAG, HAL_REO_UPDATE_RX_REO_QUEUE) |
101 FIELD_PREP(HAL_TLV_HDR_LEN, sizeof(*desc));
102
103 desc = (struct hal_reo_update_rx_queue *)tlv->value;
104 memset(&desc->queue_addr_lo, 0,
105 (sizeof(*desc) - sizeof(struct hal_reo_cmd_hdr)));
106
107 desc->cmd.info0 &= ~HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED;
108 if (cmd->flag & HAL_REO_CMD_FLG_NEED_STATUS)
109 desc->cmd.info0 |= HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED;
110
111 desc->queue_addr_lo = cmd->addr_lo;
112 desc->info0 =
113 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_QUEUE_ADDR_HI,
114 cmd->addr_hi) |
115 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_RX_QUEUE_NUM,
116 !!(cmd->upd0 & HAL_REO_CMD_UPD0_RX_QUEUE_NUM)) |
117 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_VLD,
118 !!(cmd->upd0 & HAL_REO_CMD_UPD0_VLD)) |
119 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_ASSOC_LNK_DESC_CNT,
120 !!(cmd->upd0 & HAL_REO_CMD_UPD0_ALDC)) |
121 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_DIS_DUP_DETECTION,
122 !!(cmd->upd0 & HAL_REO_CMD_UPD0_DIS_DUP_DETECTION)) |
123 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SOFT_REORDER_EN,
124 !!(cmd->upd0 & HAL_REO_CMD_UPD0_SOFT_REORDER_EN)) |
125 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_AC,
126 !!(cmd->upd0 & HAL_REO_CMD_UPD0_AC)) |
127 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_BAR,
128 !!(cmd->upd0 & HAL_REO_CMD_UPD0_BAR)) |
129 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_RETRY,
130 !!(cmd->upd0 & HAL_REO_CMD_UPD0_RETRY)) |
131 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_CHECK_2K_MODE,
132 !!(cmd->upd0 & HAL_REO_CMD_UPD0_CHECK_2K_MODE)) |
133 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_OOR_MODE,
134 !!(cmd->upd0 & HAL_REO_CMD_UPD0_OOR_MODE)) |
135 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_BA_WINDOW_SIZE,
136 !!(cmd->upd0 & HAL_REO_CMD_UPD0_BA_WINDOW_SIZE)) |
137 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_CHECK,
138 !!(cmd->upd0 & HAL_REO_CMD_UPD0_PN_CHECK)) |
139 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_EVEN_PN,
140 !!(cmd->upd0 & HAL_REO_CMD_UPD0_EVEN_PN)) |
141 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_UNEVEN_PN,
142 !!(cmd->upd0 & HAL_REO_CMD_UPD0_UNEVEN_PN)) |
143 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_HANDLE_ENABLE,
144 !!(cmd->upd0 & HAL_REO_CMD_UPD0_PN_HANDLE_ENABLE)) |
145 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_SIZE,
146 !!(cmd->upd0 & HAL_REO_CMD_UPD0_PN_SIZE)) |
147 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_IGNORE_AMPDU_FLG,
148 !!(cmd->upd0 & HAL_REO_CMD_UPD0_IGNORE_AMPDU_FLG)) |
149 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SVLD,
150 !!(cmd->upd0 & HAL_REO_CMD_UPD0_SVLD)) |
151 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SSN,
152 !!(cmd->upd0 & HAL_REO_CMD_UPD0_SSN)) |
153 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SEQ_2K_ERR,
154 !!(cmd->upd0 & HAL_REO_CMD_UPD0_SEQ_2K_ERR)) |
155 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_VALID,
156 !!(cmd->upd0 & HAL_REO_CMD_UPD0_PN_VALID)) |
157 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN,
158 !!(cmd->upd0 & HAL_REO_CMD_UPD0_PN));
159
160 desc->info1 =
161 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_RX_QUEUE_NUMBER,
162 cmd->rx_queue_num) |
163 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_VLD,
164 !!(cmd->upd1 & HAL_REO_CMD_UPD1_VLD)) |
165 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_ASSOC_LNK_DESC_COUNTER,
166 FIELD_GET(HAL_REO_CMD_UPD1_ALDC, cmd->upd1)) |
167 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_DIS_DUP_DETECTION,
168 !!(cmd->upd1 & HAL_REO_CMD_UPD1_DIS_DUP_DETECTION)) |
169 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_SOFT_REORDER_EN,
170 !!(cmd->upd1 & HAL_REO_CMD_UPD1_SOFT_REORDER_EN)) |
171 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_AC,
172 FIELD_GET(HAL_REO_CMD_UPD1_AC, cmd->upd1)) |
173 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_BAR,
174 !!(cmd->upd1 & HAL_REO_CMD_UPD1_BAR)) |
175 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_CHECK_2K_MODE,
176 !!(cmd->upd1 & HAL_REO_CMD_UPD1_CHECK_2K_MODE)) |
177 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_RETRY,
178 !!(cmd->upd1 & HAL_REO_CMD_UPD1_RETRY)) |
179 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_OOR_MODE,
180 !!(cmd->upd1 & HAL_REO_CMD_UPD1_OOR_MODE)) |
181 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_PN_CHECK,
182 !!(cmd->upd1 & HAL_REO_CMD_UPD1_PN_CHECK)) |
183 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_EVEN_PN,
184 !!(cmd->upd1 & HAL_REO_CMD_UPD1_EVEN_PN)) |
185 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_UNEVEN_PN,
186 !!(cmd->upd1 & HAL_REO_CMD_UPD1_UNEVEN_PN)) |
187 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_PN_HANDLE_ENABLE,
188 !!(cmd->upd1 & HAL_REO_CMD_UPD1_PN_HANDLE_ENABLE)) |
189 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO1_IGNORE_AMPDU_FLG,
190 !!(cmd->upd1 & HAL_REO_CMD_UPD1_IGNORE_AMPDU_FLG));
191
192 if (cmd->pn_size == 24)
193 cmd->pn_size = HAL_RX_REO_QUEUE_PN_SIZE_24;
194 else if (cmd->pn_size == 48)
195 cmd->pn_size = HAL_RX_REO_QUEUE_PN_SIZE_48;
196 else if (cmd->pn_size == 128)
197 cmd->pn_size = HAL_RX_REO_QUEUE_PN_SIZE_128;
198
199 if (cmd->ba_window_size < 1)
200 cmd->ba_window_size = 1;
201
202 if (cmd->ba_window_size == 1)
203 cmd->ba_window_size++;
204
205 desc->info2 =
206 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO2_BA_WINDOW_SIZE,
207 cmd->ba_window_size - 1) |
208 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO2_PN_SIZE, cmd->pn_size) |
209 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO2_SVLD,
210 !!(cmd->upd2 & HAL_REO_CMD_UPD2_SVLD)) |
211 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO2_SSN,
212 FIELD_GET(HAL_REO_CMD_UPD2_SSN, cmd->upd2)) |
213 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO2_SEQ_2K_ERR,
214 !!(cmd->upd2 & HAL_REO_CMD_UPD2_SEQ_2K_ERR)) |
215 FIELD_PREP(HAL_REO_UPD_RX_QUEUE_INFO2_PN_ERR,
216 !!(cmd->upd2 & HAL_REO_CMD_UPD2_PN_ERR));
217
218 return FIELD_GET(HAL_REO_CMD_HDR_INFO0_CMD_NUMBER, desc->cmd.info0);
219 }
220
ath11k_hal_reo_cmd_send(struct ath11k_base * ab,struct hal_srng * srng,enum hal_reo_cmd_type type,struct ath11k_hal_reo_cmd * cmd)221 int ath11k_hal_reo_cmd_send(struct ath11k_base *ab, struct hal_srng *srng,
222 enum hal_reo_cmd_type type,
223 struct ath11k_hal_reo_cmd *cmd)
224 {
225 struct hal_tlv_hdr *reo_desc;
226 int ret;
227
228 spin_lock_bh(&srng->lock);
229
230 ath11k_hal_srng_access_begin(ab, srng);
231 reo_desc = (struct hal_tlv_hdr *)ath11k_hal_srng_src_get_next_entry(ab, srng);
232 if (!reo_desc) {
233 ret = -ENOBUFS;
234 goto out;
235 }
236
237 switch (type) {
238 case HAL_REO_CMD_GET_QUEUE_STATS:
239 ret = ath11k_hal_reo_cmd_queue_stats(reo_desc, cmd);
240 break;
241 case HAL_REO_CMD_FLUSH_CACHE:
242 ret = ath11k_hal_reo_cmd_flush_cache(&ab->hal, reo_desc, cmd);
243 break;
244 case HAL_REO_CMD_UPDATE_RX_QUEUE:
245 ret = ath11k_hal_reo_cmd_update_rx_queue(reo_desc, cmd);
246 break;
247 case HAL_REO_CMD_FLUSH_QUEUE:
248 case HAL_REO_CMD_UNBLOCK_CACHE:
249 case HAL_REO_CMD_FLUSH_TIMEOUT_LIST:
250 ath11k_warn(ab, "Unsupported reo command %d\n", type);
251 ret = -ENOTSUPP;
252 break;
253 default:
254 ath11k_warn(ab, "Unknown reo command %d\n", type);
255 ret = -EINVAL;
256 break;
257 }
258
259 ath11k_dp_shadow_start_timer(ab, srng, &ab->dp.reo_cmd_timer);
260
261 out:
262 ath11k_hal_srng_access_end(ab, srng);
263 spin_unlock_bh(&srng->lock);
264
265 return ret;
266 }
267
ath11k_hal_rx_buf_addr_info_set(void * desc,dma_addr_t paddr,u32 cookie,u8 manager)268 void ath11k_hal_rx_buf_addr_info_set(void *desc, dma_addr_t paddr,
269 u32 cookie, u8 manager)
270 {
271 struct ath11k_buffer_addr *binfo = (struct ath11k_buffer_addr *)desc;
272 u32 paddr_lo, paddr_hi;
273
274 paddr_lo = lower_32_bits(paddr);
275 paddr_hi = upper_32_bits(paddr);
276 binfo->info0 = FIELD_PREP(BUFFER_ADDR_INFO0_ADDR, paddr_lo);
277 binfo->info1 = FIELD_PREP(BUFFER_ADDR_INFO1_ADDR, paddr_hi) |
278 FIELD_PREP(BUFFER_ADDR_INFO1_SW_COOKIE, cookie) |
279 FIELD_PREP(BUFFER_ADDR_INFO1_RET_BUF_MGR, manager);
280 }
281
ath11k_hal_rx_buf_addr_info_get(void * desc,dma_addr_t * paddr,u32 * cookie,u8 * rbm)282 void ath11k_hal_rx_buf_addr_info_get(void *desc, dma_addr_t *paddr,
283 u32 *cookie, u8 *rbm)
284 {
285 struct ath11k_buffer_addr *binfo = (struct ath11k_buffer_addr *)desc;
286
287 *paddr =
288 (((u64)FIELD_GET(BUFFER_ADDR_INFO1_ADDR, binfo->info1)) << 32) |
289 FIELD_GET(BUFFER_ADDR_INFO0_ADDR, binfo->info0);
290 *cookie = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE, binfo->info1);
291 *rbm = FIELD_GET(BUFFER_ADDR_INFO1_RET_BUF_MGR, binfo->info1);
292 }
293
ath11k_hal_rx_msdu_link_info_get(void * link_desc,u32 * num_msdus,u32 * msdu_cookies,enum hal_rx_buf_return_buf_manager * rbm)294 void ath11k_hal_rx_msdu_link_info_get(void *link_desc, u32 *num_msdus,
295 u32 *msdu_cookies,
296 enum hal_rx_buf_return_buf_manager *rbm)
297 {
298 struct hal_rx_msdu_link *link = (struct hal_rx_msdu_link *)link_desc;
299 struct hal_rx_msdu_details *msdu;
300 int i;
301
302 *num_msdus = HAL_NUM_RX_MSDUS_PER_LINK_DESC;
303
304 msdu = &link->msdu_link[0];
305 *rbm = FIELD_GET(BUFFER_ADDR_INFO1_RET_BUF_MGR,
306 msdu->buf_addr_info.info1);
307
308 for (i = 0; i < *num_msdus; i++) {
309 msdu = &link->msdu_link[i];
310
311 if (!FIELD_GET(BUFFER_ADDR_INFO0_ADDR,
312 msdu->buf_addr_info.info0)) {
313 *num_msdus = i;
314 break;
315 }
316 *msdu_cookies = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE,
317 msdu->buf_addr_info.info1);
318 msdu_cookies++;
319 }
320 }
321
ath11k_hal_desc_reo_parse_err(struct ath11k_base * ab,u32 * rx_desc,dma_addr_t * paddr,u32 * desc_bank)322 int ath11k_hal_desc_reo_parse_err(struct ath11k_base *ab, u32 *rx_desc,
323 dma_addr_t *paddr, u32 *desc_bank)
324 {
325 struct hal_reo_dest_ring *desc = (struct hal_reo_dest_ring *)rx_desc;
326 enum hal_reo_dest_ring_push_reason push_reason;
327 enum hal_reo_dest_ring_error_code err_code;
328
329 push_reason = FIELD_GET(HAL_REO_DEST_RING_INFO0_PUSH_REASON,
330 desc->info0);
331 err_code = FIELD_GET(HAL_REO_DEST_RING_INFO0_ERROR_CODE,
332 desc->info0);
333 ab->soc_stats.reo_error[err_code]++;
334
335 if (push_reason != HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED &&
336 push_reason != HAL_REO_DEST_RING_PUSH_REASON_ROUTING_INSTRUCTION) {
337 ath11k_warn(ab, "expected error push reason code, received %d\n",
338 push_reason);
339 return -EINVAL;
340 }
341
342 if (FIELD_GET(HAL_REO_DEST_RING_INFO0_BUFFER_TYPE, desc->info0) !=
343 HAL_REO_DEST_RING_BUFFER_TYPE_LINK_DESC) {
344 ath11k_warn(ab, "expected buffer type link_desc");
345 return -EINVAL;
346 }
347
348 ath11k_hal_rx_reo_ent_paddr_get(ab, rx_desc, paddr, desc_bank);
349
350 return 0;
351 }
352
ath11k_hal_wbm_desc_parse_err(struct ath11k_base * ab,void * desc,struct hal_rx_wbm_rel_info * rel_info)353 int ath11k_hal_wbm_desc_parse_err(struct ath11k_base *ab, void *desc,
354 struct hal_rx_wbm_rel_info *rel_info)
355 {
356 struct hal_wbm_release_ring *wbm_desc = desc;
357 enum hal_wbm_rel_desc_type type;
358 enum hal_wbm_rel_src_module rel_src;
359 enum hal_rx_buf_return_buf_manager ret_buf_mgr;
360
361 type = FIELD_GET(HAL_WBM_RELEASE_INFO0_DESC_TYPE,
362 wbm_desc->info0);
363 /* We expect only WBM_REL buffer type */
364 if (type != HAL_WBM_REL_DESC_TYPE_REL_MSDU) {
365 WARN_ON(1);
366 return -EINVAL;
367 }
368
369 rel_src = FIELD_GET(HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE,
370 wbm_desc->info0);
371 if (rel_src != HAL_WBM_REL_SRC_MODULE_RXDMA &&
372 rel_src != HAL_WBM_REL_SRC_MODULE_REO)
373 return -EINVAL;
374
375 ret_buf_mgr = FIELD_GET(BUFFER_ADDR_INFO1_RET_BUF_MGR,
376 wbm_desc->buf_addr_info.info1);
377 if (ret_buf_mgr != ab->hw_params.hal_params->rx_buf_rbm) {
378 ab->soc_stats.invalid_rbm++;
379 return -EINVAL;
380 }
381
382 rel_info->cookie = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE,
383 wbm_desc->buf_addr_info.info1);
384 rel_info->err_rel_src = rel_src;
385 if (rel_src == HAL_WBM_REL_SRC_MODULE_REO) {
386 rel_info->push_reason =
387 FIELD_GET(HAL_WBM_RELEASE_INFO0_REO_PUSH_REASON,
388 wbm_desc->info0);
389 rel_info->err_code =
390 FIELD_GET(HAL_WBM_RELEASE_INFO0_REO_ERROR_CODE,
391 wbm_desc->info0);
392 } else {
393 rel_info->push_reason =
394 FIELD_GET(HAL_WBM_RELEASE_INFO0_RXDMA_PUSH_REASON,
395 wbm_desc->info0);
396 rel_info->err_code =
397 FIELD_GET(HAL_WBM_RELEASE_INFO0_RXDMA_ERROR_CODE,
398 wbm_desc->info0);
399 }
400
401 rel_info->first_msdu = FIELD_GET(HAL_WBM_RELEASE_INFO2_FIRST_MSDU,
402 wbm_desc->info2);
403 rel_info->last_msdu = FIELD_GET(HAL_WBM_RELEASE_INFO2_LAST_MSDU,
404 wbm_desc->info2);
405 return 0;
406 }
407
ath11k_hal_rx_reo_ent_paddr_get(struct ath11k_base * ab,void * desc,dma_addr_t * paddr,u32 * desc_bank)408 void ath11k_hal_rx_reo_ent_paddr_get(struct ath11k_base *ab, void *desc,
409 dma_addr_t *paddr, u32 *desc_bank)
410 {
411 struct ath11k_buffer_addr *buff_addr = desc;
412
413 *paddr = ((u64)(FIELD_GET(BUFFER_ADDR_INFO1_ADDR, buff_addr->info1)) << 32) |
414 FIELD_GET(BUFFER_ADDR_INFO0_ADDR, buff_addr->info0);
415
416 *desc_bank = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE, buff_addr->info1);
417 }
418
ath11k_hal_rx_msdu_link_desc_set(struct ath11k_base * ab,void * desc,void * link_desc,enum hal_wbm_rel_bm_act action)419 void ath11k_hal_rx_msdu_link_desc_set(struct ath11k_base *ab, void *desc,
420 void *link_desc,
421 enum hal_wbm_rel_bm_act action)
422 {
423 struct hal_wbm_release_ring *dst_desc = desc;
424 struct hal_wbm_release_ring *src_desc = link_desc;
425
426 dst_desc->buf_addr_info = src_desc->buf_addr_info;
427 dst_desc->info0 |= FIELD_PREP(HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE,
428 HAL_WBM_REL_SRC_MODULE_SW) |
429 FIELD_PREP(HAL_WBM_RELEASE_INFO0_BM_ACTION, action) |
430 FIELD_PREP(HAL_WBM_RELEASE_INFO0_DESC_TYPE,
431 HAL_WBM_REL_DESC_TYPE_MSDU_LINK);
432 }
433
ath11k_hal_reo_status_queue_stats(struct ath11k_base * ab,u32 * reo_desc,struct hal_reo_status * status)434 void ath11k_hal_reo_status_queue_stats(struct ath11k_base *ab, u32 *reo_desc,
435 struct hal_reo_status *status)
436 {
437 struct hal_tlv_hdr *tlv = (struct hal_tlv_hdr *)reo_desc;
438 struct hal_reo_get_queue_stats_status *desc =
439 (struct hal_reo_get_queue_stats_status *)tlv->value;
440
441 status->uniform_hdr.cmd_num =
442 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_STATUS_NUM,
443 desc->hdr.info0);
444 status->uniform_hdr.cmd_status =
445 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS,
446 desc->hdr.info0);
447
448 ath11k_dbg(ab, ATH11k_DBG_HAL, "Queue stats status:\n");
449 ath11k_dbg(ab, ATH11k_DBG_HAL, "header: cmd_num %d status %d\n",
450 status->uniform_hdr.cmd_num,
451 status->uniform_hdr.cmd_status);
452 ath11k_dbg(ab, ATH11k_DBG_HAL, "ssn %ld cur_idx %ld\n",
453 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO0_SSN,
454 desc->info0),
455 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO0_CUR_IDX,
456 desc->info0));
457 ath11k_dbg(ab, ATH11k_DBG_HAL, "pn = [%08x, %08x, %08x, %08x]\n",
458 desc->pn[0], desc->pn[1], desc->pn[2], desc->pn[3]);
459 ath11k_dbg(ab, ATH11k_DBG_HAL, "last_rx: enqueue_tstamp %08x dequeue_tstamp %08x\n",
460 desc->last_rx_enqueue_timestamp,
461 desc->last_rx_dequeue_timestamp);
462 ath11k_dbg(ab, ATH11k_DBG_HAL, "rx_bitmap [%08x %08x %08x %08x %08x %08x %08x %08x]\n",
463 desc->rx_bitmap[0], desc->rx_bitmap[1], desc->rx_bitmap[2],
464 desc->rx_bitmap[3], desc->rx_bitmap[4], desc->rx_bitmap[5],
465 desc->rx_bitmap[6], desc->rx_bitmap[7]);
466 ath11k_dbg(ab, ATH11k_DBG_HAL, "count: cur_mpdu %ld cur_msdu %ld\n",
467 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO1_MPDU_COUNT,
468 desc->info1),
469 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO1_MSDU_COUNT,
470 desc->info1));
471 ath11k_dbg(ab, ATH11k_DBG_HAL, "fwd_timeout %ld fwd_bar %ld dup_count %ld\n",
472 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_TIMEOUT_COUNT,
473 desc->info2),
474 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_FDTB_COUNT,
475 desc->info2),
476 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_DUPLICATE_COUNT,
477 desc->info2));
478 ath11k_dbg(ab, ATH11k_DBG_HAL, "frames_in_order %ld bar_rcvd %ld\n",
479 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO3_FIO_COUNT,
480 desc->info3),
481 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO3_BAR_RCVD_CNT,
482 desc->info3));
483 ath11k_dbg(ab, ATH11k_DBG_HAL, "num_mpdus %d num_msdus %d total_bytes %d\n",
484 desc->num_mpdu_frames, desc->num_msdu_frames,
485 desc->total_bytes);
486 ath11k_dbg(ab, ATH11k_DBG_HAL, "late_rcvd %ld win_jump_2k %ld hole_cnt %ld\n",
487 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_LATE_RX_MPDU,
488 desc->info4),
489 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_WINDOW_JMP2K,
490 desc->info4),
491 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_HOLE_COUNT,
492 desc->info4));
493 ath11k_dbg(ab, ATH11k_DBG_HAL, "looping count %ld\n",
494 FIELD_GET(HAL_REO_GET_QUEUE_STATS_STATUS_INFO5_LOOPING_CNT,
495 desc->info5));
496 }
497
ath11k_hal_reo_process_status(u8 * reo_desc,u8 * status)498 int ath11k_hal_reo_process_status(u8 *reo_desc, u8 *status)
499 {
500 struct hal_tlv_hdr *tlv = (struct hal_tlv_hdr *)reo_desc;
501 struct hal_reo_status_hdr *hdr;
502
503 hdr = (struct hal_reo_status_hdr *)tlv->value;
504 *status = FIELD_GET(HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS, hdr->info0);
505
506 return FIELD_GET(HAL_REO_STATUS_HDR_INFO0_STATUS_NUM, hdr->info0);
507 }
508
ath11k_hal_reo_flush_queue_status(struct ath11k_base * ab,u32 * reo_desc,struct hal_reo_status * status)509 void ath11k_hal_reo_flush_queue_status(struct ath11k_base *ab, u32 *reo_desc,
510 struct hal_reo_status *status)
511 {
512 struct hal_tlv_hdr *tlv = (struct hal_tlv_hdr *)reo_desc;
513 struct hal_reo_flush_queue_status *desc =
514 (struct hal_reo_flush_queue_status *)tlv->value;
515
516 status->uniform_hdr.cmd_num =
517 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_STATUS_NUM,
518 desc->hdr.info0);
519 status->uniform_hdr.cmd_status =
520 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS,
521 desc->hdr.info0);
522 status->u.flush_queue.err_detected =
523 FIELD_GET(HAL_REO_FLUSH_QUEUE_INFO0_ERR_DETECTED,
524 desc->info0);
525 }
526
ath11k_hal_reo_flush_cache_status(struct ath11k_base * ab,u32 * reo_desc,struct hal_reo_status * status)527 void ath11k_hal_reo_flush_cache_status(struct ath11k_base *ab, u32 *reo_desc,
528 struct hal_reo_status *status)
529 {
530 struct ath11k_hal *hal = &ab->hal;
531 struct hal_tlv_hdr *tlv = (struct hal_tlv_hdr *)reo_desc;
532 struct hal_reo_flush_cache_status *desc =
533 (struct hal_reo_flush_cache_status *)tlv->value;
534
535 status->uniform_hdr.cmd_num =
536 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_STATUS_NUM,
537 desc->hdr.info0);
538 status->uniform_hdr.cmd_status =
539 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS,
540 desc->hdr.info0);
541
542 status->u.flush_cache.err_detected =
543 FIELD_GET(HAL_REO_FLUSH_CACHE_STATUS_INFO0_IS_ERR,
544 desc->info0);
545 status->u.flush_cache.err_code =
546 FIELD_GET(HAL_REO_FLUSH_CACHE_STATUS_INFO0_BLOCK_ERR_CODE,
547 desc->info0);
548 if (!status->u.flush_cache.err_code)
549 hal->avail_blk_resource |= BIT(hal->current_blk_index);
550
551 status->u.flush_cache.cache_controller_flush_status_hit =
552 FIELD_GET(HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_STATUS_HIT,
553 desc->info0);
554
555 status->u.flush_cache.cache_controller_flush_status_desc_type =
556 FIELD_GET(HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_DESC_TYPE,
557 desc->info0);
558 status->u.flush_cache.cache_controller_flush_status_client_id =
559 FIELD_GET(HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_CLIENT_ID,
560 desc->info0);
561 status->u.flush_cache.cache_controller_flush_status_err =
562 FIELD_GET(HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_ERR,
563 desc->info0);
564 status->u.flush_cache.cache_controller_flush_status_cnt =
565 FIELD_GET(HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_COUNT,
566 desc->info0);
567 }
568
ath11k_hal_reo_unblk_cache_status(struct ath11k_base * ab,u32 * reo_desc,struct hal_reo_status * status)569 void ath11k_hal_reo_unblk_cache_status(struct ath11k_base *ab, u32 *reo_desc,
570 struct hal_reo_status *status)
571 {
572 struct ath11k_hal *hal = &ab->hal;
573 struct hal_tlv_hdr *tlv = (struct hal_tlv_hdr *)reo_desc;
574 struct hal_reo_unblock_cache_status *desc =
575 (struct hal_reo_unblock_cache_status *)tlv->value;
576
577 status->uniform_hdr.cmd_num =
578 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_STATUS_NUM,
579 desc->hdr.info0);
580 status->uniform_hdr.cmd_status =
581 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS,
582 desc->hdr.info0);
583
584 status->u.unblock_cache.err_detected =
585 FIELD_GET(HAL_REO_UNBLOCK_CACHE_STATUS_INFO0_IS_ERR,
586 desc->info0);
587 status->u.unblock_cache.unblock_type =
588 FIELD_GET(HAL_REO_UNBLOCK_CACHE_STATUS_INFO0_TYPE,
589 desc->info0);
590
591 if (!status->u.unblock_cache.err_detected &&
592 status->u.unblock_cache.unblock_type ==
593 HAL_REO_STATUS_UNBLOCK_BLOCKING_RESOURCE)
594 hal->avail_blk_resource &= ~BIT(hal->current_blk_index);
595 }
596
ath11k_hal_reo_flush_timeout_list_status(struct ath11k_base * ab,u32 * reo_desc,struct hal_reo_status * status)597 void ath11k_hal_reo_flush_timeout_list_status(struct ath11k_base *ab,
598 u32 *reo_desc,
599 struct hal_reo_status *status)
600 {
601 struct hal_tlv_hdr *tlv = (struct hal_tlv_hdr *)reo_desc;
602 struct hal_reo_flush_timeout_list_status *desc =
603 (struct hal_reo_flush_timeout_list_status *)tlv->value;
604
605 status->uniform_hdr.cmd_num =
606 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_STATUS_NUM,
607 desc->hdr.info0);
608 status->uniform_hdr.cmd_status =
609 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS,
610 desc->hdr.info0);
611
612 status->u.timeout_list.err_detected =
613 FIELD_GET(HAL_REO_FLUSH_TIMEOUT_STATUS_INFO0_IS_ERR,
614 desc->info0);
615 status->u.timeout_list.list_empty =
616 FIELD_GET(HAL_REO_FLUSH_TIMEOUT_STATUS_INFO0_LIST_EMPTY,
617 desc->info0);
618
619 status->u.timeout_list.release_desc_cnt =
620 FIELD_GET(HAL_REO_FLUSH_TIMEOUT_STATUS_INFO1_REL_DESC_COUNT,
621 desc->info1);
622 status->u.timeout_list.fwd_buf_cnt =
623 FIELD_GET(HAL_REO_FLUSH_TIMEOUT_STATUS_INFO1_FWD_BUF_COUNT,
624 desc->info1);
625 }
626
ath11k_hal_reo_desc_thresh_reached_status(struct ath11k_base * ab,u32 * reo_desc,struct hal_reo_status * status)627 void ath11k_hal_reo_desc_thresh_reached_status(struct ath11k_base *ab,
628 u32 *reo_desc,
629 struct hal_reo_status *status)
630 {
631 struct hal_tlv_hdr *tlv = (struct hal_tlv_hdr *)reo_desc;
632 struct hal_reo_desc_thresh_reached_status *desc =
633 (struct hal_reo_desc_thresh_reached_status *)tlv->value;
634
635 status->uniform_hdr.cmd_num =
636 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_STATUS_NUM,
637 desc->hdr.info0);
638 status->uniform_hdr.cmd_status =
639 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS,
640 desc->hdr.info0);
641
642 status->u.desc_thresh_reached.threshold_idx =
643 FIELD_GET(HAL_REO_DESC_THRESH_STATUS_INFO0_THRESH_INDEX,
644 desc->info0);
645
646 status->u.desc_thresh_reached.link_desc_counter0 =
647 FIELD_GET(HAL_REO_DESC_THRESH_STATUS_INFO1_LINK_DESC_COUNTER0,
648 desc->info1);
649
650 status->u.desc_thresh_reached.link_desc_counter1 =
651 FIELD_GET(HAL_REO_DESC_THRESH_STATUS_INFO2_LINK_DESC_COUNTER1,
652 desc->info2);
653
654 status->u.desc_thresh_reached.link_desc_counter2 =
655 FIELD_GET(HAL_REO_DESC_THRESH_STATUS_INFO3_LINK_DESC_COUNTER2,
656 desc->info3);
657
658 status->u.desc_thresh_reached.link_desc_counter_sum =
659 FIELD_GET(HAL_REO_DESC_THRESH_STATUS_INFO4_LINK_DESC_COUNTER_SUM,
660 desc->info4);
661 }
662
ath11k_hal_reo_update_rx_reo_queue_status(struct ath11k_base * ab,u32 * reo_desc,struct hal_reo_status * status)663 void ath11k_hal_reo_update_rx_reo_queue_status(struct ath11k_base *ab,
664 u32 *reo_desc,
665 struct hal_reo_status *status)
666 {
667 struct hal_tlv_hdr *tlv = (struct hal_tlv_hdr *)reo_desc;
668 struct hal_reo_status_hdr *desc =
669 (struct hal_reo_status_hdr *)tlv->value;
670
671 status->uniform_hdr.cmd_num =
672 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_STATUS_NUM,
673 desc->info0);
674 status->uniform_hdr.cmd_status =
675 FIELD_GET(HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS,
676 desc->info0);
677 }
678
ath11k_hal_reo_qdesc_size(u32 ba_window_size,u8 tid)679 u32 ath11k_hal_reo_qdesc_size(u32 ba_window_size, u8 tid)
680 {
681 u32 num_ext_desc;
682
683 if (ba_window_size <= 1) {
684 if (tid != HAL_DESC_REO_NON_QOS_TID)
685 num_ext_desc = 1;
686 else
687 num_ext_desc = 0;
688 } else if (ba_window_size <= 105) {
689 num_ext_desc = 1;
690 } else if (ba_window_size <= 210) {
691 num_ext_desc = 2;
692 } else {
693 num_ext_desc = 3;
694 }
695
696 return sizeof(struct hal_rx_reo_queue) +
697 (num_ext_desc * sizeof(struct hal_rx_reo_queue_ext));
698 }
699
ath11k_hal_reo_qdesc_setup(void * vaddr,int tid,u32 ba_window_size,u32 start_seq,enum hal_pn_type type)700 void ath11k_hal_reo_qdesc_setup(void *vaddr, int tid, u32 ba_window_size,
701 u32 start_seq, enum hal_pn_type type)
702 {
703 struct hal_rx_reo_queue *qdesc = (struct hal_rx_reo_queue *)vaddr;
704 struct hal_rx_reo_queue_ext *ext_desc;
705
706 memset(qdesc, 0, sizeof(*qdesc));
707
708 ath11k_hal_reo_set_desc_hdr(&qdesc->desc_hdr, HAL_DESC_REO_OWNED,
709 HAL_DESC_REO_QUEUE_DESC,
710 REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_0);
711
712 qdesc->rx_queue_num = FIELD_PREP(HAL_RX_REO_QUEUE_RX_QUEUE_NUMBER, tid);
713
714 qdesc->info0 =
715 FIELD_PREP(HAL_RX_REO_QUEUE_INFO0_VLD, 1) |
716 FIELD_PREP(HAL_RX_REO_QUEUE_INFO0_ASSOC_LNK_DESC_COUNTER, 1) |
717 FIELD_PREP(HAL_RX_REO_QUEUE_INFO0_AC, ath11k_tid_to_ac(tid));
718
719 if (ba_window_size < 1)
720 ba_window_size = 1;
721
722 if (ba_window_size == 1 && tid != HAL_DESC_REO_NON_QOS_TID)
723 ba_window_size++;
724
725 if (ba_window_size == 1)
726 qdesc->info0 |= FIELD_PREP(HAL_RX_REO_QUEUE_INFO0_RETRY, 1);
727
728 qdesc->info0 |= FIELD_PREP(HAL_RX_REO_QUEUE_INFO0_BA_WINDOW_SIZE,
729 ba_window_size - 1);
730 switch (type) {
731 case HAL_PN_TYPE_NONE:
732 case HAL_PN_TYPE_WAPI_EVEN:
733 case HAL_PN_TYPE_WAPI_UNEVEN:
734 break;
735 case HAL_PN_TYPE_WPA:
736 qdesc->info0 |=
737 FIELD_PREP(HAL_RX_REO_QUEUE_INFO0_PN_CHECK, 1) |
738 FIELD_PREP(HAL_RX_REO_QUEUE_INFO0_PN_SIZE,
739 HAL_RX_REO_QUEUE_PN_SIZE_48);
740 break;
741 }
742
743 /* TODO: Set Ignore ampdu flags based on BA window size and/or
744 * AMPDU capabilities
745 */
746 qdesc->info0 |= FIELD_PREP(HAL_RX_REO_QUEUE_INFO0_IGNORE_AMPDU_FLG, 1);
747
748 qdesc->info1 |= FIELD_PREP(HAL_RX_REO_QUEUE_INFO1_SVLD, 0);
749
750 if (start_seq <= 0xfff)
751 qdesc->info1 = FIELD_PREP(HAL_RX_REO_QUEUE_INFO1_SSN,
752 start_seq);
753
754 if (tid == HAL_DESC_REO_NON_QOS_TID)
755 return;
756
757 ext_desc = qdesc->ext_desc;
758
759 /* TODO: HW queue descriptors are currently allocated for max BA
760 * window size for all QOS TIDs so that same descriptor can be used
761 * later when ADDBA request is recevied. This should be changed to
762 * allocate HW queue descriptors based on BA window size being
763 * negotiated (0 for non BA cases), and reallocate when BA window
764 * size changes and also send WMI message to FW to change the REO
765 * queue descriptor in Rx peer entry as part of dp_rx_tid_update.
766 */
767 memset(ext_desc, 0, 3 * sizeof(*ext_desc));
768 ath11k_hal_reo_set_desc_hdr(&ext_desc->desc_hdr, HAL_DESC_REO_OWNED,
769 HAL_DESC_REO_QUEUE_EXT_DESC,
770 REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_1);
771 ext_desc++;
772 ath11k_hal_reo_set_desc_hdr(&ext_desc->desc_hdr, HAL_DESC_REO_OWNED,
773 HAL_DESC_REO_QUEUE_EXT_DESC,
774 REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_2);
775 ext_desc++;
776 ath11k_hal_reo_set_desc_hdr(&ext_desc->desc_hdr, HAL_DESC_REO_OWNED,
777 HAL_DESC_REO_QUEUE_EXT_DESC,
778 REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_3);
779 }
780
ath11k_hal_reo_init_cmd_ring(struct ath11k_base * ab,struct hal_srng * srng)781 void ath11k_hal_reo_init_cmd_ring(struct ath11k_base *ab,
782 struct hal_srng *srng)
783 {
784 struct hal_srng_params params;
785 struct hal_tlv_hdr *tlv;
786 struct hal_reo_get_queue_stats *desc;
787 int i, cmd_num = 1;
788 int entry_size;
789 u8 *entry;
790
791 memset(¶ms, 0, sizeof(params));
792
793 entry_size = ath11k_hal_srng_get_entrysize(ab, HAL_REO_CMD);
794 ath11k_hal_srng_get_params(ab, srng, ¶ms);
795 entry = (u8 *)params.ring_base_vaddr;
796
797 for (i = 0; i < params.num_entries; i++) {
798 tlv = (struct hal_tlv_hdr *)entry;
799 desc = (struct hal_reo_get_queue_stats *)tlv->value;
800 desc->cmd.info0 =
801 FIELD_PREP(HAL_REO_CMD_HDR_INFO0_CMD_NUMBER, cmd_num++);
802 entry += entry_size;
803 }
804 }
805
806 static enum hal_rx_mon_status
ath11k_hal_rx_parse_mon_status_tlv(struct ath11k_base * ab,struct hal_rx_mon_ppdu_info * ppdu_info,u32 tlv_tag,u8 * tlv_data)807 ath11k_hal_rx_parse_mon_status_tlv(struct ath11k_base *ab,
808 struct hal_rx_mon_ppdu_info *ppdu_info,
809 u32 tlv_tag, u8 *tlv_data)
810 {
811 u32 info0, info1;
812
813 switch (tlv_tag) {
814 case HAL_RX_PPDU_START: {
815 struct hal_rx_ppdu_start *ppdu_start =
816 (struct hal_rx_ppdu_start *)tlv_data;
817
818 ppdu_info->ppdu_id =
819 FIELD_GET(HAL_RX_PPDU_START_INFO0_PPDU_ID,
820 __le32_to_cpu(ppdu_start->info0));
821 ppdu_info->chan_num = __le32_to_cpu(ppdu_start->chan_num);
822 ppdu_info->ppdu_ts = __le32_to_cpu(ppdu_start->ppdu_start_ts);
823 break;
824 }
825 case HAL_RX_PPDU_END_USER_STATS: {
826 struct hal_rx_ppdu_end_user_stats *eu_stats =
827 (struct hal_rx_ppdu_end_user_stats *)tlv_data;
828
829 info0 = __le32_to_cpu(eu_stats->info0);
830 info1 = __le32_to_cpu(eu_stats->info1);
831
832 ppdu_info->tid =
833 ffs(FIELD_GET(HAL_RX_PPDU_END_USER_STATS_INFO6_TID_BITMAP,
834 __le32_to_cpu(eu_stats->info6))) - 1;
835 ppdu_info->tcp_msdu_count =
836 FIELD_GET(HAL_RX_PPDU_END_USER_STATS_INFO4_TCP_MSDU_CNT,
837 __le32_to_cpu(eu_stats->info4));
838 ppdu_info->udp_msdu_count =
839 FIELD_GET(HAL_RX_PPDU_END_USER_STATS_INFO4_UDP_MSDU_CNT,
840 __le32_to_cpu(eu_stats->info4));
841 ppdu_info->other_msdu_count =
842 FIELD_GET(HAL_RX_PPDU_END_USER_STATS_INFO5_OTHER_MSDU_CNT,
843 __le32_to_cpu(eu_stats->info5));
844 ppdu_info->tcp_ack_msdu_count =
845 FIELD_GET(HAL_RX_PPDU_END_USER_STATS_INFO5_TCP_ACK_MSDU_CNT,
846 __le32_to_cpu(eu_stats->info5));
847 ppdu_info->preamble_type =
848 FIELD_GET(HAL_RX_PPDU_END_USER_STATS_INFO1_PKT_TYPE, info1);
849 ppdu_info->num_mpdu_fcs_ok =
850 FIELD_GET(HAL_RX_PPDU_END_USER_STATS_INFO1_MPDU_CNT_FCS_OK,
851 info1);
852 ppdu_info->num_mpdu_fcs_err =
853 FIELD_GET(HAL_RX_PPDU_END_USER_STATS_INFO0_MPDU_CNT_FCS_ERR,
854 info0);
855 break;
856 }
857 case HAL_PHYRX_HT_SIG: {
858 struct hal_rx_ht_sig_info *ht_sig =
859 (struct hal_rx_ht_sig_info *)tlv_data;
860
861 info0 = __le32_to_cpu(ht_sig->info0);
862 info1 = __le32_to_cpu(ht_sig->info1);
863
864 ppdu_info->mcs = FIELD_GET(HAL_RX_HT_SIG_INFO_INFO0_MCS, info0);
865 ppdu_info->bw = FIELD_GET(HAL_RX_HT_SIG_INFO_INFO0_BW, info0);
866 ppdu_info->is_stbc = FIELD_GET(HAL_RX_HT_SIG_INFO_INFO1_STBC,
867 info1);
868 ppdu_info->ldpc = FIELD_GET(HAL_RX_HT_SIG_INFO_INFO1_FEC_CODING, info1);
869 ppdu_info->gi = info1 & HAL_RX_HT_SIG_INFO_INFO1_GI;
870
871 switch (ppdu_info->mcs) {
872 case 0 ... 7:
873 ppdu_info->nss = 1;
874 break;
875 case 8 ... 15:
876 ppdu_info->nss = 2;
877 break;
878 case 16 ... 23:
879 ppdu_info->nss = 3;
880 break;
881 case 24 ... 31:
882 ppdu_info->nss = 4;
883 break;
884 }
885
886 if (ppdu_info->nss > 1)
887 ppdu_info->mcs = ppdu_info->mcs % 8;
888
889 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU;
890 break;
891 }
892 case HAL_PHYRX_L_SIG_B: {
893 struct hal_rx_lsig_b_info *lsigb =
894 (struct hal_rx_lsig_b_info *)tlv_data;
895
896 ppdu_info->rate = FIELD_GET(HAL_RX_LSIG_B_INFO_INFO0_RATE,
897 __le32_to_cpu(lsigb->info0));
898 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU;
899 break;
900 }
901 case HAL_PHYRX_L_SIG_A: {
902 struct hal_rx_lsig_a_info *lsiga =
903 (struct hal_rx_lsig_a_info *)tlv_data;
904
905 ppdu_info->rate = FIELD_GET(HAL_RX_LSIG_A_INFO_INFO0_RATE,
906 __le32_to_cpu(lsiga->info0));
907 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU;
908 break;
909 }
910 case HAL_PHYRX_VHT_SIG_A: {
911 struct hal_rx_vht_sig_a_info *vht_sig =
912 (struct hal_rx_vht_sig_a_info *)tlv_data;
913 u32 nsts;
914 u32 group_id;
915 u8 gi_setting;
916
917 info0 = __le32_to_cpu(vht_sig->info0);
918 info1 = __le32_to_cpu(vht_sig->info1);
919
920 ppdu_info->ldpc = FIELD_GET(HAL_RX_VHT_SIG_A_INFO_INFO1_SU_MU_CODING,
921 info0);
922 ppdu_info->mcs = FIELD_GET(HAL_RX_VHT_SIG_A_INFO_INFO1_MCS,
923 info1);
924 gi_setting = FIELD_GET(HAL_RX_VHT_SIG_A_INFO_INFO1_GI_SETTING,
925 info1);
926 switch (gi_setting) {
927 case HAL_RX_VHT_SIG_A_NORMAL_GI:
928 ppdu_info->gi = HAL_RX_GI_0_8_US;
929 break;
930 case HAL_RX_VHT_SIG_A_SHORT_GI:
931 case HAL_RX_VHT_SIG_A_SHORT_GI_AMBIGUITY:
932 ppdu_info->gi = HAL_RX_GI_0_4_US;
933 break;
934 }
935
936 ppdu_info->is_stbc = info0 & HAL_RX_VHT_SIG_A_INFO_INFO0_STBC;
937 nsts = FIELD_GET(HAL_RX_VHT_SIG_A_INFO_INFO0_NSTS, info0);
938 if (ppdu_info->is_stbc && nsts > 0)
939 nsts = ((nsts + 1) >> 1) - 1;
940
941 ppdu_info->nss = (nsts & VHT_SIG_SU_NSS_MASK) + 1;
942 ppdu_info->bw = FIELD_GET(HAL_RX_VHT_SIG_A_INFO_INFO0_BW,
943 info0);
944 ppdu_info->beamformed = info1 &
945 HAL_RX_VHT_SIG_A_INFO_INFO1_BEAMFORMED;
946 group_id = FIELD_GET(HAL_RX_VHT_SIG_A_INFO_INFO0_GROUP_ID,
947 info0);
948 if (group_id == 0 || group_id == 63)
949 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU;
950 else
951 ppdu_info->reception_type =
952 HAL_RX_RECEPTION_TYPE_MU_MIMO;
953 break;
954 }
955 case HAL_PHYRX_HE_SIG_A_SU: {
956 struct hal_rx_he_sig_a_su_info *he_sig_a =
957 (struct hal_rx_he_sig_a_su_info *)tlv_data;
958 u32 nsts, cp_ltf, dcm;
959
960 info0 = __le32_to_cpu(he_sig_a->info0);
961 info1 = __le32_to_cpu(he_sig_a->info1);
962
963 ppdu_info->mcs =
964 FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_MCS,
965 info0);
966 ppdu_info->bw =
967 FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_BW,
968 info0);
969 ppdu_info->ldpc = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO1_CODING, info0);
970 ppdu_info->is_stbc = info1 &
971 HAL_RX_HE_SIG_A_SU_INFO_INFO1_STBC;
972 ppdu_info->beamformed = info1 &
973 HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXBF;
974 dcm = info0 & HAL_RX_HE_SIG_A_SU_INFO_INFO0_DCM;
975 cp_ltf = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_CP_LTF_SIZE,
976 info0);
977 nsts = FIELD_GET(HAL_RX_HE_SIG_A_SU_INFO_INFO0_NSTS, info0);
978
979 switch (cp_ltf) {
980 case 0:
981 case 1:
982 ppdu_info->gi = HAL_RX_GI_0_8_US;
983 break;
984 case 2:
985 ppdu_info->gi = HAL_RX_GI_1_6_US;
986 break;
987 case 3:
988 if (dcm && ppdu_info->is_stbc)
989 ppdu_info->gi = HAL_RX_GI_0_8_US;
990 else
991 ppdu_info->gi = HAL_RX_GI_3_2_US;
992 break;
993 }
994
995 ppdu_info->nss = nsts + 1;
996 ppdu_info->dcm = dcm;
997 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU;
998 break;
999 }
1000 case HAL_PHYRX_HE_SIG_A_MU_DL: {
1001 struct hal_rx_he_sig_a_mu_dl_info *he_sig_a_mu_dl =
1002 (struct hal_rx_he_sig_a_mu_dl_info *)tlv_data;
1003
1004 u32 cp_ltf;
1005
1006 info0 = __le32_to_cpu(he_sig_a_mu_dl->info0);
1007 info1 = __le32_to_cpu(he_sig_a_mu_dl->info1);
1008
1009 ppdu_info->bw =
1010 FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_TRANSMIT_BW,
1011 info0);
1012 cp_ltf = FIELD_GET(HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_CP_LTF_SIZE,
1013 info0);
1014
1015 switch (cp_ltf) {
1016 case 0:
1017 case 1:
1018 ppdu_info->gi = HAL_RX_GI_0_8_US;
1019 break;
1020 case 2:
1021 ppdu_info->gi = HAL_RX_GI_1_6_US;
1022 break;
1023 case 3:
1024 ppdu_info->gi = HAL_RX_GI_3_2_US;
1025 break;
1026 }
1027
1028 ppdu_info->is_stbc = info1 &
1029 HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_STBC;
1030 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_MIMO;
1031 break;
1032 }
1033 case HAL_PHYRX_HE_SIG_B1_MU: {
1034 struct hal_rx_he_sig_b1_mu_info *he_sig_b1_mu =
1035 (struct hal_rx_he_sig_b1_mu_info *)tlv_data;
1036 u16 ru_tones;
1037
1038 info0 = __le32_to_cpu(he_sig_b1_mu->info0);
1039
1040 ru_tones = FIELD_GET(HAL_RX_HE_SIG_B1_MU_INFO_INFO0_RU_ALLOCATION,
1041 info0);
1042 ppdu_info->ru_alloc = ath11k_he_ru_tones_to_nl80211_he_ru_alloc(ru_tones);
1043 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_MIMO;
1044 break;
1045 }
1046 case HAL_PHYRX_HE_SIG_B2_MU: {
1047 struct hal_rx_he_sig_b2_mu_info *he_sig_b2_mu =
1048 (struct hal_rx_he_sig_b2_mu_info *)tlv_data;
1049
1050 info0 = __le32_to_cpu(he_sig_b2_mu->info0);
1051
1052 ppdu_info->mcs =
1053 FIELD_GET(HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_MCS,
1054 info0);
1055 ppdu_info->nss =
1056 FIELD_GET(HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_NSTS,
1057 info0) + 1;
1058 ppdu_info->ldpc = FIELD_GET(HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_CODING,
1059 info0);
1060 break;
1061 }
1062 case HAL_PHYRX_HE_SIG_B2_OFDMA: {
1063 struct hal_rx_he_sig_b2_ofdma_info *he_sig_b2_ofdma =
1064 (struct hal_rx_he_sig_b2_ofdma_info *)tlv_data;
1065
1066 info0 = __le32_to_cpu(he_sig_b2_ofdma->info0);
1067
1068 ppdu_info->mcs =
1069 FIELD_GET(HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_MCS,
1070 info0);
1071 ppdu_info->nss =
1072 FIELD_GET(HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_NSTS,
1073 info0) + 1;
1074 ppdu_info->beamformed =
1075 info0 &
1076 HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_TXBF;
1077 ppdu_info->ldpc = FIELD_GET(HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_CODING,
1078 info0);
1079 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_OFDMA;
1080 break;
1081 }
1082 case HAL_PHYRX_RSSI_LEGACY: {
1083 struct hal_rx_phyrx_rssi_legacy_info *rssi =
1084 (struct hal_rx_phyrx_rssi_legacy_info *)tlv_data;
1085
1086 /* TODO: Please note that the combined rssi will not be accurate
1087 * in MU case. Rssi in MU needs to be retrieved from
1088 * PHYRX_OTHER_RECEIVE_INFO TLV.
1089 */
1090 ppdu_info->rssi_comb =
1091 FIELD_GET(HAL_RX_PHYRX_RSSI_LEGACY_INFO_INFO1_RSSI_COMB,
1092 __le32_to_cpu(rssi->info0));
1093 break;
1094 }
1095 case HAL_RX_MPDU_START: {
1096 u16 peer_id;
1097
1098 peer_id = ab->hw_params.hw_ops->mpdu_info_get_peerid(tlv_data);
1099 if (peer_id)
1100 ppdu_info->peer_id = peer_id;
1101 break;
1102 }
1103 case HAL_RXPCU_PPDU_END_INFO: {
1104 struct hal_rx_ppdu_end_duration *ppdu_rx_duration =
1105 (struct hal_rx_ppdu_end_duration *)tlv_data;
1106 ppdu_info->rx_duration =
1107 FIELD_GET(HAL_RX_PPDU_END_DURATION,
1108 __le32_to_cpu(ppdu_rx_duration->info0));
1109 break;
1110 }
1111 case HAL_DUMMY:
1112 return HAL_RX_MON_STATUS_BUF_DONE;
1113 case HAL_RX_PPDU_END_STATUS_DONE:
1114 case 0:
1115 return HAL_RX_MON_STATUS_PPDU_DONE;
1116 default:
1117 break;
1118 }
1119
1120 return HAL_RX_MON_STATUS_PPDU_NOT_DONE;
1121 }
1122
1123 enum hal_rx_mon_status
ath11k_hal_rx_parse_mon_status(struct ath11k_base * ab,struct hal_rx_mon_ppdu_info * ppdu_info,struct sk_buff * skb)1124 ath11k_hal_rx_parse_mon_status(struct ath11k_base *ab,
1125 struct hal_rx_mon_ppdu_info *ppdu_info,
1126 struct sk_buff *skb)
1127 {
1128 struct hal_tlv_hdr *tlv;
1129 enum hal_rx_mon_status hal_status = HAL_RX_MON_STATUS_BUF_DONE;
1130 u16 tlv_tag;
1131 u16 tlv_len;
1132 u8 *ptr = skb->data;
1133
1134 do {
1135 tlv = (struct hal_tlv_hdr *)ptr;
1136 tlv_tag = FIELD_GET(HAL_TLV_HDR_TAG, tlv->tl);
1137 tlv_len = FIELD_GET(HAL_TLV_HDR_LEN, tlv->tl);
1138 ptr += sizeof(*tlv);
1139
1140 /* The actual length of PPDU_END is the combined length of many PHY
1141 * TLVs that follow. Skip the TLV header and
1142 * rx_rxpcu_classification_overview that follows the header to get to
1143 * next TLV.
1144 */
1145 if (tlv_tag == HAL_RX_PPDU_END)
1146 tlv_len = sizeof(struct hal_rx_rxpcu_classification_overview);
1147
1148 hal_status = ath11k_hal_rx_parse_mon_status_tlv(ab, ppdu_info,
1149 tlv_tag, ptr);
1150 ptr += tlv_len;
1151 ptr = PTR_ALIGN(ptr, HAL_TLV_ALIGN);
1152
1153 if ((ptr - skb->data) >= DP_RX_BUFFER_SIZE)
1154 break;
1155 } while (hal_status == HAL_RX_MON_STATUS_PPDU_NOT_DONE);
1156
1157 return hal_status;
1158 }
1159
ath11k_hal_rx_reo_ent_buf_paddr_get(void * rx_desc,dma_addr_t * paddr,u32 * sw_cookie,void ** pp_buf_addr,u8 * rbm,u32 * msdu_cnt)1160 void ath11k_hal_rx_reo_ent_buf_paddr_get(void *rx_desc, dma_addr_t *paddr,
1161 u32 *sw_cookie, void **pp_buf_addr,
1162 u8 *rbm, u32 *msdu_cnt)
1163 {
1164 struct hal_reo_entrance_ring *reo_ent_ring =
1165 (struct hal_reo_entrance_ring *)rx_desc;
1166 struct ath11k_buffer_addr *buf_addr_info;
1167 struct rx_mpdu_desc *rx_mpdu_desc_info_details;
1168
1169 rx_mpdu_desc_info_details =
1170 (struct rx_mpdu_desc *)&reo_ent_ring->rx_mpdu_info;
1171
1172 *msdu_cnt = FIELD_GET(RX_MPDU_DESC_INFO0_MSDU_COUNT,
1173 rx_mpdu_desc_info_details->info0);
1174
1175 buf_addr_info = (struct ath11k_buffer_addr *)&reo_ent_ring->buf_addr_info;
1176
1177 *paddr = (((u64)FIELD_GET(BUFFER_ADDR_INFO1_ADDR,
1178 buf_addr_info->info1)) << 32) |
1179 FIELD_GET(BUFFER_ADDR_INFO0_ADDR,
1180 buf_addr_info->info0);
1181
1182 *sw_cookie = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE,
1183 buf_addr_info->info1);
1184 *rbm = FIELD_GET(BUFFER_ADDR_INFO1_RET_BUF_MGR,
1185 buf_addr_info->info1);
1186
1187 *pp_buf_addr = (void *)buf_addr_info;
1188 }
1189