1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2010
4 * Rob Emanuele <rob@emanuele.us>
5 * Reinhard Meyer, EMK Elektronik <reinhard.meyer@emk-elektronik.de>
6 *
7 * Original Driver:
8 * Copyright (C) 2004-2006 Atmel Corporation
9 */
10
11 #include <common.h>
12 #include <clk.h>
13 #include <dm.h>
14 #include <log.h>
15 #include <mmc.h>
16 #include <part.h>
17 #include <malloc.h>
18 #include <asm/io.h>
19 #include <linux/delay.h>
20 #include <linux/errno.h>
21 #include <asm/byteorder.h>
22 #include <asm/arch/clk.h>
23 #include <asm/arch/hardware.h>
24 #include "atmel_mci.h"
25
26 #ifndef CONFIG_SYS_MMC_CLK_OD
27 # define CONFIG_SYS_MMC_CLK_OD 150000
28 #endif
29
30 #define MMC_DEFAULT_BLKLEN 512
31
32 #if defined(CONFIG_ATMEL_MCI_PORTB)
33 # define MCI_BUS 1
34 #else
35 # define MCI_BUS 0
36 #endif
37
38 #ifdef CONFIG_DM_MMC
39 struct atmel_mci_plat {
40 struct mmc mmc;
41 struct mmc_config cfg;
42 struct atmel_mci *mci;
43 };
44 #endif
45
46 struct atmel_mci_priv {
47 #ifndef CONFIG_DM_MMC
48 struct mmc_config cfg;
49 struct atmel_mci *mci;
50 #endif
51 unsigned int initialized:1;
52 unsigned int curr_clk;
53 #ifdef CONFIG_DM_MMC
54 ulong bus_clk_rate;
55 #endif
56 };
57
58 /* Read Atmel MCI IP version */
atmel_mci_get_version(struct atmel_mci * mci)59 static unsigned int atmel_mci_get_version(struct atmel_mci *mci)
60 {
61 return readl(&mci->version) & 0x00000fff;
62 }
63
64 /*
65 * Print command and status:
66 *
67 * - always when DEBUG is defined
68 * - on command errors
69 */
dump_cmd(u32 cmdr,u32 arg,u32 status,const char * msg)70 static void dump_cmd(u32 cmdr, u32 arg, u32 status, const char* msg)
71 {
72 debug("gen_atmel_mci: CMDR %08x (%2u) ARGR %08x (SR: %08x) %s\n",
73 cmdr, cmdr & 0x3F, arg, status, msg);
74 }
75
mci_set_blklen(atmel_mci_t * mci,int blklen)76 static inline void mci_set_blklen(atmel_mci_t *mci, int blklen)
77 {
78 unsigned int version = atmel_mci_get_version(mci);
79
80 blklen &= 0xfffc;
81
82 /* MCI IP version >= 0x200 has blkr */
83 if (version >= 0x200)
84 writel(MMCI_BFINS(BLKLEN, blklen, readl(&mci->blkr)),
85 &mci->blkr);
86 else
87 writel(MMCI_BFINS(BLKLEN, blklen, readl(&mci->mr)), &mci->mr);
88 }
89
90 /* Setup for MCI Clock and Block Size */
91 #ifdef CONFIG_DM_MMC
mci_set_mode(struct udevice * dev,u32 hz,u32 blklen)92 static void mci_set_mode(struct udevice *dev, u32 hz, u32 blklen)
93 {
94 struct atmel_mci_plat *plat = dev_get_plat(dev);
95 struct atmel_mci_priv *priv = dev_get_priv(dev);
96 struct mmc *mmc = &plat->mmc;
97 u32 bus_hz = priv->bus_clk_rate;
98 atmel_mci_t *mci = plat->mci;
99 #else
100 static void mci_set_mode(struct mmc *mmc, u32 hz, u32 blklen)
101 {
102 struct atmel_mci_priv *priv = mmc->priv;
103 u32 bus_hz = get_mci_clk_rate();
104 atmel_mci_t *mci = priv->mci;
105 #endif
106
107 u32 clkdiv = 255;
108 unsigned int version = atmel_mci_get_version(mci);
109 u32 clkodd = 0;
110 u32 mr;
111
112 debug("mci: bus_hz is %u, setting clock %u Hz, block size %u\n",
113 bus_hz, hz, blklen);
114 if (hz > 0) {
115 if (version >= 0x500) {
116 clkdiv = DIV_ROUND_UP(bus_hz, hz) - 2;
117 if (clkdiv > 511)
118 clkdiv = 511;
119
120 clkodd = clkdiv & 1;
121 clkdiv >>= 1;
122
123 debug("mci: setting clock %u Hz, block size %u\n",
124 bus_hz / (clkdiv * 2 + clkodd + 2), blklen);
125 } else {
126 /* find clkdiv yielding a rate <= than requested */
127 for (clkdiv = 0; clkdiv < 255; clkdiv++) {
128 if ((bus_hz / (clkdiv + 1) / 2) <= hz)
129 break;
130 }
131 debug("mci: setting clock %u Hz, block size %u\n",
132 (bus_hz / (clkdiv + 1)) / 2, blklen);
133
134 }
135 }
136 if (version >= 0x500)
137 priv->curr_clk = bus_hz / (clkdiv * 2 + clkodd + 2);
138 else
139 priv->curr_clk = (bus_hz / (clkdiv + 1)) / 2;
140
141 mr = MMCI_BF(CLKDIV, clkdiv);
142
143 /* MCI IP version >= 0x200 has R/WPROOF */
144 if (version >= 0x200)
145 mr |= MMCI_BIT(RDPROOF) | MMCI_BIT(WRPROOF);
146
147 /*
148 * MCI IP version >= 0x500 use bit 16 as clkodd.
149 * MCI IP version < 0x500 use upper 16 bits for blklen.
150 */
151 if (version >= 0x500)
152 mr |= MMCI_BF(CLKODD, clkodd);
153
154 writel(mr, &mci->mr);
155
156 mci_set_blklen(mci, blklen);
157
158 if (mmc->card_caps & mmc->cfg->host_caps & MMC_MODE_HS)
159 writel(MMCI_BIT(HSMODE), &mci->cfg);
160
161 priv->initialized = 1;
162 }
163
164 /* Return the CMDR with flags for a given command and data packet */
165 static u32 mci_encode_cmd(
166 struct mmc_cmd *cmd, struct mmc_data *data, u32* error_flags)
167 {
168 u32 cmdr = 0;
169
170 /* Default Flags for Errors */
171 *error_flags |= (MMCI_BIT(DTOE) | MMCI_BIT(RDIRE) | MMCI_BIT(RENDE) |
172 MMCI_BIT(RINDE) | MMCI_BIT(RTOE));
173
174 /* Default Flags for the Command */
175 cmdr |= MMCI_BIT(MAXLAT);
176
177 if (data) {
178 cmdr |= MMCI_BF(TRCMD, 1);
179 if (data->blocks > 1)
180 cmdr |= MMCI_BF(TRTYP, 1);
181 if (data->flags & MMC_DATA_READ)
182 cmdr |= MMCI_BIT(TRDIR);
183 }
184
185 if (cmd->resp_type & MMC_RSP_CRC)
186 *error_flags |= MMCI_BIT(RCRCE);
187 if (cmd->resp_type & MMC_RSP_136)
188 cmdr |= MMCI_BF(RSPTYP, 2);
189 else if (cmd->resp_type & MMC_RSP_BUSY)
190 cmdr |= MMCI_BF(RSPTYP, 3);
191 else if (cmd->resp_type & MMC_RSP_PRESENT)
192 cmdr |= MMCI_BF(RSPTYP, 1);
193
194 return cmdr | MMCI_BF(CMDNB, cmd->cmdidx);
195 }
196
197 /* Entered into function pointer in mci_send_cmd */
198 static u32 mci_data_read(atmel_mci_t *mci, u32* data, u32 error_flags)
199 {
200 u32 status;
201
202 do {
203 status = readl(&mci->sr);
204 if (status & (error_flags | MMCI_BIT(OVRE)))
205 goto io_fail;
206 } while (!(status & MMCI_BIT(RXRDY)));
207
208 if (status & MMCI_BIT(RXRDY)) {
209 *data = readl(&mci->rdr);
210 status = 0;
211 }
212 io_fail:
213 return status;
214 }
215
216 /* Entered into function pointer in mci_send_cmd */
217 static u32 mci_data_write(atmel_mci_t *mci, u32* data, u32 error_flags)
218 {
219 u32 status;
220
221 do {
222 status = readl(&mci->sr);
223 if (status & (error_flags | MMCI_BIT(UNRE)))
224 goto io_fail;
225 } while (!(status & MMCI_BIT(TXRDY)));
226
227 if (status & MMCI_BIT(TXRDY)) {
228 writel(*data, &mci->tdr);
229 status = 0;
230 }
231 io_fail:
232 return status;
233 }
234
235 /*
236 * Entered into mmc structure during driver init
237 *
238 * Sends a command out on the bus and deals with the block data.
239 * Takes the mmc pointer, a command pointer, and an optional data pointer.
240 */
241 #ifdef CONFIG_DM_MMC
242 static int atmel_mci_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
243 struct mmc_data *data)
244 {
245 struct atmel_mci_plat *plat = dev_get_plat(dev);
246 struct atmel_mci_priv *priv = dev_get_priv(dev);
247 atmel_mci_t *mci = plat->mci;
248 #else
249 static int
250 mci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
251 {
252 struct atmel_mci_priv *priv = mmc->priv;
253 atmel_mci_t *mci = priv->mci;
254 #endif
255 u32 cmdr;
256 u32 error_flags = 0;
257 u32 status;
258
259 if (!priv->initialized) {
260 puts ("MCI not initialized!\n");
261 return -ECOMM;
262 }
263
264 /* Figure out the transfer arguments */
265 cmdr = mci_encode_cmd(cmd, data, &error_flags);
266
267 mci_set_blklen(mci, data->blocksize);
268
269 /* For multi blocks read/write, set the block register */
270 if ((cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK)
271 || (cmd->cmdidx == MMC_CMD_WRITE_MULTIPLE_BLOCK))
272 writel(data->blocks | MMCI_BF(BLKLEN, data->blocksize),
273 &mci->blkr);
274
275 /* Send the command */
276 writel(cmd->cmdarg, &mci->argr);
277 writel(cmdr, &mci->cmdr);
278
279 #ifdef DEBUG
280 dump_cmd(cmdr, cmd->cmdarg, 0, "DEBUG");
281 #endif
282
283 /* Wait for the command to complete */
284 while (!((status = readl(&mci->sr)) & MMCI_BIT(CMDRDY)));
285
286 if ((status & error_flags) & MMCI_BIT(RTOE)) {
287 dump_cmd(cmdr, cmd->cmdarg, status, "Command Time Out");
288 return -ETIMEDOUT;
289 } else if (status & error_flags) {
290 dump_cmd(cmdr, cmd->cmdarg, status, "Command Failed");
291 return -ECOMM;
292 }
293
294 /* Copy the response to the response buffer */
295 if (cmd->resp_type & MMC_RSP_136) {
296 cmd->response[0] = readl(&mci->rspr);
297 cmd->response[1] = readl(&mci->rspr1);
298 cmd->response[2] = readl(&mci->rspr2);
299 cmd->response[3] = readl(&mci->rspr3);
300 } else
301 cmd->response[0] = readl(&mci->rspr);
302
303 /* transfer all of the blocks */
304 if (data) {
305 u32 word_count, block_count;
306 u32* ioptr;
307 u32 i;
308 u32 (*mci_data_op)
309 (atmel_mci_t *mci, u32* data, u32 error_flags);
310
311 if (data->flags & MMC_DATA_READ) {
312 mci_data_op = mci_data_read;
313 ioptr = (u32*)data->dest;
314 } else {
315 mci_data_op = mci_data_write;
316 ioptr = (u32*)data->src;
317 }
318
319 status = 0;
320 for (block_count = 0;
321 block_count < data->blocks && !status;
322 block_count++) {
323 word_count = 0;
324 do {
325 status = mci_data_op(mci, ioptr, error_flags);
326 word_count++;
327 ioptr++;
328 } while (!status && word_count < (data->blocksize/4));
329 #ifdef DEBUG
330 if (data->flags & MMC_DATA_READ)
331 {
332 u32 cnt = word_count * 4;
333 printf("Read Data:\n");
334 print_buffer(0, data->dest + cnt * block_count,
335 1, cnt, 0);
336 }
337 #endif
338 if (status) {
339 dump_cmd(cmdr, cmd->cmdarg, status,
340 "Data Transfer Failed");
341 return -ECOMM;
342 }
343 }
344
345 /* Wait for Transfer End */
346 i = 0;
347 do {
348 status = readl(&mci->sr);
349
350 if (status & error_flags) {
351 dump_cmd(cmdr, cmd->cmdarg, status,
352 "DTIP Wait Failed");
353 return -ECOMM;
354 }
355 i++;
356 } while ((status & MMCI_BIT(DTIP)) && i < 10000);
357 if (status & MMCI_BIT(DTIP)) {
358 dump_cmd(cmdr, cmd->cmdarg, status,
359 "XFER DTIP never unset, ignoring");
360 }
361 }
362
363 /*
364 * After the switch command, wait for 8 clocks before the next
365 * command
366 */
367 if (cmd->cmdidx == MMC_CMD_SWITCH)
368 udelay(8*1000000 / priv->curr_clk); /* 8 clk in us */
369
370 return 0;
371 }
372
373 #ifdef CONFIG_DM_MMC
374 static int atmel_mci_set_ios(struct udevice *dev)
375 {
376 struct atmel_mci_plat *plat = dev_get_plat(dev);
377 struct mmc *mmc = mmc_get_mmc_dev(dev);
378 atmel_mci_t *mci = plat->mci;
379 #else
380 /* Entered into mmc structure during driver init */
381 static int mci_set_ios(struct mmc *mmc)
382 {
383 struct atmel_mci_priv *priv = mmc->priv;
384 atmel_mci_t *mci = priv->mci;
385 #endif
386 int bus_width = mmc->bus_width;
387 unsigned int version = atmel_mci_get_version(mci);
388 int busw;
389
390 /* Set the clock speed */
391 #ifdef CONFIG_DM_MMC
392 mci_set_mode(dev, mmc->clock, MMC_DEFAULT_BLKLEN);
393 #else
394 mci_set_mode(mmc, mmc->clock, MMC_DEFAULT_BLKLEN);
395 #endif
396
397 /*
398 * set the bus width and select slot for this interface
399 * there is no capability for multiple slots on the same interface yet
400 */
401 if ((version & 0xf00) >= 0x300) {
402 switch (bus_width) {
403 case 8:
404 busw = 3;
405 break;
406 case 4:
407 busw = 2;
408 break;
409 default:
410 busw = 0;
411 break;
412 }
413
414 writel(busw << 6 | MMCI_BF(SCDSEL, MCI_BUS), &mci->sdcr);
415 } else {
416 busw = (bus_width == 4) ? 1 : 0;
417
418 writel(busw << 7 | MMCI_BF(SCDSEL, MCI_BUS), &mci->sdcr);
419 }
420
421 return 0;
422 }
423
424 #ifdef CONFIG_DM_MMC
425 static int atmel_mci_hw_init(struct udevice *dev)
426 {
427 struct atmel_mci_plat *plat = dev_get_plat(dev);
428 atmel_mci_t *mci = plat->mci;
429 #else
430 /* Entered into mmc structure during driver init */
431 static int mci_init(struct mmc *mmc)
432 {
433 struct atmel_mci_priv *priv = mmc->priv;
434 atmel_mci_t *mci = priv->mci;
435 #endif
436
437 /* Initialize controller */
438 writel(MMCI_BIT(SWRST), &mci->cr); /* soft reset */
439 writel(MMCI_BIT(PWSDIS), &mci->cr); /* disable power save */
440 writel(MMCI_BIT(MCIEN), &mci->cr); /* enable mci */
441 writel(MMCI_BF(SCDSEL, MCI_BUS), &mci->sdcr); /* select port */
442
443 /* This delay can be optimized, but stick with max value */
444 writel(0x7f, &mci->dtor);
445 /* Disable Interrupts */
446 writel(~0UL, &mci->idr);
447
448 /* Set default clocks and blocklen */
449 #ifdef CONFIG_DM_MMC
450 mci_set_mode(dev, CONFIG_SYS_MMC_CLK_OD, MMC_DEFAULT_BLKLEN);
451 #else
452 mci_set_mode(mmc, CONFIG_SYS_MMC_CLK_OD, MMC_DEFAULT_BLKLEN);
453 #endif
454
455 return 0;
456 }
457
458 #ifndef CONFIG_DM_MMC
459 static const struct mmc_ops atmel_mci_ops = {
460 .send_cmd = mci_send_cmd,
461 .set_ios = mci_set_ios,
462 .init = mci_init,
463 };
464
465 /*
466 * This is the only exported function
467 *
468 * Call it with the MCI register base address
469 */
470 int atmel_mci_init(void *regs)
471 {
472 struct mmc *mmc;
473 struct mmc_config *cfg;
474 struct atmel_mci_priv *priv;
475 unsigned int version;
476
477 priv = calloc(1, sizeof(*priv));
478 if (!priv)
479 return -ENOMEM;
480
481 cfg = &priv->cfg;
482
483 cfg->name = "mci";
484 cfg->ops = &atmel_mci_ops;
485
486 priv->mci = (struct atmel_mci *)regs;
487 priv->initialized = 0;
488
489 /* need to be able to pass these in on a board by board basis */
490 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
491 version = atmel_mci_get_version(priv->mci);
492 if ((version & 0xf00) >= 0x300) {
493 cfg->host_caps = MMC_MODE_8BIT;
494 cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz;
495 }
496
497 cfg->host_caps |= MMC_MODE_4BIT;
498
499 /*
500 * min and max frequencies determined by
501 * max and min of clock divider
502 */
503 cfg->f_min = get_mci_clk_rate() / (2*256);
504 cfg->f_max = get_mci_clk_rate() / (2*1);
505
506 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
507
508 mmc = mmc_create(cfg, priv);
509
510 if (mmc == NULL) {
511 free(priv);
512 return -ENODEV;
513 }
514 /* NOTE: possibly leaking the priv structure */
515
516 return 0;
517 }
518 #endif
519
520 #ifdef CONFIG_DM_MMC
521 static const struct dm_mmc_ops atmel_mci_mmc_ops = {
522 .send_cmd = atmel_mci_send_cmd,
523 .set_ios = atmel_mci_set_ios,
524 };
525
526 static void atmel_mci_setup_cfg(struct udevice *dev)
527 {
528 struct atmel_mci_plat *plat = dev_get_plat(dev);
529 struct atmel_mci_priv *priv = dev_get_priv(dev);
530 struct mmc_config *cfg;
531 u32 version;
532
533 cfg = &plat->cfg;
534 cfg->name = "Atmel mci";
535 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
536
537 /*
538 * If the version is above 3.0, the capabilities of the 8-bit
539 * bus width and high speed are supported.
540 */
541 version = atmel_mci_get_version(plat->mci);
542 if ((version & 0xf00) >= 0x300) {
543 cfg->host_caps = MMC_MODE_8BIT |
544 MMC_MODE_HS | MMC_MODE_HS_52MHz;
545 }
546
547 cfg->host_caps |= MMC_MODE_4BIT;
548 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
549 cfg->f_min = priv->bus_clk_rate / (2 * 256);
550 cfg->f_max = priv->bus_clk_rate / 2;
551 }
552
553 static int atmel_mci_enable_clk(struct udevice *dev)
554 {
555 struct atmel_mci_priv *priv = dev_get_priv(dev);
556 struct clk clk;
557 ulong clk_rate;
558 int ret = 0;
559
560 ret = clk_get_by_index(dev, 0, &clk);
561 if (ret) {
562 ret = -EINVAL;
563 goto failed;
564 }
565
566 ret = clk_enable(&clk);
567 if (ret)
568 goto failed;
569
570 clk_rate = clk_get_rate(&clk);
571 if (!clk_rate) {
572 ret = -EINVAL;
573 goto failed;
574 }
575
576 priv->bus_clk_rate = clk_rate;
577
578 failed:
579 clk_free(&clk);
580
581 return ret;
582 }
583
584 static int atmel_mci_probe(struct udevice *dev)
585 {
586 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
587 struct atmel_mci_plat *plat = dev_get_plat(dev);
588 struct mmc *mmc;
589 int ret;
590
591 ret = atmel_mci_enable_clk(dev);
592 if (ret)
593 return ret;
594
595 plat->mci = dev_read_addr_ptr(dev);
596
597 atmel_mci_setup_cfg(dev);
598
599 mmc = &plat->mmc;
600 mmc->cfg = &plat->cfg;
601 mmc->dev = dev;
602 upriv->mmc = mmc;
603
604 atmel_mci_hw_init(dev);
605
606 return 0;
607 }
608
609 static int atmel_mci_bind(struct udevice *dev)
610 {
611 struct atmel_mci_plat *plat = dev_get_plat(dev);
612
613 return mmc_bind(dev, &plat->mmc, &plat->cfg);
614 }
615
616 static const struct udevice_id atmel_mci_ids[] = {
617 { .compatible = "atmel,hsmci" },
618 { }
619 };
620
621 U_BOOT_DRIVER(atmel_mci) = {
622 .name = "atmel-mci",
623 .id = UCLASS_MMC,
624 .of_match = atmel_mci_ids,
625 .bind = atmel_mci_bind,
626 .probe = atmel_mci_probe,
627 .plat_auto = sizeof(struct atmel_mci_plat),
628 .priv_auto = sizeof(struct atmel_mci_priv),
629 .ops = &atmel_mci_mmc_ops,
630 };
631 #endif
632