1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Porting to u-boot:
4 *
5 * (C) Copyright 2011
6 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
7 *
8 * Copyright (C) 2008-2009 MontaVista Software Inc.
9 * Copyright (C) 2008-2009 Texas Instruments Inc
10 *
11 * Based on the LCD driver for TI Avalanche processors written by
12 * Ajay Singh and Shalom Hai.
13 */
14
15 #include <common.h>
16 #include <log.h>
17 #include <malloc.h>
18 #include <memalign.h>
19 #include <video_fb.h>
20 #include <asm/global_data.h>
21 #include <linux/delay.h>
22 #include <linux/list.h>
23 #include <linux/fb.h>
24
25 #include <linux/errno.h>
26 #include <asm/io.h>
27 #include <asm/arch/hardware.h>
28
29 #include "videomodes.h"
30 #include "da8xx-fb.h"
31
32 #if !defined(DA8XX_LCD_CNTL_BASE)
33 #define DA8XX_LCD_CNTL_BASE DAVINCI_LCD_CNTL_BASE
34 #endif
35
36 #define DRIVER_NAME "da8xx_lcdc"
37
38 #define LCD_VERSION_1 1
39 #define LCD_VERSION_2 2
40
41 /* LCD Status Register */
42 #define LCD_END_OF_FRAME1 (1 << 9)
43 #define LCD_END_OF_FRAME0 (1 << 8)
44 #define LCD_PL_LOAD_DONE (1 << 6)
45 #define LCD_FIFO_UNDERFLOW (1 << 5)
46 #define LCD_SYNC_LOST (1 << 2)
47
48 /* LCD DMA Control Register */
49 #define LCD_DMA_BURST_SIZE(x) ((x) << 4)
50 #define LCD_DMA_BURST_1 0x0
51 #define LCD_DMA_BURST_2 0x1
52 #define LCD_DMA_BURST_4 0x2
53 #define LCD_DMA_BURST_8 0x3
54 #define LCD_DMA_BURST_16 0x4
55 #define LCD_V1_END_OF_FRAME_INT_ENA (1 << 2)
56 #define LCD_V2_END_OF_FRAME0_INT_ENA (1 << 8)
57 #define LCD_V2_END_OF_FRAME1_INT_ENA (1 << 9)
58 #define LCD_DUAL_FRAME_BUFFER_ENABLE (1 << 0)
59
60 #define LCD_V2_TFT_24BPP_MODE (1 << 25)
61 #define LCD_V2_TFT_24BPP_UNPACK (1 << 26)
62
63 /* LCD Control Register */
64 #define LCD_CLK_DIVISOR(x) ((x) << 8)
65 #define LCD_RASTER_MODE 0x01
66
67 /* LCD Raster Control Register */
68 #define LCD_PALETTE_LOAD_MODE(x) ((x) << 20)
69 #define PALETTE_AND_DATA 0x00
70 #define PALETTE_ONLY 0x01
71 #define DATA_ONLY 0x02
72
73 #define LCD_MONO_8BIT_MODE (1 << 9)
74 #define LCD_RASTER_ORDER (1 << 8)
75 #define LCD_TFT_MODE (1 << 7)
76 #define LCD_V1_UNDERFLOW_INT_ENA (1 << 6)
77 #define LCD_V2_UNDERFLOW_INT_ENA (1 << 5)
78 #define LCD_V1_PL_INT_ENA (1 << 4)
79 #define LCD_V2_PL_INT_ENA (1 << 6)
80 #define LCD_MONOCHROME_MODE (1 << 1)
81 #define LCD_RASTER_ENABLE (1 << 0)
82 #define LCD_TFT_ALT_ENABLE (1 << 23)
83 #define LCD_STN_565_ENABLE (1 << 24)
84 #define LCD_V2_DMA_CLK_EN (1 << 2)
85 #define LCD_V2_LIDD_CLK_EN (1 << 1)
86 #define LCD_V2_CORE_CLK_EN (1 << 0)
87 #define LCD_V2_LPP_B10 26
88 #define LCD_V2_TFT_24BPP_MODE (1 << 25)
89 #define LCD_V2_TFT_24BPP_UNPACK (1 << 26)
90
91 /* LCD Raster Timing 2 Register */
92 #define LCD_AC_BIAS_TRANSITIONS_PER_INT(x) ((x) << 16)
93 #define LCD_AC_BIAS_FREQUENCY(x) ((x) << 8)
94 #define LCD_SYNC_CTRL (1 << 25)
95 #define LCD_SYNC_EDGE (1 << 24)
96 #define LCD_INVERT_PIXEL_CLOCK (1 << 22)
97 #define LCD_INVERT_LINE_CLOCK (1 << 21)
98 #define LCD_INVERT_FRAME_CLOCK (1 << 20)
99
100 /* Clock registers available only on Version 2 */
101 #define LCD_CLK_MAIN_RESET (1 << 3)
102 /* LCD Block */
103 struct da8xx_lcd_regs {
104 u32 revid;
105 u32 ctrl;
106 u32 stat;
107 u32 lidd_ctrl;
108 u32 lidd_cs0_conf;
109 u32 lidd_cs0_addr;
110 u32 lidd_cs0_data;
111 u32 lidd_cs1_conf;
112 u32 lidd_cs1_addr;
113 u32 lidd_cs1_data;
114 u32 raster_ctrl;
115 u32 raster_timing_0;
116 u32 raster_timing_1;
117 u32 raster_timing_2;
118 u32 raster_subpanel;
119 u32 reserved;
120 u32 dma_ctrl;
121 u32 dma_frm_buf_base_addr_0;
122 u32 dma_frm_buf_ceiling_addr_0;
123 u32 dma_frm_buf_base_addr_1;
124 u32 dma_frm_buf_ceiling_addr_1;
125 u32 resv1;
126 u32 raw_stat;
127 u32 masked_stat;
128 u32 int_ena_set;
129 u32 int_ena_clr;
130 u32 end_of_int_ind;
131 /* Clock registers available only on Version 2 */
132 u32 clk_ena;
133 u32 clk_reset;
134 };
135
136 #define LCD_NUM_BUFFERS 1
137
138 #define WSI_TIMEOUT 50
139 #define PALETTE_SIZE 256
140 #define LEFT_MARGIN 64
141 #define RIGHT_MARGIN 64
142 #define UPPER_MARGIN 32
143 #define LOWER_MARGIN 32
144 #define WAIT_FOR_FRAME_DONE true
145 #define NO_WAIT_FOR_FRAME_DONE false
146
147 #define calc_fbsize() (panel.plnSizeX * panel.plnSizeY * panel.gdfBytesPP)
148
149 static struct da8xx_lcd_regs *da8xx_fb_reg_base;
150
151 DECLARE_GLOBAL_DATA_PTR;
152
153 /* graphics setup */
154 static GraphicDevice gpanel;
155 static const struct da8xx_panel *lcd_panel;
156 static struct fb_info *da8xx_fb_info;
157 static int bits_x_pixel;
158 static unsigned int lcd_revision;
159 const struct lcd_ctrl_config *da8xx_lcd_cfg;
160
lcdc_read(u32 * addr)161 static inline unsigned int lcdc_read(u32 *addr)
162 {
163 return (unsigned int)readl(addr);
164 }
165
lcdc_write(unsigned int val,u32 * addr)166 static inline void lcdc_write(unsigned int val, u32 *addr)
167 {
168 writel(val, addr);
169 }
170
171 struct da8xx_fb_par {
172 u32 p_palette_base;
173 unsigned char *v_palette_base;
174 dma_addr_t vram_phys;
175 unsigned long vram_size;
176 void *vram_virt;
177 unsigned int dma_start;
178 unsigned int dma_end;
179 struct clk *lcdc_clk;
180 int irq;
181 unsigned short pseudo_palette[16];
182 unsigned int palette_sz;
183 unsigned int pxl_clk;
184 int blank;
185 int vsync_flag;
186 int vsync_timeout;
187 };
188
189
190 /* Variable Screen Information */
191 static struct fb_var_screeninfo da8xx_fb_var = {
192 .xoffset = 0,
193 .yoffset = 0,
194 .transp = {0, 0, 0},
195 .nonstd = 0,
196 .activate = 0,
197 .height = -1,
198 .width = -1,
199 .pixclock = 46666, /* 46us - AUO display */
200 .accel_flags = 0,
201 .left_margin = LEFT_MARGIN,
202 .right_margin = RIGHT_MARGIN,
203 .upper_margin = UPPER_MARGIN,
204 .lower_margin = LOWER_MARGIN,
205 .sync = 0,
206 .vmode = FB_VMODE_NONINTERLACED
207 };
208
209 static struct fb_fix_screeninfo da8xx_fb_fix = {
210 .id = "DA8xx FB Drv",
211 .type = FB_TYPE_PACKED_PIXELS,
212 .type_aux = 0,
213 .visual = FB_VISUAL_PSEUDOCOLOR,
214 .xpanstep = 0,
215 .ypanstep = 1,
216 .ywrapstep = 0,
217 .accel = FB_ACCEL_NONE
218 };
219
220 /* Enable the Raster Engine of the LCD Controller */
lcd_enable_raster(void)221 static inline void lcd_enable_raster(void)
222 {
223 u32 reg;
224
225 /* Put LCDC in reset for several cycles */
226 if (lcd_revision == LCD_VERSION_2)
227 lcdc_write(LCD_CLK_MAIN_RESET,
228 &da8xx_fb_reg_base->clk_reset);
229
230 udelay(1000);
231 /* Bring LCDC out of reset */
232 if (lcd_revision == LCD_VERSION_2)
233 lcdc_write(0,
234 &da8xx_fb_reg_base->clk_reset);
235
236 udelay(1000);
237
238 reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
239 if (!(reg & LCD_RASTER_ENABLE))
240 lcdc_write(reg | LCD_RASTER_ENABLE,
241 &da8xx_fb_reg_base->raster_ctrl);
242 }
243
244 /* Disable the Raster Engine of the LCD Controller */
lcd_disable_raster(bool wait_for_frame_done)245 static inline void lcd_disable_raster(bool wait_for_frame_done)
246 {
247 u32 reg;
248 u32 loop_cnt = 0;
249 u32 stat;
250 u32 i = 0;
251
252 if (wait_for_frame_done)
253 loop_cnt = 5000;
254
255 reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
256 if (reg & LCD_RASTER_ENABLE)
257 lcdc_write(reg & ~LCD_RASTER_ENABLE,
258 &da8xx_fb_reg_base->raster_ctrl);
259
260 /* Wait for the current frame to complete */
261 do {
262 if (lcd_revision == LCD_VERSION_1)
263 stat = lcdc_read(&da8xx_fb_reg_base->stat);
264 else
265 stat = lcdc_read(&da8xx_fb_reg_base->raw_stat);
266
267 mdelay(1);
268 } while (!(stat & 0x01) && (i++ < loop_cnt));
269
270 if (lcd_revision == LCD_VERSION_1)
271 lcdc_write(stat, &da8xx_fb_reg_base->stat);
272 else
273 lcdc_write(stat, &da8xx_fb_reg_base->raw_stat);
274
275 if ((loop_cnt != 0) && (i >= loop_cnt)) {
276 printf("LCD Controller timed out\n");
277 return;
278 }
279 }
280
lcd_blit(int load_mode,struct da8xx_fb_par * par)281 static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
282 {
283 u32 start;
284 u32 end;
285 u32 reg_ras;
286 u32 reg_dma;
287 u32 reg_int;
288
289 /* init reg to clear PLM (loading mode) fields */
290 reg_ras = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
291 reg_ras &= ~(3 << 20);
292
293 reg_dma = lcdc_read(&da8xx_fb_reg_base->dma_ctrl);
294
295 if (load_mode == LOAD_DATA) {
296 start = par->dma_start;
297 end = par->dma_end;
298
299 reg_ras |= LCD_PALETTE_LOAD_MODE(DATA_ONLY);
300 if (lcd_revision == LCD_VERSION_1) {
301 reg_dma |= LCD_V1_END_OF_FRAME_INT_ENA;
302 } else {
303 reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_set) |
304 LCD_V2_END_OF_FRAME0_INT_ENA |
305 LCD_V2_END_OF_FRAME1_INT_ENA |
306 LCD_V2_UNDERFLOW_INT_ENA | LCD_SYNC_LOST;
307 lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_set);
308 }
309
310 #if (LCD_NUM_BUFFERS == 2)
311 reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE;
312 lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
313 lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
314 lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_1);
315 lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
316 #else
317 reg_dma &= ~LCD_DUAL_FRAME_BUFFER_ENABLE;
318 lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
319 lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
320 lcdc_write(0, &da8xx_fb_reg_base->dma_frm_buf_base_addr_1);
321 lcdc_write(0, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
322 #endif
323
324 } else if (load_mode == LOAD_PALETTE) {
325 start = par->p_palette_base;
326 end = start + par->palette_sz - 1;
327
328 reg_ras |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY);
329 if (lcd_revision == LCD_VERSION_1) {
330 reg_ras |= LCD_V1_PL_INT_ENA;
331 } else {
332 reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_set) |
333 LCD_V2_PL_INT_ENA;
334 lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_set);
335 }
336
337 lcdc_write(start, &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
338 lcdc_write(end, &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
339 }
340
341 lcdc_write(reg_dma, &da8xx_fb_reg_base->dma_ctrl);
342 lcdc_write(reg_ras, &da8xx_fb_reg_base->raster_ctrl);
343
344 /*
345 * The Raster enable bit must be set after all other control fields are
346 * set.
347 */
348 lcd_enable_raster();
349 }
350
351 /* Configure the Burst Size of DMA */
lcd_cfg_dma(int burst_size)352 static int lcd_cfg_dma(int burst_size)
353 {
354 u32 reg;
355
356 reg = lcdc_read(&da8xx_fb_reg_base->dma_ctrl) & 0x00000001;
357 switch (burst_size) {
358 case 1:
359 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1);
360 break;
361 case 2:
362 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2);
363 break;
364 case 4:
365 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4);
366 break;
367 case 8:
368 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8);
369 break;
370 case 16:
371 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16);
372 break;
373 default:
374 return -EINVAL;
375 }
376 lcdc_write(reg, &da8xx_fb_reg_base->dma_ctrl);
377
378 return 0;
379 }
380
lcd_cfg_ac_bias(int period,int transitions_per_int)381 static void lcd_cfg_ac_bias(int period, int transitions_per_int)
382 {
383 u32 reg;
384
385 /* Set the AC Bias Period and Number of Transitions per Interrupt */
386 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2) & 0xFFF00000;
387 reg |= LCD_AC_BIAS_FREQUENCY(period) |
388 LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int);
389 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2);
390 }
391
lcd_cfg_horizontal_sync(int back_porch,int pulse_width,int front_porch)392 static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width,
393 int front_porch)
394 {
395 u32 reg;
396
397 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_0) & 0xf;
398 reg |= ((back_porch & 0xff) << 24)
399 | ((front_porch & 0xff) << 16)
400 | ((pulse_width & 0x3f) << 10);
401 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_0);
402 }
403
lcd_cfg_vertical_sync(int back_porch,int pulse_width,int front_porch)404 static void lcd_cfg_vertical_sync(int back_porch, int pulse_width,
405 int front_porch)
406 {
407 u32 reg;
408
409 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_1) & 0x3ff;
410 reg |= ((back_porch & 0xff) << 24)
411 | ((front_porch & 0xff) << 16)
412 | ((pulse_width & 0x3f) << 10);
413 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_1);
414 }
415
lcd_cfg_display(const struct lcd_ctrl_config * cfg)416 static int lcd_cfg_display(const struct lcd_ctrl_config *cfg)
417 {
418 u32 reg;
419 u32 reg_int;
420
421 reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & ~(LCD_TFT_MODE |
422 LCD_MONO_8BIT_MODE |
423 LCD_MONOCHROME_MODE);
424
425 switch (cfg->p_disp_panel->panel_shade) {
426 case MONOCHROME:
427 reg |= LCD_MONOCHROME_MODE;
428 if (cfg->mono_8bit_mode)
429 reg |= LCD_MONO_8BIT_MODE;
430 break;
431 case COLOR_ACTIVE:
432 reg |= LCD_TFT_MODE;
433 if (cfg->tft_alt_mode)
434 reg |= LCD_TFT_ALT_ENABLE;
435 break;
436
437 case COLOR_PASSIVE:
438 if (cfg->stn_565_mode)
439 reg |= LCD_STN_565_ENABLE;
440 break;
441
442 default:
443 return -EINVAL;
444 }
445
446 /* enable additional interrupts here */
447 if (lcd_revision == LCD_VERSION_1) {
448 reg |= LCD_V1_UNDERFLOW_INT_ENA;
449 } else {
450 reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_set) |
451 LCD_V2_UNDERFLOW_INT_ENA;
452 lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_set);
453 }
454
455 lcdc_write(reg, &da8xx_fb_reg_base->raster_ctrl);
456
457 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2);
458
459 if (cfg->sync_ctrl)
460 reg |= LCD_SYNC_CTRL;
461 else
462 reg &= ~LCD_SYNC_CTRL;
463
464 if (cfg->sync_edge)
465 reg |= LCD_SYNC_EDGE;
466 else
467 reg &= ~LCD_SYNC_EDGE;
468
469 if (cfg->invert_line_clock)
470 reg |= LCD_INVERT_LINE_CLOCK;
471 else
472 reg &= ~LCD_INVERT_LINE_CLOCK;
473
474 if (cfg->invert_frm_clock)
475 reg |= LCD_INVERT_FRAME_CLOCK;
476 else
477 reg &= ~LCD_INVERT_FRAME_CLOCK;
478
479 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2);
480
481 return 0;
482 }
483
lcd_cfg_frame_buffer(struct da8xx_fb_par * par,u32 width,u32 height,u32 bpp,u32 raster_order)484 static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height,
485 u32 bpp, u32 raster_order)
486 {
487 u32 reg;
488
489 /* Set the Panel Width */
490 /* Pixels per line = (PPL + 1)*16 */
491 if (lcd_revision == LCD_VERSION_1) {
492 /*
493 * 0x3F in bits 4..9 gives max horizontal resolution = 1024
494 * pixels
495 */
496 width &= 0x3f0;
497 } else {
498 /*
499 * 0x7F in bits 4..10 gives max horizontal resolution = 2048
500 * pixels.
501 */
502 width &= 0x7f0;
503 }
504 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_0);
505 reg &= 0xfffffc00;
506 if (lcd_revision == LCD_VERSION_1) {
507 reg |= ((width >> 4) - 1) << 4;
508 } else {
509 width = (width >> 4) - 1;
510 reg |= ((width & 0x3f) << 4) | ((width & 0x40) >> 3);
511 }
512 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_0);
513
514 /* Set the Panel Height */
515 /* Set bits 9:0 of Lines Per Pixel */
516 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_1);
517 reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00);
518 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_1);
519
520 /* Set bit 10 of Lines Per Pixel */
521 if (lcd_revision == LCD_VERSION_2) {
522 reg = lcdc_read(&da8xx_fb_reg_base->raster_timing_2);
523 reg |= ((height - 1) & 0x400) << 16;
524 lcdc_write(reg, &da8xx_fb_reg_base->raster_timing_2);
525 }
526
527 /* Set the Raster Order of the Frame Buffer */
528 reg = lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & ~(1 << 8);
529 if (raster_order)
530 reg |= LCD_RASTER_ORDER;
531
532 if (bpp == 24)
533 reg |= (LCD_TFT_MODE | LCD_V2_TFT_24BPP_MODE);
534 else if (bpp == 32)
535 reg |= (LCD_TFT_MODE | LCD_V2_TFT_24BPP_MODE
536 | LCD_V2_TFT_24BPP_UNPACK);
537
538 lcdc_write(reg, &da8xx_fb_reg_base->raster_ctrl);
539
540 switch (bpp) {
541 case 1:
542 case 2:
543 case 4:
544 case 16:
545 case 24:
546 case 32:
547 par->palette_sz = 16 * 2;
548 break;
549
550 case 8:
551 par->palette_sz = 256 * 2;
552 break;
553
554 default:
555 return -EINVAL;
556 }
557
558 return 0;
559 }
560
fb_setcolreg(unsigned regno,unsigned red,unsigned green,unsigned blue,unsigned transp,struct fb_info * info)561 static int fb_setcolreg(unsigned regno, unsigned red, unsigned green,
562 unsigned blue, unsigned transp,
563 struct fb_info *info)
564 {
565 struct da8xx_fb_par *par = info->par;
566 unsigned short *palette = (unsigned short *) par->v_palette_base;
567 u_short pal;
568 int update_hw = 0;
569
570 if (regno > 255)
571 return 1;
572
573 if (info->fix.visual == FB_VISUAL_DIRECTCOLOR)
574 return 1;
575
576 if (info->var.bits_per_pixel == 8) {
577 red >>= 4;
578 green >>= 8;
579 blue >>= 12;
580
581 pal = (red & 0x0f00);
582 pal |= (green & 0x00f0);
583 pal |= (blue & 0x000f);
584
585 if (palette[regno] != pal) {
586 update_hw = 1;
587 palette[regno] = pal;
588 }
589 } else if ((info->var.bits_per_pixel == 16) && regno < 16) {
590 red >>= (16 - info->var.red.length);
591 red <<= info->var.red.offset;
592
593 green >>= (16 - info->var.green.length);
594 green <<= info->var.green.offset;
595
596 blue >>= (16 - info->var.blue.length);
597 blue <<= info->var.blue.offset;
598
599 par->pseudo_palette[regno] = red | green | blue;
600
601 if (palette[0] != 0x4000) {
602 update_hw = 1;
603 palette[0] = 0x4000;
604 }
605 } else if (((info->var.bits_per_pixel == 32) && regno < 32) ||
606 ((info->var.bits_per_pixel == 24) && regno < 24)) {
607 red >>= (24 - info->var.red.length);
608 red <<= info->var.red.offset;
609
610 green >>= (24 - info->var.green.length);
611 green <<= info->var.green.offset;
612
613 blue >>= (24 - info->var.blue.length);
614 blue <<= info->var.blue.offset;
615
616 par->pseudo_palette[regno] = red | green | blue;
617
618 if (palette[0] != 0x4000) {
619 update_hw = 1;
620 palette[0] = 0x4000;
621 }
622 }
623
624 /* Update the palette in the h/w as needed. */
625 if (update_hw)
626 lcd_blit(LOAD_PALETTE, par);
627
628 return 0;
629 }
630
lcd_reset(struct da8xx_fb_par * par)631 static void lcd_reset(struct da8xx_fb_par *par)
632 {
633 /* Disable the Raster if previously Enabled */
634 lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
635
636 /* DMA has to be disabled */
637 lcdc_write(0, &da8xx_fb_reg_base->dma_ctrl);
638 lcdc_write(0, &da8xx_fb_reg_base->raster_ctrl);
639
640 if (lcd_revision == LCD_VERSION_2) {
641 lcdc_write(0, &da8xx_fb_reg_base->int_ena_set);
642 /* Write 1 to reset */
643 lcdc_write(LCD_CLK_MAIN_RESET, &da8xx_fb_reg_base->clk_reset);
644 lcdc_write(0, &da8xx_fb_reg_base->clk_reset);
645 }
646 }
647
lcd_calc_clk_divider(struct da8xx_fb_par * par)648 static void lcd_calc_clk_divider(struct da8xx_fb_par *par)
649 {
650 unsigned int lcd_clk, div;
651
652 /* Get clock from sysclk2 */
653 lcd_clk = clk_get(2);
654
655 div = lcd_clk / par->pxl_clk;
656 debug("LCD Clock: %d Divider: %d PixClk: %d\n",
657 lcd_clk, div, par->pxl_clk);
658
659 /* Configure the LCD clock divisor. */
660 lcdc_write(LCD_CLK_DIVISOR(div) |
661 (LCD_RASTER_MODE & 0x1), &da8xx_fb_reg_base->ctrl);
662
663 if (lcd_revision == LCD_VERSION_2)
664 lcdc_write(LCD_V2_DMA_CLK_EN | LCD_V2_LIDD_CLK_EN |
665 LCD_V2_CORE_CLK_EN,
666 &da8xx_fb_reg_base->clk_ena);
667 }
668
lcd_init(struct da8xx_fb_par * par,const struct lcd_ctrl_config * cfg,const struct da8xx_panel * panel)669 static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg,
670 const struct da8xx_panel *panel)
671 {
672 u32 bpp;
673 int ret = 0;
674
675 lcd_reset(par);
676
677 /* Calculate the divider */
678 lcd_calc_clk_divider(par);
679
680 if (panel->invert_pxl_clk)
681 lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_timing_2) |
682 LCD_INVERT_PIXEL_CLOCK),
683 &da8xx_fb_reg_base->raster_timing_2);
684 else
685 lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_timing_2) &
686 ~LCD_INVERT_PIXEL_CLOCK),
687 &da8xx_fb_reg_base->raster_timing_2);
688
689 /* Configure the DMA burst size. */
690 ret = lcd_cfg_dma(cfg->dma_burst_sz);
691 if (ret < 0)
692 return ret;
693
694 /* Configure the AC bias properties. */
695 lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt);
696
697 /* Configure the vertical and horizontal sync properties. */
698 lcd_cfg_vertical_sync(panel->vbp, panel->vsw, panel->vfp);
699 lcd_cfg_horizontal_sync(panel->hbp, panel->hsw, panel->hfp);
700
701 /* Configure for display */
702 ret = lcd_cfg_display(cfg);
703 if (ret < 0)
704 return ret;
705
706 if ((QVGA != cfg->p_disp_panel->panel_type) &&
707 (WVGA != cfg->p_disp_panel->panel_type))
708 return -EINVAL;
709
710 if (cfg->bpp <= cfg->p_disp_panel->max_bpp &&
711 cfg->bpp >= cfg->p_disp_panel->min_bpp)
712 bpp = cfg->bpp;
713 else
714 bpp = cfg->p_disp_panel->max_bpp;
715 if (bpp == 12)
716 bpp = 16;
717 ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->width,
718 (unsigned int)panel->height, bpp,
719 cfg->raster_order);
720 if (ret < 0)
721 return ret;
722
723 /* Configure FDD */
724 lcdc_write((lcdc_read(&da8xx_fb_reg_base->raster_ctrl) & 0xfff00fff) |
725 (cfg->fdd << 12), &da8xx_fb_reg_base->raster_ctrl);
726
727 return 0;
728 }
729
lcdc_dma_start(void)730 static void lcdc_dma_start(void)
731 {
732 struct da8xx_fb_par *par = da8xx_fb_info->par;
733 lcdc_write(par->dma_start,
734 &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
735 lcdc_write(par->dma_end,
736 &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
737 lcdc_write(0,
738 &da8xx_fb_reg_base->dma_frm_buf_base_addr_1);
739 lcdc_write(0,
740 &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_1);
741 }
742
lcdc_irq_handler_rev01(void)743 static u32 lcdc_irq_handler_rev01(void)
744 {
745 struct da8xx_fb_par *par = da8xx_fb_info->par;
746 u32 stat = lcdc_read(&da8xx_fb_reg_base->stat);
747 u32 reg_ras;
748
749 if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
750 debug("LCD_SYNC_LOST\n");
751 lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
752 lcdc_write(stat, &da8xx_fb_reg_base->stat);
753 lcd_enable_raster();
754 return LCD_SYNC_LOST;
755 } else if (stat & LCD_PL_LOAD_DONE) {
756 debug("LCD_PL_LOAD_DONE\n");
757 /*
758 * Must disable raster before changing state of any control bit.
759 * And also must be disabled before clearing the PL loading
760 * interrupt via the following write to the status register. If
761 * this is done after then one gets multiple PL done interrupts.
762 */
763 lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
764
765 lcdc_write(stat, &da8xx_fb_reg_base->stat);
766
767 /* Disable PL completion interrupt */
768 reg_ras = lcdc_read(&da8xx_fb_reg_base->raster_ctrl);
769 reg_ras &= ~LCD_V1_PL_INT_ENA;
770 lcdc_write(reg_ras, &da8xx_fb_reg_base->raster_ctrl);
771
772 /* Setup and start data loading mode */
773 lcd_blit(LOAD_DATA, par);
774 return LCD_PL_LOAD_DONE;
775 } else {
776 lcdc_write(stat, &da8xx_fb_reg_base->stat);
777
778 if (stat & LCD_END_OF_FRAME0)
779 debug("LCD_END_OF_FRAME0\n");
780
781 lcdc_write(par->dma_start,
782 &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
783 lcdc_write(par->dma_end,
784 &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
785 par->vsync_flag = 1;
786 return LCD_END_OF_FRAME0;
787 }
788 return stat;
789 }
790
lcdc_irq_handler_rev02(void)791 static u32 lcdc_irq_handler_rev02(void)
792 {
793 struct da8xx_fb_par *par = da8xx_fb_info->par;
794 u32 stat = lcdc_read(&da8xx_fb_reg_base->masked_stat);
795 u32 reg_int;
796
797 if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
798 debug("LCD_SYNC_LOST\n");
799 lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
800 lcdc_write(stat, &da8xx_fb_reg_base->masked_stat);
801 lcd_enable_raster();
802 lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind);
803 return LCD_SYNC_LOST;
804 } else if (stat & LCD_PL_LOAD_DONE) {
805 debug("LCD_PL_LOAD_DONE\n");
806 /*
807 * Must disable raster before changing state of any control bit.
808 * And also must be disabled before clearing the PL loading
809 * interrupt via the following write to the status register. If
810 * this is done after then one gets multiple PL done interrupts.
811 */
812 lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
813
814 lcdc_write(stat, &da8xx_fb_reg_base->masked_stat);
815
816 /* Disable PL completion interrupt */
817 reg_int = lcdc_read(&da8xx_fb_reg_base->int_ena_clr) |
818 (LCD_V2_PL_INT_ENA);
819 lcdc_write(reg_int, &da8xx_fb_reg_base->int_ena_clr);
820
821 /* Setup and start data loading mode */
822 lcd_blit(LOAD_DATA, par);
823 lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind);
824 return LCD_PL_LOAD_DONE;
825 } else {
826 lcdc_write(stat, &da8xx_fb_reg_base->masked_stat);
827
828 if (stat & LCD_END_OF_FRAME0)
829 debug("LCD_END_OF_FRAME0\n");
830
831 lcdc_write(par->dma_start,
832 &da8xx_fb_reg_base->dma_frm_buf_base_addr_0);
833 lcdc_write(par->dma_end,
834 &da8xx_fb_reg_base->dma_frm_buf_ceiling_addr_0);
835 par->vsync_flag = 1;
836 lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind);
837 return LCD_END_OF_FRAME0;
838 }
839 lcdc_write(0, &da8xx_fb_reg_base->end_of_int_ind);
840 return stat;
841 }
842
lcdc_irq_handler(void)843 static u32 lcdc_irq_handler(void)
844 {
845 if (lcd_revision == LCD_VERSION_1)
846 return lcdc_irq_handler_rev01();
847 else
848 return lcdc_irq_handler_rev02();
849 }
850
wait_for_event(u32 event)851 static u32 wait_for_event(u32 event)
852 {
853 u32 timeout = 50000;
854 u32 ret;
855
856 do {
857 ret = lcdc_irq_handler();
858 udelay(1000);
859 --timeout;
860 } while (!(ret & event) && timeout);
861
862 if (!(ret & event)) {
863 printf("%s: event %d not hit\n", __func__, event);
864 return -1;
865 }
866
867 return 0;
868
869 }
870
video_hw_init(void)871 void *video_hw_init(void)
872 {
873 struct da8xx_fb_par *par;
874 u32 size;
875 u32 rev;
876 char *p;
877
878 if (!lcd_panel) {
879 printf("Display not initialized\n");
880 return NULL;
881 }
882 gpanel.winSizeX = lcd_panel->width;
883 gpanel.winSizeY = lcd_panel->height;
884 gpanel.plnSizeX = lcd_panel->width;
885 gpanel.plnSizeY = lcd_panel->height;
886
887 switch (bits_x_pixel) {
888 case 32:
889 gpanel.gdfBytesPP = 4;
890 gpanel.gdfIndex = GDF_32BIT_X888RGB;
891 break;
892 case 24:
893 gpanel.gdfBytesPP = 4;
894 gpanel.gdfIndex = GDF_32BIT_X888RGB;
895 break;
896 case 16:
897 gpanel.gdfBytesPP = 2;
898 gpanel.gdfIndex = GDF_16BIT_565RGB;
899 break;
900 default:
901 gpanel.gdfBytesPP = 1;
902 gpanel.gdfIndex = GDF__8BIT_INDEX;
903 break;
904 }
905
906 da8xx_fb_reg_base = (struct da8xx_lcd_regs *)DA8XX_LCD_CNTL_BASE;
907
908 /* Determine LCD IP Version */
909 rev = lcdc_read(&da8xx_fb_reg_base->revid);
910 switch (rev) {
911 case 0x4C100102:
912 lcd_revision = LCD_VERSION_1;
913 break;
914 case 0x4F200800:
915 case 0x4F201000:
916 lcd_revision = LCD_VERSION_2;
917 break;
918 default:
919 printf("Unknown PID Reg value 0x%x, defaulting to LCD revision 1\n",
920 rev);
921 lcd_revision = LCD_VERSION_1;
922 break;
923 }
924
925 debug("rev: 0x%x Resolution: %dx%d %d\n", rev,
926 gpanel.winSizeX,
927 gpanel.winSizeY,
928 da8xx_lcd_cfg->bpp);
929
930 size = sizeof(struct fb_info) + sizeof(struct da8xx_fb_par);
931 da8xx_fb_info = malloc_cache_aligned(size);
932 debug("da8xx_fb_info at %x\n", (unsigned int)da8xx_fb_info);
933
934 if (!da8xx_fb_info) {
935 printf("Memory allocation failed for fb_info\n");
936 return NULL;
937 }
938 memset(da8xx_fb_info, 0, size);
939 p = (char *)da8xx_fb_info;
940 da8xx_fb_info->par = p + sizeof(struct fb_info);
941 debug("da8xx_par at %x\n", (unsigned int)da8xx_fb_info->par);
942
943 par = da8xx_fb_info->par;
944 par->pxl_clk = lcd_panel->pxl_clk;
945
946 if (lcd_init(par, da8xx_lcd_cfg, lcd_panel) < 0) {
947 printf("lcd_init failed\n");
948 goto err_release_fb;
949 }
950
951 /* allocate frame buffer */
952 par->vram_size = lcd_panel->width * lcd_panel->height *
953 da8xx_lcd_cfg->bpp;
954 par->vram_size = par->vram_size * LCD_NUM_BUFFERS / 8;
955
956 par->vram_virt = malloc_cache_aligned(par->vram_size);
957
958 par->vram_phys = (dma_addr_t) par->vram_virt;
959 debug("Requesting 0x%x bytes for framebuffer at 0x%x\n",
960 (unsigned int)par->vram_size,
961 (unsigned int)par->vram_virt);
962 if (!par->vram_virt) {
963 printf("GLCD: malloc for frame buffer failed\n");
964 goto err_release_fb;
965 }
966 gd->fb_base = (int)par->vram_virt;
967
968 gpanel.frameAdrs = (unsigned int)par->vram_virt;
969 da8xx_fb_info->screen_base = (char *) par->vram_virt;
970 da8xx_fb_fix.smem_start = gpanel.frameAdrs;
971 da8xx_fb_fix.smem_len = par->vram_size;
972 da8xx_fb_fix.line_length = (lcd_panel->width * da8xx_lcd_cfg->bpp) / 8;
973
974 par->dma_start = par->vram_phys;
975 par->dma_end = par->dma_start + lcd_panel->height *
976 da8xx_fb_fix.line_length - 1;
977
978 /* allocate palette buffer */
979 par->v_palette_base = malloc_cache_aligned(PALETTE_SIZE);
980 if (!par->v_palette_base) {
981 printf("GLCD: malloc for palette buffer failed\n");
982 goto err_release_fb_mem;
983 }
984 memset(par->v_palette_base, 0, PALETTE_SIZE);
985 par->p_palette_base = (unsigned int)par->v_palette_base;
986
987 /* Initialize par */
988 da8xx_fb_info->var.bits_per_pixel = da8xx_lcd_cfg->bpp;
989
990 da8xx_fb_var.xres = lcd_panel->width;
991 da8xx_fb_var.xres_virtual = lcd_panel->width;
992
993 da8xx_fb_var.yres = lcd_panel->height;
994 da8xx_fb_var.yres_virtual = lcd_panel->height * LCD_NUM_BUFFERS;
995
996 da8xx_fb_var.grayscale =
997 da8xx_lcd_cfg->p_disp_panel->panel_shade == MONOCHROME ? 1 : 0;
998 da8xx_fb_var.bits_per_pixel = da8xx_lcd_cfg->bpp;
999
1000 da8xx_fb_var.hsync_len = lcd_panel->hsw;
1001 da8xx_fb_var.vsync_len = lcd_panel->vsw;
1002
1003 /* Initialize fbinfo */
1004 da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT;
1005 da8xx_fb_info->fix = da8xx_fb_fix;
1006 da8xx_fb_info->var = da8xx_fb_var;
1007 da8xx_fb_info->pseudo_palette = par->pseudo_palette;
1008 da8xx_fb_info->fix.visual = (da8xx_fb_info->var.bits_per_pixel <= 8) ?
1009 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
1010
1011 /* Clear interrupt */
1012 memset((void *)par->vram_virt, 0, par->vram_size);
1013 lcd_disable_raster(NO_WAIT_FOR_FRAME_DONE);
1014 if (lcd_revision == LCD_VERSION_1)
1015 lcdc_write(0xFFFF, &da8xx_fb_reg_base->stat);
1016 else
1017 lcdc_write(0xFFFF, &da8xx_fb_reg_base->masked_stat);
1018 debug("Palette at 0x%x size %d\n", par->p_palette_base,
1019 par->palette_sz);
1020 lcdc_dma_start();
1021
1022 /* Load a default palette */
1023 fb_setcolreg(0, 0, 0, 0, 0xffff, da8xx_fb_info);
1024
1025 /* Check that the palette is loaded */
1026 wait_for_event(LCD_PL_LOAD_DONE);
1027
1028 /* Wait until DMA is working */
1029 wait_for_event(LCD_END_OF_FRAME0);
1030
1031 return (void *)&gpanel;
1032
1033 err_release_fb_mem:
1034 free(par->vram_virt);
1035
1036 err_release_fb:
1037 free(da8xx_fb_info);
1038
1039 return NULL;
1040 }
1041
da8xx_video_init(const struct da8xx_panel * panel,const struct lcd_ctrl_config * lcd_cfg,int bits_pixel)1042 void da8xx_video_init(const struct da8xx_panel *panel,
1043 const struct lcd_ctrl_config *lcd_cfg, int bits_pixel)
1044 {
1045 lcd_panel = panel;
1046 da8xx_lcd_cfg = lcd_cfg;
1047 bits_x_pixel = bits_pixel;
1048 }
1049