1 /*
2 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
3 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include <assert.h>
9 #include <errno.h>
10 #include <inttypes.h>
11 #include <stddef.h>
12 #include <string.h>
13
14 #include <platform_def.h>
15
16 #include <arch.h>
17 #include <arch_helpers.h>
18 #include <bl31/bl31.h>
19 #include <common/bl_common.h>
20 #include <common/debug.h>
21 #include <cortex_a57.h>
22 #include <denver.h>
23 #include <drivers/console.h>
24 #include <lib/mmio.h>
25 #include <lib/utils.h>
26 #include <lib/utils_def.h>
27 #include <plat/common/platform.h>
28
29 #include <memctrl.h>
30 #include <profiler.h>
31 #include <smmu.h>
32 #include <tegra_def.h>
33 #include <tegra_platform.h>
34 #include <tegra_private.h>
35
36 /* length of Trusty's input parameters (in bytes) */
37 #define TRUSTY_PARAMS_LEN_BYTES (4096*2)
38
39 /*******************************************************************************
40 * Declarations of linker defined symbols which will help us find the layout
41 * of trusted SRAM
42 ******************************************************************************/
43 IMPORT_SYM(uint64_t, __RW_START__, BL31_RW_START);
44
45 extern uint64_t tegra_bl31_phys_base;
46
47 static entry_point_info_t bl33_image_ep_info, bl32_image_ep_info;
48 static plat_params_from_bl2_t plat_bl31_params_from_bl2 = {
49 .tzdram_size = TZDRAM_SIZE
50 };
51 #ifdef SPD_trusty
52 static aapcs64_params_t bl32_args;
53 #endif
54
55 /*******************************************************************************
56 * This variable holds the non-secure image entry address
57 ******************************************************************************/
58 extern uint64_t ns_image_entrypoint;
59
60 /*******************************************************************************
61 * Return a pointer to the 'entry_point_info' structure of the next image for
62 * security state specified. BL33 corresponds to the non-secure image type
63 * while BL32 corresponds to the secure image type.
64 ******************************************************************************/
bl31_plat_get_next_image_ep_info(uint32_t type)65 entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
66 {
67 entry_point_info_t *ep = NULL;
68
69 /* return BL32 entry point info if it is valid */
70 if (type == NON_SECURE) {
71 ep = &bl33_image_ep_info;
72 } else if ((type == SECURE) && (bl32_image_ep_info.pc != 0U)) {
73 ep = &bl32_image_ep_info;
74 }
75
76 return ep;
77 }
78
79 /*******************************************************************************
80 * Return a pointer to the 'plat_params_from_bl2_t' structure. The BL2 image
81 * passes this platform specific information.
82 ******************************************************************************/
bl31_get_plat_params(void)83 plat_params_from_bl2_t *bl31_get_plat_params(void)
84 {
85 return &plat_bl31_params_from_bl2;
86 }
87
88 /*******************************************************************************
89 * Perform any BL31 specific platform actions. Populate the BL33 and BL32 image
90 * info.
91 ******************************************************************************/
bl31_early_platform_setup2(u_register_t arg0,u_register_t arg1,u_register_t arg2,u_register_t arg3)92 void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
93 u_register_t arg2, u_register_t arg3)
94 {
95 struct tegra_bl31_params *arg_from_bl2 = (struct tegra_bl31_params *) arg0;
96 plat_params_from_bl2_t *plat_params = (plat_params_from_bl2_t *)arg1;
97 int32_t ret;
98
99 /*
100 * For RESET_TO_BL31 systems, BL31 is the first bootloader to run so
101 * there's no argument to relay from a previous bootloader. Platforms
102 * might use custom ways to get arguments.
103 */
104 if (arg_from_bl2 == NULL) {
105 arg_from_bl2 = plat_get_bl31_params();
106 }
107 if (plat_params == NULL) {
108 plat_params = plat_get_bl31_plat_params();
109 }
110
111 /*
112 * Copy BL3-3, BL3-2 entry point information.
113 * They are stored in Secure RAM, in BL2's address space.
114 */
115 assert(arg_from_bl2 != NULL);
116 assert(arg_from_bl2->bl33_ep_info != NULL);
117 bl33_image_ep_info = *arg_from_bl2->bl33_ep_info;
118
119 if (arg_from_bl2->bl32_ep_info != NULL) {
120 bl32_image_ep_info = *arg_from_bl2->bl32_ep_info;
121 #ifdef SPD_trusty
122 /* save BL32 boot parameters */
123 memcpy(&bl32_args, &arg_from_bl2->bl32_ep_info->args, sizeof(bl32_args));
124 #endif
125 }
126
127 /*
128 * Parse platform specific parameters
129 */
130 assert(plat_params != NULL);
131 plat_bl31_params_from_bl2.tzdram_base = plat_params->tzdram_base;
132 plat_bl31_params_from_bl2.tzdram_size = plat_params->tzdram_size;
133 plat_bl31_params_from_bl2.uart_id = plat_params->uart_id;
134 plat_bl31_params_from_bl2.l2_ecc_parity_prot_dis = plat_params->l2_ecc_parity_prot_dis;
135 plat_bl31_params_from_bl2.sc7entry_fw_size = plat_params->sc7entry_fw_size;
136 plat_bl31_params_from_bl2.sc7entry_fw_base = plat_params->sc7entry_fw_base;
137
138 /*
139 * It is very important that we run either from TZDRAM or TZSRAM base.
140 * Add an explicit check here.
141 */
142 if ((plat_bl31_params_from_bl2.tzdram_base != (uint64_t)BL31_BASE) &&
143 (TEGRA_TZRAM_BASE != BL31_BASE)) {
144 panic();
145 }
146
147 /*
148 * Enable console for the platform
149 */
150 plat_enable_console(plat_params->uart_id);
151
152 /*
153 * The previous bootloader passes the base address of the shared memory
154 * location to store the boot profiler logs. Sanity check the
155 * address and initialise the profiler library, if it looks ok.
156 */
157 ret = bl31_check_ns_address(plat_params->boot_profiler_shmem_base,
158 PROFILER_SIZE_BYTES);
159 if (ret == (int32_t)0) {
160
161 /* store the membase for the profiler lib */
162 plat_bl31_params_from_bl2.boot_profiler_shmem_base =
163 plat_params->boot_profiler_shmem_base;
164
165 /* initialise the profiler library */
166 boot_profiler_init(plat_params->boot_profiler_shmem_base,
167 TEGRA_TMRUS_BASE);
168 }
169
170 /*
171 * Add timestamp for platform early setup entry.
172 */
173 boot_profiler_add_record("[TF] early setup entry");
174
175 /*
176 * Initialize delay timer
177 */
178 tegra_delay_timer_init();
179
180 /* Early platform setup for Tegra SoCs */
181 plat_early_platform_setup();
182
183 /*
184 * Add timestamp for platform early setup exit.
185 */
186 boot_profiler_add_record("[TF] early setup exit");
187
188 INFO("BL3-1: Boot CPU: %s Processor [%lx]\n",
189 (((read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK)
190 == DENVER_IMPL) ? "Denver" : "ARM", read_mpidr());
191 }
192
193 #ifdef SPD_trusty
plat_trusty_set_boot_args(aapcs64_params_t * args)194 void plat_trusty_set_boot_args(aapcs64_params_t *args)
195 {
196 /*
197 * arg0 = TZDRAM aperture available for BL32
198 * arg1 = BL32 boot params
199 * arg2 = EKS Blob Length
200 * arg3 = Boot Profiler Carveout Base
201 */
202 args->arg0 = bl32_args.arg0;
203 args->arg1 = bl32_args.arg2;
204
205 /* update EKS size */
206 args->arg2 = bl32_args.arg4;
207
208 /* Profiler Carveout Base */
209 args->arg3 = bl32_args.arg5;
210 }
211 #endif
212
213 /*******************************************************************************
214 * Initialize the gic, configure the SCR.
215 ******************************************************************************/
bl31_platform_setup(void)216 void bl31_platform_setup(void)
217 {
218 /*
219 * Add timestamp for platform setup entry.
220 */
221 boot_profiler_add_record("[TF] plat setup entry");
222
223 /* Initialize the gic cpu and distributor interfaces */
224 plat_gic_setup();
225
226 /*
227 * Setup secondary CPU POR infrastructure.
228 */
229 plat_secondary_setup();
230
231 /*
232 * Initial Memory Controller configuration.
233 */
234 tegra_memctrl_setup();
235
236 /*
237 * Late setup handler to allow platforms to performs additional
238 * functionality.
239 * This handler gets called with MMU enabled.
240 */
241 plat_late_platform_setup();
242
243 /*
244 * Add timestamp for platform setup exit.
245 */
246 boot_profiler_add_record("[TF] plat setup exit");
247
248 INFO("BL3-1: Tegra platform setup complete\n");
249 }
250
251 /*******************************************************************************
252 * Perform any BL3-1 platform runtime setup prior to BL3-1 cold boot exit
253 ******************************************************************************/
bl31_plat_runtime_setup(void)254 void bl31_plat_runtime_setup(void)
255 {
256 /*
257 * Platform specific runtime setup
258 */
259 plat_runtime_setup();
260
261 /*
262 * Add final timestamp before exiting BL31.
263 */
264 boot_profiler_add_record("[TF] bl31 exit");
265 boot_profiler_deinit();
266 }
267
268 /*******************************************************************************
269 * Perform the very early platform specific architectural setup here. At the
270 * moment this only intializes the mmu in a quick and dirty way.
271 ******************************************************************************/
bl31_plat_arch_setup(void)272 void bl31_plat_arch_setup(void)
273 {
274 uint64_t rw_start = BL31_RW_START;
275 uint64_t rw_size = BL_END - BL31_RW_START;
276 uint64_t rodata_start = BL_RO_DATA_BASE;
277 uint64_t rodata_size = BL_RO_DATA_END - BL_RO_DATA_BASE;
278 uint64_t code_base = BL_CODE_BASE;
279 uint64_t code_size = BL_CODE_END - BL_CODE_BASE;
280 const mmap_region_t *plat_mmio_map = NULL;
281 const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
282
283 /*
284 * Add timestamp for arch setup entry.
285 */
286 boot_profiler_add_record("[TF] arch setup entry");
287
288 /* add MMIO space */
289 plat_mmio_map = plat_get_mmio_map();
290 if (plat_mmio_map != NULL) {
291 mmap_add(plat_mmio_map);
292 } else {
293 WARN("MMIO map not available\n");
294 }
295
296 /* add memory regions */
297 mmap_add_region(rw_start, rw_start,
298 rw_size,
299 MT_MEMORY | MT_RW | MT_SECURE);
300 mmap_add_region(rodata_start, rodata_start,
301 rodata_size,
302 MT_RO_DATA | MT_SECURE);
303 mmap_add_region(code_base, code_base,
304 code_size,
305 MT_CODE | MT_SECURE);
306
307 /* map TZDRAM used by BL31 as coherent memory */
308 if (TEGRA_TZRAM_BASE == tegra_bl31_phys_base) {
309 mmap_add_region(params_from_bl2->tzdram_base,
310 params_from_bl2->tzdram_base,
311 BL31_SIZE,
312 MT_DEVICE | MT_RW | MT_SECURE);
313 }
314
315 /* set up translation tables */
316 init_xlat_tables();
317
318 /* enable the MMU */
319 enable_mmu_el3(0);
320
321 /*
322 * Add timestamp for arch setup exit.
323 */
324 boot_profiler_add_record("[TF] arch setup exit");
325
326 INFO("BL3-1: Tegra: MMU enabled\n");
327 }
328
329 /*******************************************************************************
330 * Check if the given NS DRAM range is valid
331 ******************************************************************************/
bl31_check_ns_address(uint64_t base,uint64_t size_in_bytes)332 int32_t bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes)
333 {
334 uint64_t end = base + size_in_bytes - U(1);
335
336 /*
337 * Sanity check the input values
338 */
339 if ((base == 0U) || (size_in_bytes == 0U)) {
340 ERROR("NS address 0x%" PRIx64 " (%" PRId64 " bytes) is invalid\n",
341 base, size_in_bytes);
342 return -EINVAL;
343 }
344
345 /*
346 * Check if the NS DRAM address is valid
347 */
348 if ((base < TEGRA_DRAM_BASE) || (base >= TEGRA_DRAM_END) ||
349 (end > TEGRA_DRAM_END)) {
350
351 ERROR("NS address 0x%" PRIx64 " is out-of-bounds!\n", base);
352 return -EFAULT;
353 }
354
355 /*
356 * TZDRAM aperture contains the BL31 and BL32 images, so we need
357 * to check if the NS DRAM range overlaps the TZDRAM aperture.
358 */
359 if ((base < (uint64_t)TZDRAM_END) && (end > tegra_bl31_phys_base)) {
360 ERROR("NS address 0x%" PRIx64 " overlaps TZDRAM!\n", base);
361 return -ENOTSUP;
362 }
363
364 /* valid NS address */
365 return 0;
366 }
367