1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2013 Gateworks Corporation
4 *
5 * Author: Tim Harvey <tharvey@gateworks.com>
6 */
7
8 #include <common.h>
9 #include <init.h>
10 #include <log.h>
11 #include <net.h>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/crm_regs.h>
14 #include <asm/arch/iomux.h>
15 #include <asm/arch/mx6-pins.h>
16 #include <asm/arch/mxc_hdmi.h>
17 #include <asm/arch/sys_proto.h>
18 #include <asm/global_data.h>
19 #include <asm/gpio.h>
20 #include <asm/mach-imx/boot_mode.h>
21 #include <asm/mach-imx/sata.h>
22 #include <asm/mach-imx/spi.h>
23 #include <asm/mach-imx/video.h>
24 #include <asm/io.h>
25 #include <asm/setup.h>
26 #include <dm.h>
27 #include <dm/platform_data/serial_mxc.h>
28 #include <env.h>
29 #include <hwconfig.h>
30 #include <i2c.h>
31 #include <fdt_support.h>
32 #include <fsl_esdhc_imx.h>
33 #include <jffs2/load_kernel.h>
34 #include <linux/ctype.h>
35 #include <miiphy.h>
36 #include <mtd_node.h>
37 #include <netdev.h>
38 #include <pci.h>
39 #include <linux/delay.h>
40 #include <linux/libfdt.h>
41 #include <power/pmic.h>
42 #include <power/ltc3676_pmic.h>
43 #include <power/pfuze100_pmic.h>
44 #include <fdt_support.h>
45 #include <jffs2/load_kernel.h>
46 #include <spi_flash.h>
47
48 #include "gsc.h"
49 #include "common.h"
50
51 DECLARE_GLOBAL_DATA_PTR;
52
53
54 /*
55 * EEPROM board info struct populated by read_eeprom so that we only have to
56 * read it once.
57 */
58 struct ventana_board_info ventana_info;
59
60 static int board_type;
61
62 /* ENET */
63 static iomux_v3_cfg_t const enet_pads[] = {
64 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
65 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
66 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
67 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
68 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
69 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
70 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
71 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
72 MUX_PAD_CTRL(ENET_PAD_CTRL)),
73 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
74 MUX_PAD_CTRL(ENET_PAD_CTRL)),
75 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
76 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
77 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
78 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
79 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
80 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
81 MUX_PAD_CTRL(ENET_PAD_CTRL)),
82 /* PHY nRST */
83 IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | DIO_PAD_CFG),
84 };
85
86 #ifdef CONFIG_CMD_NAND
87 static iomux_v3_cfg_t const nfc_pads[] = {
88 IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)),
89 IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)),
90 IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
91 IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
92 IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
93 IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
94 IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
95 IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
96 IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
97 IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
98 IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
99 IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
100 IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
101 IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
102 IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
103 };
104
setup_gpmi_nand(void)105 static void setup_gpmi_nand(void)
106 {
107 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
108
109 /* config gpmi nand iomux */
110 SETUP_IOMUX_PADS(nfc_pads);
111
112 /* config gpmi and bch clock to 100 MHz */
113 clrsetbits_le32(&mxc_ccm->cs2cdr,
114 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
115 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
116 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
117 MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
118 MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
119 MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
120
121 /* enable gpmi and bch clock gating */
122 setbits_le32(&mxc_ccm->CCGR4,
123 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
124 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
125 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
126 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
127 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
128
129 /* enable apbh clock gating */
130 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
131 }
132 #endif
133
setup_iomux_enet(int gpio)134 static void setup_iomux_enet(int gpio)
135 {
136 SETUP_IOMUX_PADS(enet_pads);
137
138 /* toggle PHY_RST# */
139 gpio_request(gpio, "phy_rst#");
140 gpio_direction_output(gpio, 0);
141 mdelay(10);
142 gpio_set_value(gpio, 1);
143 mdelay(100);
144 }
145
146 #ifdef CONFIG_USB_EHCI_MX6
147 static iomux_v3_cfg_t const usb_pads[] = {
148 IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | DIO_PAD_CFG),
149 IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC | DIO_PAD_CFG),
150 /* OTG PWR */
151 IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22 | DIO_PAD_CFG),
152 };
153
board_ehci_hcd_init(int port)154 int board_ehci_hcd_init(int port)
155 {
156 int gpio;
157
158 SETUP_IOMUX_PADS(usb_pads);
159
160 /* Reset USB HUB */
161 switch (board_type) {
162 case GW53xx:
163 case GW552x:
164 case GW5906:
165 gpio = (IMX_GPIO_NR(1, 9));
166 break;
167 case GW54proto:
168 case GW54xx:
169 gpio = (IMX_GPIO_NR(1, 16));
170 break;
171 default:
172 return 0;
173 }
174
175 /* request and toggle hub rst */
176 gpio_request(gpio, "usb_hub_rst#");
177 gpio_direction_output(gpio, 0);
178 mdelay(2);
179 gpio_set_value(gpio, 1);
180
181 return 0;
182 }
183
board_ehci_power(int port,int on)184 int board_ehci_power(int port, int on)
185 {
186 /* enable OTG VBUS */
187 if (!port && board_type < GW_UNKNOWN) {
188 if (gpio_cfg[board_type].otgpwr_en)
189 gpio_set_value(gpio_cfg[board_type].otgpwr_en, on);
190 }
191 return 0;
192 }
193 #endif /* CONFIG_USB_EHCI_MX6 */
194
195 #ifdef CONFIG_MXC_SPI
196 iomux_v3_cfg_t const ecspi1_pads[] = {
197 /* SS1 */
198 IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(SPI_PAD_CTRL)),
199 IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
200 IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
201 IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
202 };
203
board_spi_cs_gpio(unsigned bus,unsigned cs)204 int board_spi_cs_gpio(unsigned bus, unsigned cs)
205 {
206 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -1;
207 }
208
setup_spi(void)209 static void setup_spi(void)
210 {
211 gpio_request(IMX_GPIO_NR(3, 19), "spi_cs");
212 gpio_direction_output(IMX_GPIO_NR(3, 19), 1);
213 SETUP_IOMUX_PADS(ecspi1_pads);
214 }
215 #endif
216
217 /* configure eth0 PHY board-specific LED behavior */
board_phy_config(struct phy_device * phydev)218 int board_phy_config(struct phy_device *phydev)
219 {
220 unsigned short val;
221
222 /* Marvel 88E1510 */
223 if (phydev->phy_id == 0x1410dd1) {
224 /*
225 * Page 3, Register 16: LED[2:0] Function Control Register
226 * LED[0] (SPD:Amber) R16_3.3:0 to 0111: on-GbE link
227 * LED[1] (LNK:Green) R16_3.7:4 to 0001: on-link, blink-activity
228 */
229 phy_write(phydev, MDIO_DEVAD_NONE, 22, 3);
230 val = phy_read(phydev, MDIO_DEVAD_NONE, 16);
231 val &= 0xff00;
232 val |= 0x0017;
233 phy_write(phydev, MDIO_DEVAD_NONE, 16, val);
234 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
235 }
236
237 /* TI DP83867 */
238 else if (phydev->phy_id == 0x2000a231) {
239 /* configure register 0x170 for ref CLKOUT */
240 phy_write(phydev, MDIO_DEVAD_NONE, 13, 0x001f);
241 phy_write(phydev, MDIO_DEVAD_NONE, 14, 0x0170);
242 phy_write(phydev, MDIO_DEVAD_NONE, 13, 0x401f);
243 val = phy_read(phydev, MDIO_DEVAD_NONE, 14);
244 val &= ~0x1f00;
245 val |= 0x0b00; /* chD tx clock*/
246 phy_write(phydev, MDIO_DEVAD_NONE, 14, val);
247 }
248
249 if (phydev->drv->config)
250 phydev->drv->config(phydev);
251
252 return 0;
253 }
254
255 #ifdef CONFIG_MV88E61XX_SWITCH
mv88e61xx_hw_reset(struct phy_device * phydev)256 int mv88e61xx_hw_reset(struct phy_device *phydev)
257 {
258 struct mii_dev *bus = phydev->bus;
259
260 /* GPIO[0] output, CLK125 */
261 debug("enabling RGMII_REFCLK\n");
262 bus->write(bus, 0x1c /*MV_GLOBAL2*/, 0,
263 0x1a /*MV_SCRATCH_MISC*/,
264 (1 << 15) | (0x62 /*MV_GPIO_DIR*/ << 8) | 0xfe);
265 bus->write(bus, 0x1c /*MV_GLOBAL2*/, 0,
266 0x1a /*MV_SCRATCH_MISC*/,
267 (1 << 15) | (0x68 /*MV_GPIO01_CNTL*/ << 8) | 7);
268
269 /* RGMII delay - Physical Control register bit[15:14] */
270 debug("setting port%d RGMII rx/tx delay\n", CONFIG_MV88E61XX_CPU_PORT);
271 /* forced 1000mbps full-duplex link */
272 bus->write(bus, 0x10 + CONFIG_MV88E61XX_CPU_PORT, 0, 1, 0xc0fe);
273 phydev->autoneg = AUTONEG_DISABLE;
274 phydev->speed = SPEED_1000;
275 phydev->duplex = DUPLEX_FULL;
276
277 /* LED configuration: 7:4-green (8=Activity) 3:0 amber (8=Link) */
278 bus->write(bus, 0x10, 0, 0x16, 0x8088);
279 bus->write(bus, 0x11, 0, 0x16, 0x8088);
280 bus->write(bus, 0x12, 0, 0x16, 0x8088);
281 bus->write(bus, 0x13, 0, 0x16, 0x8088);
282
283 return 0;
284 }
285 #endif // CONFIG_MV88E61XX_SWITCH
286
board_eth_init(struct bd_info * bis)287 int board_eth_init(struct bd_info *bis)
288 {
289 #ifdef CONFIG_FEC_MXC
290 struct ventana_board_info *info = &ventana_info;
291
292 if (test_bit(EECONFIG_ETH0, info->config)) {
293 setup_iomux_enet(GP_PHY_RST);
294 cpu_eth_init(bis);
295 }
296 #endif
297
298 #ifdef CONFIG_E1000
299 e1000_initialize(bis);
300 #endif
301
302 #ifdef CONFIG_CI_UDC
303 /* For otg ethernet*/
304 usb_eth_initialize(bis);
305 #endif
306
307 /* default to the first detected enet dev */
308 if (!env_get("ethprime")) {
309 struct eth_device *dev = eth_get_dev_by_index(0);
310 if (dev) {
311 env_set("ethprime", dev->name);
312 printf("set ethprime to %s\n", env_get("ethprime"));
313 }
314 }
315
316 return 0;
317 }
318
319 #if defined(CONFIG_VIDEO_IPUV3)
320
enable_hdmi(struct display_info_t const * dev)321 static void enable_hdmi(struct display_info_t const *dev)
322 {
323 imx_enable_hdmi_phy();
324 }
325
detect_i2c(struct display_info_t const * dev)326 static int detect_i2c(struct display_info_t const *dev)
327 {
328 return i2c_set_bus_num(dev->bus) == 0 &&
329 i2c_probe(dev->addr) == 0;
330 }
331
enable_lvds(struct display_info_t const * dev)332 static void enable_lvds(struct display_info_t const *dev)
333 {
334 struct iomuxc *iomux = (struct iomuxc *)
335 IOMUXC_BASE_ADDR;
336
337 /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
338 u32 reg = readl(&iomux->gpr[2]);
339 reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
340 writel(reg, &iomux->gpr[2]);
341
342 /* Enable Backlight */
343 gpio_request(IMX_GPIO_NR(1, 10), "bklt_gpio");
344 gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
345 gpio_request(IMX_GPIO_NR(1, 18), "bklt_en");
346 SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | DIO_PAD_CFG);
347 gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
348 }
349
350 struct display_info_t const displays[] = {{
351 /* HDMI Output */
352 .bus = -1,
353 .addr = 0,
354 .pixfmt = IPU_PIX_FMT_RGB24,
355 .detect = detect_hdmi,
356 .enable = enable_hdmi,
357 .mode = {
358 .name = "HDMI",
359 .refresh = 60,
360 .xres = 1024,
361 .yres = 768,
362 .pixclock = 15385,
363 .left_margin = 220,
364 .right_margin = 40,
365 .upper_margin = 21,
366 .lower_margin = 7,
367 .hsync_len = 60,
368 .vsync_len = 10,
369 .sync = FB_SYNC_EXT,
370 .vmode = FB_VMODE_NONINTERLACED
371 } }, {
372 /* Freescale MXC-LVDS1: HannStar HSD100PXN1-A00 w/ egalx_ts cont */
373 .bus = 2,
374 .addr = 0x4,
375 .pixfmt = IPU_PIX_FMT_LVDS666,
376 .detect = detect_i2c,
377 .enable = enable_lvds,
378 .mode = {
379 .name = "Hannstar-XGA",
380 .refresh = 60,
381 .xres = 1024,
382 .yres = 768,
383 .pixclock = 15385,
384 .left_margin = 220,
385 .right_margin = 40,
386 .upper_margin = 21,
387 .lower_margin = 7,
388 .hsync_len = 60,
389 .vsync_len = 10,
390 .sync = FB_SYNC_EXT,
391 .vmode = FB_VMODE_NONINTERLACED
392 } }, {
393 /* DLC700JMG-T-4 */
394 .bus = 2,
395 .addr = 0x38,
396 .detect = NULL,
397 .enable = enable_lvds,
398 .pixfmt = IPU_PIX_FMT_LVDS666,
399 .mode = {
400 .name = "DLC700JMGT4",
401 .refresh = 60,
402 .xres = 1024, /* 1024x600active pixels */
403 .yres = 600,
404 .pixclock = 15385, /* 64MHz */
405 .left_margin = 220,
406 .right_margin = 40,
407 .upper_margin = 21,
408 .lower_margin = 7,
409 .hsync_len = 60,
410 .vsync_len = 10,
411 .sync = FB_SYNC_EXT,
412 .vmode = FB_VMODE_NONINTERLACED
413 } }, {
414 /* DLC800FIG-T-3 */
415 .bus = 2,
416 .addr = 0x14,
417 .detect = NULL,
418 .enable = enable_lvds,
419 .pixfmt = IPU_PIX_FMT_LVDS666,
420 .mode = {
421 .name = "DLC800FIGT3",
422 .refresh = 60,
423 .xres = 1024, /* 1024x768 active pixels */
424 .yres = 768,
425 .pixclock = 15385, /* 64MHz */
426 .left_margin = 220,
427 .right_margin = 40,
428 .upper_margin = 21,
429 .lower_margin = 7,
430 .hsync_len = 60,
431 .vsync_len = 10,
432 .sync = FB_SYNC_EXT,
433 .vmode = FB_VMODE_NONINTERLACED
434 } }, {
435 .bus = 2,
436 .addr = 0x5d,
437 .detect = detect_i2c,
438 .enable = enable_lvds,
439 .pixfmt = IPU_PIX_FMT_LVDS666,
440 .mode = {
441 .name = "Z101WX01",
442 .refresh = 60,
443 .xres = 1280,
444 .yres = 800,
445 .pixclock = 15385, /* 64MHz */
446 .left_margin = 220,
447 .right_margin = 40,
448 .upper_margin = 21,
449 .lower_margin = 7,
450 .hsync_len = 60,
451 .vsync_len = 10,
452 .sync = FB_SYNC_EXT,
453 .vmode = FB_VMODE_NONINTERLACED
454 }
455 },
456 };
457 size_t display_count = ARRAY_SIZE(displays);
458
setup_display(void)459 static void setup_display(void)
460 {
461 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
462 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
463 int reg;
464
465 enable_ipu_clock();
466 imx_setup_hdmi();
467 /* Turn on LDB0,IPU,IPU DI0 clocks */
468 reg = __raw_readl(&mxc_ccm->CCGR3);
469 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
470 writel(reg, &mxc_ccm->CCGR3);
471
472 /* set LDB0, LDB1 clk select to 011/011 */
473 reg = readl(&mxc_ccm->cs2cdr);
474 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
475 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
476 reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
477 |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
478 writel(reg, &mxc_ccm->cs2cdr);
479
480 reg = readl(&mxc_ccm->cscmr2);
481 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
482 writel(reg, &mxc_ccm->cscmr2);
483
484 reg = readl(&mxc_ccm->chsccdr);
485 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
486 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
487 writel(reg, &mxc_ccm->chsccdr);
488
489 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
490 |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
491 |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
492 |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
493 |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
494 |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
495 |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
496 |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
497 |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
498 writel(reg, &iomux->gpr[2]);
499
500 reg = readl(&iomux->gpr[3]);
501 reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
502 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
503 <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
504 writel(reg, &iomux->gpr[3]);
505
506 /* LVDS Backlight GPIO on LVDS connector - output low */
507 SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | DIO_PAD_CFG);
508 gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
509 }
510 #endif /* CONFIG_VIDEO_IPUV3 */
511
512 /* setup board specific PMIC */
power_init_board(void)513 int power_init_board(void)
514 {
515 setup_pmic();
516 return 0;
517 }
518
519 #if defined(CONFIG_CMD_PCI)
imx6_pcie_toggle_reset(void)520 int imx6_pcie_toggle_reset(void)
521 {
522 if (board_type < GW_UNKNOWN) {
523 uint pin = gpio_cfg[board_type].pcie_rst;
524 gpio_request(pin, "pci_rst#");
525 gpio_direction_output(pin, 0);
526 mdelay(50);
527 gpio_direction_output(pin, 1);
528 }
529 return 0;
530 }
531
532 /*
533 * Most Ventana boards have a PLX PEX860x PCIe switch onboard and use its
534 * GPIO's as PERST# signals for its downstream ports - configure the GPIO's
535 * properly and assert reset for 100ms.
536 */
537 #define MAX_PCI_DEVS 32
538 struct pci_dev {
539 pci_dev_t devfn;
540 unsigned short vendor;
541 unsigned short device;
542 unsigned short class;
543 unsigned short busno; /* subbordinate busno */
544 struct pci_dev *ppar;
545 };
546 struct pci_dev pci_devs[MAX_PCI_DEVS];
547 int pci_devno;
548 int pci_bridgeno;
549
board_pci_fixup_dev(struct pci_controller * hose,pci_dev_t dev,unsigned short vendor,unsigned short device,unsigned short class)550 void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
551 unsigned short vendor, unsigned short device,
552 unsigned short class)
553 {
554 int i;
555 u32 dw;
556 struct pci_dev *pdev = &pci_devs[pci_devno++];
557
558 debug("%s: %02d:%02d.%02d: %04x:%04x\n", __func__,
559 PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), vendor, device);
560
561 /* store array of devs for later use in device-tree fixup */
562 pdev->devfn = dev;
563 pdev->vendor = vendor;
564 pdev->device = device;
565 pdev->class = class;
566 pdev->ppar = NULL;
567 if (class == PCI_CLASS_BRIDGE_PCI)
568 pdev->busno = ++pci_bridgeno;
569 else
570 pdev->busno = 0;
571
572 /* fixup RC - it should be 00:00.0 not 00:01.0 */
573 if (PCI_BUS(dev) == 0)
574 pdev->devfn = 0;
575
576 /* find dev's parent */
577 for (i = 0; i < pci_devno; i++) {
578 if (pci_devs[i].busno == PCI_BUS(pdev->devfn)) {
579 pdev->ppar = &pci_devs[i];
580 break;
581 }
582 }
583
584 /* assert downstream PERST# */
585 if (vendor == PCI_VENDOR_ID_PLX &&
586 (device & 0xfff0) == 0x8600 &&
587 PCI_DEV(dev) == 0 && PCI_FUNC(dev) == 0) {
588 debug("configuring PLX 860X downstream PERST#\n");
589 pci_hose_read_config_dword(hose, dev, 0x62c, &dw);
590 dw |= 0xaaa8; /* GPIO1-7 outputs */
591 pci_hose_write_config_dword(hose, dev, 0x62c, dw);
592
593 pci_hose_read_config_dword(hose, dev, 0x644, &dw);
594 dw |= 0xfe; /* GPIO1-7 output high */
595 pci_hose_write_config_dword(hose, dev, 0x644, dw);
596
597 mdelay(100);
598 }
599 }
600 #endif /* CONFIG_CMD_PCI */
601
602 #ifdef CONFIG_SERIAL_TAG
603 /*
604 * called when setting up ATAGS before booting kernel
605 * populate serialnum from the following (in order of priority):
606 * serial# env var
607 * eeprom
608 */
get_board_serial(struct tag_serialnr * serialnr)609 void get_board_serial(struct tag_serialnr *serialnr)
610 {
611 char *serial = env_get("serial#");
612
613 if (serial) {
614 serialnr->high = 0;
615 serialnr->low = simple_strtoul(serial, NULL, 10);
616 } else if (ventana_info.model[0]) {
617 serialnr->high = 0;
618 serialnr->low = ventana_info.serial;
619 } else {
620 serialnr->high = 0;
621 serialnr->low = 0;
622 }
623 }
624 #endif
625
626 /*
627 * Board Support
628 */
629
board_early_init_f(void)630 int board_early_init_f(void)
631 {
632 setup_iomux_uart();
633
634 #if defined(CONFIG_VIDEO_IPUV3)
635 setup_display();
636 #endif
637 return 0;
638 }
639
dram_init(void)640 int dram_init(void)
641 {
642 gd->ram_size = imx_ddr_size();
643 return 0;
644 }
645
board_init(void)646 int board_init(void)
647 {
648 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
649
650 clrsetbits_le32(&iomuxc_regs->gpr[1],
651 IOMUXC_GPR1_OTG_ID_MASK,
652 IOMUXC_GPR1_OTG_ID_GPIO1);
653
654 /* address of linux boot parameters */
655 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
656
657 /* read Gateworks EEPROM into global struct (used later) */
658 setup_ventana_i2c(0);
659 board_type = read_eeprom(CONFIG_I2C_GSC, &ventana_info);
660
661 #ifdef CONFIG_CMD_NAND
662 if (gpio_cfg[board_type].nand)
663 setup_gpmi_nand();
664 #endif
665 #ifdef CONFIG_MXC_SPI
666 setup_spi();
667 #endif
668 setup_ventana_i2c(1);
669 setup_ventana_i2c(2);
670
671 #ifdef CONFIG_SATA
672 setup_sata();
673 #endif
674
675 setup_iomux_gpio(board_type, &ventana_info);
676
677 return 0;
678 }
679
680 #if defined(CONFIG_DISPLAY_BOARDINFO_LATE)
681 /*
682 * called during late init (after relocation and after board_init())
683 * by virtue of CONFIG_DISPLAY_BOARDINFO_LATE as we needed i2c initialized and
684 * EEPROM read.
685 */
checkboard(void)686 int checkboard(void)
687 {
688 struct ventana_board_info *info = &ventana_info;
689 unsigned char buf[4];
690 const char *p;
691 int quiet; /* Quiet or minimal output mode */
692
693 quiet = 0;
694 p = env_get("quiet");
695 if (p)
696 quiet = simple_strtol(p, NULL, 10);
697 else
698 env_set("quiet", "0");
699
700 puts("\nGateworks Corporation Copyright 2014\n");
701 if (info->model[0]) {
702 printf("Model: %s\n", info->model);
703 printf("MFGDate: %02x-%02x-%02x%02x\n",
704 info->mfgdate[0], info->mfgdate[1],
705 info->mfgdate[2], info->mfgdate[3]);
706 printf("Serial:%d\n", info->serial);
707 } else {
708 puts("Invalid EEPROM - board will not function fully\n");
709 }
710 if (quiet)
711 return 0;
712
713 /* Display GSC firmware revision/CRC/status */
714 gsc_info(0);
715
716 /* Display RTC */
717 if (!gsc_i2c_read(GSC_RTC_ADDR, 0x00, 1, buf, 4)) {
718 printf("RTC: %d\n",
719 buf[0] | buf[1]<<8 | buf[2]<<16 | buf[3]<<24);
720 }
721
722 return 0;
723 }
724 #endif
725
726 #ifdef CONFIG_CMD_BMODE
727 /*
728 * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
729 * see Table 8-11 and Table 5-9
730 * BOOT_CFG1[7] = 1 (boot from NAND)
731 * BOOT_CFG1[5] = 0 - raw NAND
732 * BOOT_CFG1[4] = 0 - default pad settings
733 * BOOT_CFG1[3:2] = 00 - devices = 1
734 * BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
735 * BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
736 * BOOT_CFG2[2:1] = 01 - Pages In Block = 64
737 * BOOT_CFG2[0] = 0 - Reset time 12ms
738 */
739 static const struct boot_mode board_boot_modes[] = {
740 /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
741 { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
742 { "emmc2", MAKE_CFGVAL(0x60, 0x48, 0x00, 0x00) }, /* GW5600 */
743 { "emmc3", MAKE_CFGVAL(0x60, 0x50, 0x00, 0x00) }, /* GW5903/4/5 */
744 { NULL, 0 },
745 };
746 #endif
747
748 /* late init */
misc_init_r(void)749 int misc_init_r(void)
750 {
751 struct ventana_board_info *info = &ventana_info;
752 char buf[256];
753 int i;
754
755 /* set env vars based on EEPROM data */
756 if (ventana_info.model[0]) {
757 char str[16], fdt[36];
758 char *p;
759 const char *cputype = "";
760
761 /*
762 * FDT name will be prefixed with CPU type. Three versions
763 * will be created each increasingly generic and bootloader
764 * env scripts will try loading each from most specific to
765 * least.
766 */
767 if (is_cpu_type(MXC_CPU_MX6Q) ||
768 is_cpu_type(MXC_CPU_MX6D))
769 cputype = "imx6q";
770 else if (is_cpu_type(MXC_CPU_MX6DL) ||
771 is_cpu_type(MXC_CPU_MX6SOLO))
772 cputype = "imx6dl";
773 env_set("soctype", cputype);
774 if (8 << (ventana_info.nand_flash_size-1) >= 2048)
775 env_set("flash_layout", "large");
776 else
777 env_set("flash_layout", "normal");
778 memset(str, 0, sizeof(str));
779 for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++)
780 str[i] = tolower(info->model[i]);
781 env_set("model", str);
782 if (!env_get("fdt_file")) {
783 sprintf(fdt, "%s-%s.dtb", cputype, str);
784 env_set("fdt_file", fdt);
785 }
786 p = strchr(str, '-');
787 if (p) {
788 *p++ = 0;
789
790 env_set("model_base", str);
791 sprintf(fdt, "%s-%s.dtb", cputype, str);
792 env_set("fdt_file1", fdt);
793 if (board_type != GW551x &&
794 board_type != GW552x &&
795 board_type != GW553x &&
796 board_type != GW560x)
797 str[4] = 'x';
798 str[5] = 'x';
799 str[6] = 0;
800 sprintf(fdt, "%s-%s.dtb", cputype, str);
801 env_set("fdt_file2", fdt);
802 }
803
804 /* initialize env from EEPROM */
805 if (test_bit(EECONFIG_ETH0, info->config) &&
806 !env_get("ethaddr")) {
807 eth_env_set_enetaddr("ethaddr", info->mac0);
808 }
809 if (test_bit(EECONFIG_ETH1, info->config) &&
810 !env_get("eth1addr")) {
811 eth_env_set_enetaddr("eth1addr", info->mac1);
812 }
813
814 /* board serial-number */
815 sprintf(str, "%6d", info->serial);
816 env_set("serial#", str);
817
818 /* memory MB */
819 sprintf(str, "%d", (int) (gd->ram_size >> 20));
820 env_set("mem_mb", str);
821 }
822
823 /* Set a non-initialized hwconfig based on board configuration */
824 if (!strcmp(env_get("hwconfig"), "_UNKNOWN_")) {
825 buf[0] = 0;
826 if (gpio_cfg[board_type].rs232_en)
827 strcat(buf, "rs232;");
828 for (i = 0; i < gpio_cfg[board_type].dio_num; i++) {
829 char buf1[32];
830 sprintf(buf1, "dio%d:mode=gpio;", i);
831 if (strlen(buf) + strlen(buf1) < sizeof(buf))
832 strcat(buf, buf1);
833 }
834 env_set("hwconfig", buf);
835 }
836
837 /* setup baseboard specific GPIO based on board and env */
838 setup_board_gpio(board_type, info);
839
840 #ifdef CONFIG_CMD_BMODE
841 add_board_boot_modes(board_boot_modes);
842 #endif
843
844 /* disable boot watchdog */
845 gsc_boot_wd_disable();
846
847 return 0;
848 }
849
850 #ifdef CONFIG_OF_BOARD_SETUP
851
ft_sethdmiinfmt(void * blob,char * mode)852 static int ft_sethdmiinfmt(void *blob, char *mode)
853 {
854 int off;
855
856 if (!mode)
857 return -EINVAL;
858
859 off = fdt_node_offset_by_compatible(blob, -1, "nxp,tda1997x");
860 if (off < 0)
861 return off;
862
863 if (0 == strcasecmp(mode, "yuv422bt656")) {
864 u8 cfg[] = { 0x00, 0x00, 0x00, 0x82, 0x81, 0x00,
865 0x00, 0x00, 0x00 };
866 mode = "422_ccir";
867 fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
868 fdt_setprop_u32(blob, off, "vidout_trc", 1);
869 fdt_setprop_u32(blob, off, "vidout_blc", 1);
870 fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
871 printf(" set HDMI input mode to %s\n", mode);
872 } else if (0 == strcasecmp(mode, "yuv422smp")) {
873 u8 cfg[] = { 0x00, 0x00, 0x00, 0x88, 0x87, 0x00,
874 0x82, 0x81, 0x00 };
875 mode = "422_smp";
876 fdt_setprop(blob, off, "vidout_fmt", mode, strlen(mode) + 1);
877 fdt_setprop_u32(blob, off, "vidout_trc", 0);
878 fdt_setprop_u32(blob, off, "vidout_blc", 0);
879 fdt_setprop(blob, off, "vidout_portcfg", cfg, sizeof(cfg));
880 printf(" set HDMI input mode to %s\n", mode);
881 } else {
882 return -EINVAL;
883 }
884
885 return 0;
886 }
887
888 #if defined(CONFIG_CMD_PCI)
889 #define PCI_ID(x) ( \
890 (PCI_BUS(x->devfn)<<16)| \
891 (PCI_DEV(x->devfn)<<11)| \
892 (PCI_FUNC(x->devfn)<<8) \
893 )
fdt_add_pci_node(void * blob,int par,struct pci_dev * dev)894 int fdt_add_pci_node(void *blob, int par, struct pci_dev *dev)
895 {
896 uint32_t reg[5];
897 char node[32];
898 int np;
899
900 sprintf(node, "pcie@%d,%d,%d", PCI_BUS(dev->devfn),
901 PCI_DEV(dev->devfn), PCI_FUNC(dev->devfn));
902
903 np = fdt_subnode_offset(blob, par, node);
904 if (np >= 0)
905 return np;
906 np = fdt_add_subnode(blob, par, node);
907 if (np < 0) {
908 printf(" %s failed: no space\n", __func__);
909 return np;
910 }
911
912 memset(reg, 0, sizeof(reg));
913 reg[0] = cpu_to_fdt32(PCI_ID(dev));
914 fdt_setprop(blob, np, "reg", reg, sizeof(reg));
915
916 return np;
917 }
918
919 /* build a path of nested PCI devs for all bridges passed through */
fdt_add_pci_path(void * blob,struct pci_dev * dev)920 int fdt_add_pci_path(void *blob, struct pci_dev *dev)
921 {
922 struct pci_dev *bridges[MAX_PCI_DEVS];
923 int k, np;
924
925 /* build list of parents */
926 np = fdt_node_offset_by_compatible(blob, -1, "fsl,imx6q-pcie");
927 if (np < 0)
928 return np;
929
930 k = 0;
931 while (dev) {
932 bridges[k++] = dev;
933 dev = dev->ppar;
934 };
935
936 /* now add them the to DT in reverse order */
937 while (k--) {
938 np = fdt_add_pci_node(blob, np, bridges[k]);
939 if (np < 0)
940 break;
941 }
942
943 return np;
944 }
945
946 /*
947 * The GW16082 has a hardware errata errata such that it's
948 * INTA/B/C/D are mis-mapped to its four slots (slot12-15). Because
949 * of this normal PCI interrupt swizzling will not work so we will
950 * provide an irq-map via device-tree.
951 */
fdt_fixup_gw16082(void * blob,int np,struct pci_dev * dev)952 int fdt_fixup_gw16082(void *blob, int np, struct pci_dev *dev)
953 {
954 int len;
955 int host;
956 uint32_t imap_new[8*4*4];
957 const uint32_t *imap;
958 uint32_t irq[4];
959 uint32_t reg[4];
960 int i;
961
962 /* build irq-map based on host controllers map */
963 host = fdt_node_offset_by_compatible(blob, -1, "fsl,imx6q-pcie");
964 if (host < 0) {
965 printf(" %s failed: missing host\n", __func__);
966 return host;
967 }
968
969 /* use interrupt data from root complex's node */
970 imap = fdt_getprop(blob, host, "interrupt-map", &len);
971 if (!imap || len != 128) {
972 printf(" %s failed: invalid interrupt-map\n",
973 __func__);
974 return -FDT_ERR_NOTFOUND;
975 }
976
977 /* obtain irq's of host controller in pin order */
978 for (i = 0; i < 4; i++)
979 irq[(fdt32_to_cpu(imap[(i*8)+3])-1)%4] = imap[(i*8)+6];
980
981 /*
982 * determine number of swizzles necessary:
983 * For each bridge we pass through we need to swizzle
984 * the number of the slot we are on.
985 */
986 struct pci_dev *d;
987 int b;
988 b = 0;
989 d = dev->ppar;
990 while(d && d->ppar) {
991 b += PCI_DEV(d->devfn);
992 d = d->ppar;
993 }
994
995 /* create new irq mappings for slots12-15
996 * <skt> <idsel> <slot> <skt-inta> <skt-intb>
997 * J3 AD28 12 INTD INTA
998 * J4 AD29 13 INTC INTD
999 * J5 AD30 14 INTB INTC
1000 * J2 AD31 15 INTA INTB
1001 */
1002 for (i = 0; i < 4; i++) {
1003 /* addr matches bus:dev:func */
1004 u32 addr = dev->busno << 16 | (12+i) << 11;
1005
1006 /* default cells from root complex */
1007 memcpy(&imap_new[i*32], imap, 128);
1008 /* first cell is PCI device address (BDF) */
1009 imap_new[(i*32)+(0*8)+0] = cpu_to_fdt32(addr);
1010 imap_new[(i*32)+(1*8)+0] = cpu_to_fdt32(addr);
1011 imap_new[(i*32)+(2*8)+0] = cpu_to_fdt32(addr);
1012 imap_new[(i*32)+(3*8)+0] = cpu_to_fdt32(addr);
1013 /* third cell is pin */
1014 imap_new[(i*32)+(0*8)+3] = cpu_to_fdt32(1);
1015 imap_new[(i*32)+(1*8)+3] = cpu_to_fdt32(2);
1016 imap_new[(i*32)+(2*8)+3] = cpu_to_fdt32(3);
1017 imap_new[(i*32)+(3*8)+3] = cpu_to_fdt32(4);
1018 /* sixth cell is relative interrupt */
1019 imap_new[(i*32)+(0*8)+6] = irq[(15-(12+i)+b+0)%4];
1020 imap_new[(i*32)+(1*8)+6] = irq[(15-(12+i)+b+1)%4];
1021 imap_new[(i*32)+(2*8)+6] = irq[(15-(12+i)+b+2)%4];
1022 imap_new[(i*32)+(3*8)+6] = irq[(15-(12+i)+b+3)%4];
1023 }
1024 fdt_setprop(blob, np, "interrupt-map", imap_new,
1025 sizeof(imap_new));
1026 reg[0] = cpu_to_fdt32(0xfff00);
1027 reg[1] = 0;
1028 reg[2] = 0;
1029 reg[3] = cpu_to_fdt32(0x7);
1030 fdt_setprop(blob, np, "interrupt-map-mask", reg, sizeof(reg));
1031 fdt_setprop_cell(blob, np, "#interrupt-cells", 1);
1032 fdt_setprop_string(blob, np, "device_type", "pci");
1033 fdt_setprop_cell(blob, np, "#address-cells", 3);
1034 fdt_setprop_cell(blob, np, "#size-cells", 2);
1035 printf(" Added custom interrupt-map for GW16082\n");
1036
1037 return 0;
1038 }
1039
1040 /* The sky2 GigE MAC obtains it's MAC addr from device-tree by default */
fdt_fixup_sky2(void * blob,int np,struct pci_dev * dev)1041 int fdt_fixup_sky2(void *blob, int np, struct pci_dev *dev)
1042 {
1043 char *tmp, *end;
1044 char mac[16];
1045 unsigned char mac_addr[6];
1046 int j;
1047
1048 sprintf(mac, "eth1addr");
1049 tmp = env_get(mac);
1050 if (tmp) {
1051 for (j = 0; j < 6; j++) {
1052 mac_addr[j] = tmp ?
1053 simple_strtoul(tmp, &end,16) : 0;
1054 if (tmp)
1055 tmp = (*end) ? end+1 : end;
1056 }
1057 fdt_setprop(blob, np, "local-mac-address", mac_addr,
1058 sizeof(mac_addr));
1059 printf(" Added mac addr for eth1\n");
1060 return 0;
1061 }
1062
1063 return -1;
1064 }
1065
1066 /*
1067 * PCI DT nodes must be nested therefore if we need to apply a DT fixup
1068 * we will walk the PCI bus and add bridge nodes up to the device receiving
1069 * the fixup.
1070 */
ft_board_pci_fixup(void * blob,struct bd_info * bd)1071 void ft_board_pci_fixup(void *blob, struct bd_info *bd)
1072 {
1073 int i, np;
1074 struct pci_dev *dev;
1075
1076 for (i = 0; i < pci_devno; i++) {
1077 dev = &pci_devs[i];
1078
1079 /*
1080 * The GW16082 consists of a TI XIO2001 PCIe-to-PCI bridge and
1081 * an EEPROM at i2c1-0x50.
1082 */
1083 if ((dev->vendor == PCI_VENDOR_ID_TI) &&
1084 (dev->device == 0x8240) &&
1085 (i2c_set_bus_num(1) == 0) &&
1086 (i2c_probe(0x50) == 0))
1087 {
1088 np = fdt_add_pci_path(blob, dev);
1089 if (np > 0)
1090 fdt_fixup_gw16082(blob, np, dev);
1091 }
1092
1093 /* ethernet1 mac address */
1094 else if ((dev->vendor == PCI_VENDOR_ID_MARVELL) &&
1095 (dev->device == 0x4380))
1096 {
1097 np = fdt_add_pci_path(blob, dev);
1098 if (np > 0)
1099 fdt_fixup_sky2(blob, np, dev);
1100 }
1101 }
1102 }
1103 #endif /* if defined(CONFIG_CMD_PCI) */
1104
ft_board_wdog_fixup(void * blob,phys_addr_t addr)1105 void ft_board_wdog_fixup(void *blob, phys_addr_t addr)
1106 {
1107 int off = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-wdt", addr);
1108
1109 if (off) {
1110 fdt_delprop(blob, off, "ext-reset-output");
1111 fdt_delprop(blob, off, "fsl,ext-reset-output");
1112 }
1113 }
1114
1115 /*
1116 * called prior to booting kernel or by 'fdt boardsetup' command
1117 *
1118 * unless 'fdt_noauto' env var is set we will update the following in the DTB:
1119 * - mtd partitions based on mtdparts/mtdids env
1120 * - system-serial (board serial num from EEPROM)
1121 * - board (full model from EEPROM)
1122 * - peripherals removed from DTB if not loaded on board (per EEPROM config)
1123 */
1124 #define WDOG1_ADDR 0x20bc000
1125 #define WDOG2_ADDR 0x20c0000
1126 #define GPIO3_ADDR 0x20a4000
1127 #define USDHC3_ADDR 0x2198000
1128 #define PWM0_ADDR 0x2080000
ft_board_setup(void * blob,struct bd_info * bd)1129 int ft_board_setup(void *blob, struct bd_info *bd)
1130 {
1131 struct ventana_board_info *info = &ventana_info;
1132 struct ventana_eeprom_config *cfg;
1133 static const struct node_info nodes[] = {
1134 { "sst,w25q256", MTD_DEV_TYPE_NOR, }, /* SPI flash */
1135 { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
1136 };
1137 const char *model = env_get("model");
1138 const char *display = env_get("display");
1139 int i;
1140 char rev = 0;
1141
1142 /* determine board revision */
1143 for (i = sizeof(ventana_info.model) - 1; i > 0; i--) {
1144 if (ventana_info.model[i] >= 'A') {
1145 rev = ventana_info.model[i];
1146 break;
1147 }
1148 }
1149
1150 if (env_get("fdt_noauto")) {
1151 puts(" Skiping ft_board_setup (fdt_noauto defined)\n");
1152 return 0;
1153 }
1154
1155 if (test_bit(EECONFIG_NAND, info->config)) {
1156 /* Update partition nodes using info from mtdparts env var */
1157 puts(" Updating MTD partitions...\n");
1158 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1159 }
1160
1161 /* Update display timings from display env var */
1162 if (display) {
1163 if (fdt_fixup_display(blob, fdt_get_alias(blob, "lvds0"),
1164 display) >= 0)
1165 printf(" Set display timings for %s...\n", display);
1166 }
1167
1168 printf(" Adjusting FDT per EEPROM for %s...\n", model);
1169
1170 /* board serial number */
1171 fdt_setprop(blob, 0, "system-serial", env_get("serial#"),
1172 strlen(env_get("serial#")) + 1);
1173
1174 /* board (model contains model from device-tree) */
1175 fdt_setprop(blob, 0, "board", info->model,
1176 strlen((const char *)info->model) + 1);
1177
1178 /* set desired digital video capture format */
1179 ft_sethdmiinfmt(blob, env_get("hdmiinfmt"));
1180
1181 /*
1182 * Board model specific fixups
1183 */
1184 switch (board_type) {
1185 case GW51xx:
1186 /*
1187 * disable wdog node for GW51xx-A/B to work around
1188 * errata causing wdog timer to be unreliable.
1189 */
1190 if (rev >= 'A' && rev < 'C') {
1191 i = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-wdt",
1192 WDOG1_ADDR);
1193 if (i)
1194 fdt_status_disabled(blob, i);
1195 }
1196
1197 /* GW51xx-E adds WDOG1_B external reset */
1198 if (rev < 'E')
1199 ft_board_wdog_fixup(blob, WDOG1_ADDR);
1200 break;
1201
1202 case GW52xx:
1203 /* GW522x Uses GPIO3_IO23 instead of GPIO1_IO29 */
1204 if (info->model[4] == '2') {
1205 u32 handle = 0;
1206 u32 *range = NULL;
1207
1208 i = fdt_node_offset_by_compatible(blob, -1,
1209 "fsl,imx6q-pcie");
1210 if (i)
1211 range = (u32 *)fdt_getprop(blob, i,
1212 "reset-gpio", NULL);
1213
1214 if (range) {
1215 i = fdt_node_offset_by_compat_reg(blob,
1216 "fsl,imx6q-gpio", GPIO3_ADDR);
1217 if (i)
1218 handle = fdt_get_phandle(blob, i);
1219 if (handle) {
1220 range[0] = cpu_to_fdt32(handle);
1221 range[1] = cpu_to_fdt32(23);
1222 }
1223 }
1224
1225 /* these have broken usd_vsel */
1226 if (strstr((const char *)info->model, "SP318-B") ||
1227 strstr((const char *)info->model, "SP331-B"))
1228 gpio_cfg[board_type].usd_vsel = 0;
1229
1230 /* GW522x-B adds WDOG1_B external reset */
1231 if (rev < 'B')
1232 ft_board_wdog_fixup(blob, WDOG1_ADDR);
1233 }
1234
1235 /* GW520x-E adds WDOG1_B external reset */
1236 else if (info->model[4] == '0' && rev < 'E')
1237 ft_board_wdog_fixup(blob, WDOG1_ADDR);
1238 break;
1239
1240 case GW53xx:
1241 /* GW53xx-E adds WDOG1_B external reset */
1242 if (rev < 'E')
1243 ft_board_wdog_fixup(blob, WDOG1_ADDR);
1244 break;
1245
1246 case GW54xx:
1247 /*
1248 * disable serial2 node for GW54xx for compatibility with older
1249 * 3.10.x kernel that improperly had this node enabled in the DT
1250 */
1251 fdt_set_status_by_alias(blob, "serial2", FDT_STATUS_DISABLED,
1252 0);
1253
1254 /* GW54xx-E adds WDOG2_B external reset */
1255 if (rev < 'E')
1256 ft_board_wdog_fixup(blob, WDOG2_ADDR);
1257 break;
1258
1259 case GW551x:
1260 /*
1261 * isolate CSI0_DATA_EN for GW551x-A to work around errata
1262 * causing non functional digital video in (it is not hooked up)
1263 */
1264 if (rev == 'A') {
1265 u32 *range = NULL;
1266 int len;
1267 const u32 *handle = NULL;
1268
1269 i = fdt_node_offset_by_compatible(blob, -1,
1270 "fsl,imx-tda1997x-video");
1271 if (i)
1272 handle = fdt_getprop(blob, i, "pinctrl-0",
1273 NULL);
1274 if (handle)
1275 i = fdt_node_offset_by_phandle(blob,
1276 fdt32_to_cpu(*handle));
1277 if (i)
1278 range = (u32 *)fdt_getprop(blob, i, "fsl,pins",
1279 &len);
1280 if (range) {
1281 len /= sizeof(u32);
1282 for (i = 0; i < len; i += 6) {
1283 u32 mux_reg = fdt32_to_cpu(range[i+0]);
1284 u32 conf_reg = fdt32_to_cpu(range[i+1]);
1285 /* mux PAD_CSI0_DATA_EN to GPIO */
1286 if (is_cpu_type(MXC_CPU_MX6Q) &&
1287 mux_reg == 0x260 &&
1288 conf_reg == 0x630)
1289 range[i+3] = cpu_to_fdt32(0x5);
1290 else if (!is_cpu_type(MXC_CPU_MX6Q) &&
1291 mux_reg == 0x08c &&
1292 conf_reg == 0x3a0)
1293 range[i+3] = cpu_to_fdt32(0x5);
1294 }
1295 fdt_setprop_inplace(blob, i, "fsl,pins", range,
1296 len);
1297 }
1298
1299 /* set BT656 video format */
1300 ft_sethdmiinfmt(blob, "yuv422bt656");
1301 }
1302
1303 /* GW551x-C adds WDOG1_B external reset */
1304 if (rev < 'C')
1305 ft_board_wdog_fixup(blob, WDOG1_ADDR);
1306 break;
1307 case GW5901:
1308 case GW5902:
1309 /* GW5901/GW5901 revB adds WDOG1_B as an external reset */
1310 if (rev < 'B')
1311 ft_board_wdog_fixup(blob, WDOG1_ADDR);
1312 break;
1313 }
1314
1315 /* Configure DIO */
1316 for (i = 0; i < gpio_cfg[board_type].dio_num; i++) {
1317 struct dio_cfg *cfg = &gpio_cfg[board_type].dio_cfg[i];
1318 char arg[10];
1319
1320 sprintf(arg, "dio%d", i);
1321 if (!hwconfig(arg))
1322 continue;
1323 if (hwconfig_subarg_cmp(arg, "mode", "pwm") && cfg->pwm_param)
1324 {
1325 phys_addr_t addr;
1326 int off;
1327
1328 printf(" Enabling pwm%d for DIO%d\n",
1329 cfg->pwm_param, i);
1330 addr = PWM0_ADDR + (0x4000 * (cfg->pwm_param - 1));
1331 off = fdt_node_offset_by_compat_reg(blob,
1332 "fsl,imx6q-pwm",
1333 addr);
1334 if (off)
1335 fdt_status_okay(blob, off);
1336 }
1337 }
1338
1339 /* remove no-1-8-v if UHS-I support is present */
1340 if (gpio_cfg[board_type].usd_vsel) {
1341 debug("Enabling UHS-I support\n");
1342 i = fdt_node_offset_by_compat_reg(blob, "fsl,imx6q-usdhc",
1343 USDHC3_ADDR);
1344 if (i)
1345 fdt_delprop(blob, i, "no-1-8-v");
1346 }
1347
1348 #if defined(CONFIG_CMD_PCI)
1349 if (!env_get("nopcifixup"))
1350 ft_board_pci_fixup(blob, bd);
1351 #endif
1352
1353 /*
1354 * Peripheral Config:
1355 * remove nodes by alias path if EEPROM config tells us the
1356 * peripheral is not loaded on the board.
1357 */
1358 if (env_get("fdt_noconfig")) {
1359 puts(" Skiping periperhal config (fdt_noconfig defined)\n");
1360 return 0;
1361 }
1362 cfg = econfig;
1363 while (cfg->name) {
1364 if (!test_bit(cfg->bit, info->config)) {
1365 fdt_del_node_and_alias(blob, cfg->dtalias ?
1366 cfg->dtalias : cfg->name);
1367 }
1368 cfg++;
1369 }
1370
1371 return 0;
1372 }
1373 #endif /* CONFIG_OF_BOARD_SETUP */
1374
1375 static struct mxc_serial_plat ventana_mxc_serial_plat = {
1376 .reg = (struct mxc_uart *)UART2_BASE,
1377 };
1378
1379 U_BOOT_DRVINFO(ventana_serial) = {
1380 .name = "serial_mxc",
1381 .plat = &ventana_mxc_serial_plat,
1382 };
1383