1 /*
2  * Copyright (c) 2015-2020, Broadcom
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #include <arch_helpers.h>
8 #include <common/debug.h>
9 #include <drivers/brcm/sotp.h>
10 
11 #include <cmn_plat_util.h>
12 #include <platform_def.h>
13 
boot_source_get(void)14 uint32_t boot_source_get(void)
15 {
16 	uint32_t data;
17 
18 #ifdef FORCE_BOOTSOURCE
19 	data = FORCE_BOOTSOURCE;
20 #else
21 	/* Read primary boot strap from CRMU persistent registers */
22 	data = mmio_read_32(CRMU_IHOST_SW_PERSISTENT_REG1);
23 	if (data & BOOT_SOURCE_SOFT_ENABLE_MASK) {
24 		data >>= BOOT_SOURCE_SOFT_DATA_OFFSET;
25 	} else {
26 		uint64_t sotp_atf_row;
27 
28 		sotp_atf_row =
29 			sotp_mem_read(SOTP_ATF_CFG_ROW_ID, SOTP_ROW_NO_ECC);
30 
31 		if (sotp_atf_row & SOTP_BOOT_SOURCE_ENABLE_MASK) {
32 			/* Construct the boot source based on SOTP bits */
33 			data = 0;
34 			if (sotp_atf_row & SOTP_BOOT_SOURCE_BITS0)
35 				data |= 0x1;
36 			if (sotp_atf_row & SOTP_BOOT_SOURCE_BITS1)
37 				data |= 0x2;
38 			if (sotp_atf_row & SOTP_BOOT_SOURCE_BITS2)
39 				data |= 0x4;
40 		} else {
41 
42 			/*
43 			 * This path is for L0 reset with
44 			 * Primary Boot source disabled in SOTP.
45 			 * BOOT_SOURCE_FROM_PR_ON_L1 compile flag will allow
46 			 * to never come back here so that the
47 			 * external straps will not be read on L1 reset.
48 			 */
49 
50 			/* Use the external straps */
51 			data = mmio_read_32(ROM_S0_IDM_IO_STATUS);
52 
53 #ifdef BOOT_SOURCE_FROM_PR_ON_L1
54 			/* Enable boot source read from PR#1 */
55 			mmio_setbits_32(CRMU_IHOST_SW_PERSISTENT_REG1,
56 				BOOT_SOURCE_SOFT_ENABLE_MASK);
57 
58 			/* set boot source */
59 			data &= BOOT_SOURCE_MASK;
60 			mmio_clrsetbits_32(CRMU_IHOST_SW_PERSISTENT_REG1,
61 			BOOT_SOURCE_MASK << BOOT_SOURCE_SOFT_DATA_OFFSET,
62 			data << BOOT_SOURCE_SOFT_DATA_OFFSET);
63 #endif
64 		}
65 	}
66 #endif
67 	return (data & BOOT_SOURCE_MASK);
68 }
69 
plat_soft_reset(uint32_t reset)70 void __dead2 plat_soft_reset(uint32_t reset)
71 {
72 	if (reset == SOFT_RESET_L3) {
73 		mmio_setbits_32(CRMU_IHOST_SW_PERSISTENT_REG1, reset);
74 		mmio_write_32(CRMU_MAIL_BOX0, 0x0);
75 		mmio_write_32(CRMU_MAIL_BOX1, 0xFFFFFFFF);
76 	}
77 
78 	if (reset != SOFT_SYS_RESET_L1)
79 		reset = SOFT_PWR_UP_RESET_L0;
80 
81 	if (reset == SOFT_PWR_UP_RESET_L0)
82 		INFO("L0 RESET...\n");
83 
84 	if (reset == SOFT_SYS_RESET_L1)
85 		INFO("L1 RESET...\n");
86 
87 	console_flush();
88 
89 	mmio_clrbits_32(CRMU_SOFT_RESET_CTRL, 1 << reset);
90 
91 	while (1) {
92 		;
93 	}
94 }
95