| /tf-a-ffa_el3_spmc/plat/brcm/board/stingray/include/ |
| A D | scp_utils.h | 20 #define SCP_READ_CFG(cfg) mmio_read_32(CRMU_CFG_BASE + \ argument
22 #define SCP_WRITE_CFG(cfg, value) mmio_write_32(CRMU_CFG_BASE + \ argument
25 #define SCP_READ_CFG16(cfg) mmio_read_16(CRMU_CFG_BASE + \ argument
27 #define SCP_WRITE_CFG16(cfg, value) mmio_write_16(CRMU_CFG_BASE + \ argument
30 #define SCP_READ_CFG8(cfg) mmio_read_8(CRMU_CFG_BASE + \ argument
32 #define SCP_WRITE_CFG8(cfg, value) mmio_write_8(CRMU_CFG_BASE + \ argument
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| /tf-a-ffa_el3_spmc/include/common/ |
| A D | interrupt_props.h | 13 #define INTR_PROP_DESC(num, pri, grp, cfg) \ argument
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| /tf-a-ffa_el3_spmc/plat/mediatek/mt8195/drivers/mcdi/ |
| A D | mt_cpu_pm_cpc.c | 162 static void mtk_cpc_config(uint32_t cfg, uint32_t data) in mtk_cpc_config()
205 static uint32_t mtk_cpc_read_config(uint32_t cfg) in mtk_cpc_read_config()
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| /tf-a-ffa_el3_spmc/plat/mediatek/mt8192/drivers/mcdi/ |
| A D | mt_cpu_pm_cpc.c | 162 static void mtk_cpc_config(uint32_t cfg, uint32_t data) in mtk_cpc_config()
205 static uint32_t mtk_cpc_read_config(uint32_t cfg) in mtk_cpc_read_config()
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| /tf-a-ffa_el3_spmc/plat/nvidia/tegra/soc/t210/ |
| A D | plat_psci_handlers.c | 202 uint32_t cfg; in tegra_soc_pwr_domain_suspend() local
436 uint32_t cfg; in tegra_soc_pwr_domain_on_finish() local
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| /tf-a-ffa_el3_spmc/drivers/arm/gic/v3/ |
| A D | gicrv3_helpers.c | 130 void gicr_set_icfgr(uintptr_t base, unsigned int id, unsigned int cfg) in gicr_set_icfgr()
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| A D | gicdv3_helpers.c | 22 void gicd_set_icfgr(uintptr_t base, unsigned int id, unsigned int cfg) in gicd_set_icfgr()
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| /tf-a-ffa_el3_spmc/drivers/st/bsec/ |
| A D | bsec.c | 180 uint32_t bsec_set_config(struct bsec_config *cfg) in bsec_set_config()
225 uint32_t bsec_get_config(struct bsec_config *cfg) in bsec_get_config()
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| /tf-a-ffa_el3_spmc/drivers/arm/gic/v2/ |
| A D | gicv2_main.c | 552 void gicv2_interrupt_set_cfg(unsigned int id, unsigned int cfg) in gicv2_interrupt_set_cfg()
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| A D | gicdv2_helpers.c | 327 void gicd_set_icfgr(uintptr_t base, unsigned int id, unsigned int cfg) in gicd_set_icfgr()
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| /tf-a-ffa_el3_spmc/drivers/mtd/nand/ |
| A D | spi_nand.c | 67 uint8_t cfg = spinand_dev.cfg_cache; in spi_nand_update_cfg() local
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| /tf-a-ffa_el3_spmc/include/plat/marvell/armada/a8k/common/ |
| A D | armada_common.h | 107 } cfg; member
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| /tf-a-ffa_el3_spmc/drivers/amlogic/crypto/ |
| A D | sha_dma.c | 19 uint32_t cfg; member
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| /tf-a-ffa_el3_spmc/drivers/marvell/comphy/ |
| A D | phy-comphy-3700.c | 590 uint32_t mask, data, addr, cfg, ref_clk; in mvebu_a3700_comphy_usb3_power_on() local
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| /tf-a-ffa_el3_spmc/drivers/arm/gic/common/ |
| A D | gic_common.c | 329 void gicd_set_icfgr(uintptr_t base, unsigned int id, unsigned int cfg) in gicd_set_icfgr()
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| /tf-a-ffa_el3_spmc/include/drivers/brcm/emmc/ |
| A D | emmc_chal_sd.h | 165 struct sd_cfg cfg; /* SD configuration */ member
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| /tf-a-ffa_el3_spmc/plat/intel/soc/common/drivers/qspi/ |
| A D | cadence_qspi.c | 84 uint32_t cfg = mmio_read_32(CAD_QSPI_OFFSET + CAD_QSPI_CFG); in cad_qspi_timing_config() local
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| /tf-a-ffa_el3_spmc/plat/brcm/board/stingray/src/ |
| A D | iommu.c | 284 struct arm_smmu_cfg cfg[NUM_OF_SMRS]; member
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