1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
4  *
5  */
6 
7 #include <common.h>
8 #include <asm/arch/clock_manager.h>
9 #include <asm/io.h>
10 #include <asm/arch/handoff_s10.h>
11 #include <asm/arch/system_manager.h>
12 
cm_get_default_config(void)13 const struct cm_config * const cm_get_default_config(void)
14 {
15 #ifdef CONFIG_SPL_BUILD
16 	struct cm_config *cm_handoff_cfg = (struct cm_config *)
17 		(S10_HANDOFF_CLOCK + S10_HANDOFF_OFFSET_DATA);
18 	u32 *conversion = (u32 *)cm_handoff_cfg;
19 	u32 i;
20 	u32 handoff_clk = readl(S10_HANDOFF_CLOCK);
21 
22 	if (swab32(handoff_clk) == S10_HANDOFF_MAGIC_CLOCK) {
23 		writel(swab32(handoff_clk), S10_HANDOFF_CLOCK);
24 		for (i = 0; i < (sizeof(*cm_handoff_cfg) / sizeof(u32)); i++)
25 			conversion[i] = swab32(conversion[i]);
26 		return cm_handoff_cfg;
27 	} else if (handoff_clk == S10_HANDOFF_MAGIC_CLOCK) {
28 		return cm_handoff_cfg;
29 	}
30 #endif
31 	return NULL;
32 }
33 
cm_get_osc_clk_hz(void)34 const unsigned int cm_get_osc_clk_hz(void)
35 {
36 #ifdef CONFIG_SPL_BUILD
37 
38 	u32 clock = readl(HANDOFF_CLOCK_OSC);
39 
40 	writel(clock,
41 	       socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD1);
42 #endif
43 	return readl(socfpga_get_sysmgr_addr() +
44 		     SYSMGR_SOC64_BOOT_SCRATCH_COLD1);
45 }
46 
cm_get_intosc_clk_hz(void)47 const unsigned int cm_get_intosc_clk_hz(void)
48 {
49 	return CLKMGR_INTOSC_HZ;
50 }
51 
cm_get_fpga_clk_hz(void)52 const unsigned int cm_get_fpga_clk_hz(void)
53 {
54 #ifdef CONFIG_SPL_BUILD
55 	u32 clock = readl(HANDOFF_CLOCK_FPGA);
56 
57 	writel(clock,
58 	       socfpga_get_sysmgr_addr() + SYSMGR_SOC64_BOOT_SCRATCH_COLD2);
59 #endif
60 	return readl(socfpga_get_sysmgr_addr() +
61 		     SYSMGR_SOC64_BOOT_SCRATCH_COLD2);
62 }
63