1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
4 */
5
6 #include <common.h>
7 #include <command.h>
8 #include <init.h>
9 #include <wait_bit.h>
10 #include <asm/global_data.h>
11 #include <asm/io.h>
12 #include <asm/arch/clock_manager.h>
13
14 DECLARE_GLOBAL_DATA_PTR;
15
cm_wait_for_lock(u32 mask)16 void cm_wait_for_lock(u32 mask)
17 {
18 u32 inter_val;
19 u32 retry = 0;
20 do {
21 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
22 inter_val = readl(socfpga_get_clkmgr_addr() +
23 CLKMGR_INTER) & mask;
24 #else
25 inter_val = readl(socfpga_get_clkmgr_addr() +
26 CLKMGR_STAT) & mask;
27 #endif
28 /* Wait for stable lock */
29 if (inter_val == mask)
30 retry++;
31 else
32 retry = 0;
33 if (retry >= 10)
34 break;
35 } while (1);
36 }
37
38 /* function to poll in the fsm busy bit */
cm_wait_for_fsm(void)39 int cm_wait_for_fsm(void)
40 {
41 return wait_for_bit_le32((const void *)(socfpga_get_clkmgr_addr() +
42 CLKMGR_STAT), CLKMGR_STAT_BUSY, false, 20000,
43 false);
44 }
45
set_cpu_clk_info(void)46 int set_cpu_clk_info(void)
47 {
48 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
49 /* Calculate the clock frequencies required for drivers */
50 cm_get_l4_sp_clk_hz();
51 cm_get_mmc_controller_clk_hz();
52 #endif
53
54 gd->bd->bi_arm_freq = cm_get_mpu_clk_hz() / 1000000;
55 gd->bd->bi_dsp_freq = 0;
56
57 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
58 gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 1000000;
59 #else
60 gd->bd->bi_ddr_freq = 0;
61 #endif
62
63 return 0;
64 }
65
66 #ifndef CONFIG_SPL_BUILD
do_showclocks(struct cmd_tbl * cmdtp,int flag,int argc,char * const argv[])67 static int do_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
68 char *const argv[])
69 {
70 cm_print_clock_quick_summary();
71 return 0;
72 }
73
74 U_BOOT_CMD(
75 clocks, CONFIG_SYS_MAXARGS, 1, do_showclocks,
76 "display clocks",
77 ""
78 );
79 #endif
80