1 /*
2  * Cobalt Qube/Raq PCI support
3  *
4  * This file is subject to the terms and conditions of the GNU General Public
5  * License.  See the file "COPYING" in the main directory of this archive
6  * for more details.
7  *
8  * Copyright (C) 1995, 1996, 1997, 2002, 2003 by Ralf Baechle
9  * Copyright (C) 2001, 2002, 2003 by Liam Davies (ldavies@agile.tv)
10  */
11 #include <linux/types.h>
12 #include <linux/pci.h>
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 
16 #include <asm/io.h>
17 #include <asm/gt64120.h>
18 
19 #include <cobalt.h>
20 #include <irq.h>
21 
22 /*
23  * PCI slot numbers
24  */
25 #define COBALT_PCICONF_CPU	0x06
26 #define COBALT_PCICONF_ETH0	0x07
27 #define COBALT_PCICONF_RAQSCSI	0x08
28 #define COBALT_PCICONF_VIA	0x09
29 #define COBALT_PCICONF_PCISLOT	0x0A
30 #define COBALT_PCICONF_ETH1	0x0C
31 
32 /*
33  * The Cobalt board ID information.  The boards have an ID number wired
34  * into the VIA that is available in the high nibble of register 94.
35  */
36 #define VIA_COBALT_BRD_ID_REG  0x94
37 #define VIA_COBALT_BRD_REG_to_ID(reg)	((unsigned char)(reg) >> 4)
38 
39 /*
40  * Default value of PCI Class Code on GT64111 is PCI_CLASS_MEMORY_OTHER (0x0580)
41  * instead of PCI_CLASS_BRIDGE_HOST (0x0600). Galileo explained this choice in
42  * document "GT-64111 System Controller for RC4640, RM523X and VR4300 CPUs",
43  * section "6.5.3 PCI Autoconfiguration at RESET":
44  *
45  *   Some PCs refuse to configure host bridges if they are found plugged into
46  *   a PCI slot (ask the BIOS vendors why...). The "Memory Controller" Class
47  *   Code does not cause a problem for these non-compliant BIOSes, so we used
48  *   this as the default in the GT-64111.
49  *
50  * So fix the incorrect default value of PCI Class Code. More details are on:
51  * https://lore.kernel.org/r/20211102154831.xtrlgrmrizl5eidl@pali/
52  * https://lore.kernel.org/r/20211102150201.GA11675@alpha.franken.de/
53  */
qube_raq_galileo_early_fixup(struct pci_dev * dev)54 static void qube_raq_galileo_early_fixup(struct pci_dev *dev)
55 {
56 	if (dev->devfn == PCI_DEVFN(0, 0) &&
57 		(dev->class >> 8) == PCI_CLASS_MEMORY_OTHER) {
58 
59 		dev->class = (PCI_CLASS_BRIDGE_HOST << 8) | (dev->class & 0xff);
60 
61 		printk(KERN_INFO "Galileo: fixed bridge class\n");
62 	}
63 }
64 
65 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111,
66 	 qube_raq_galileo_early_fixup);
67 
qube_raq_via_bmIDE_fixup(struct pci_dev * dev)68 static void qube_raq_via_bmIDE_fixup(struct pci_dev *dev)
69 {
70 	unsigned short cfgword;
71 	unsigned char lt;
72 
73 	/* Enable Bus Mastering and fast back to back. */
74 	pci_read_config_word(dev, PCI_COMMAND, &cfgword);
75 	cfgword |= (PCI_COMMAND_FAST_BACK | PCI_COMMAND_MASTER);
76 	pci_write_config_word(dev, PCI_COMMAND, cfgword);
77 
78 	/* Enable both ide interfaces. ROM only enables primary one.  */
79 	pci_write_config_byte(dev, 0x40, 0xb);
80 
81 	/* Set latency timer to reasonable value. */
82 	pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lt);
83 	if (lt < 64)
84 		pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
85 	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8);
86 }
87 
88 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1,
89 	 qube_raq_via_bmIDE_fixup);
90 
qube_raq_galileo_fixup(struct pci_dev * dev)91 static void qube_raq_galileo_fixup(struct pci_dev *dev)
92 {
93 	if (dev->devfn != PCI_DEVFN(0, 0))
94 		return;
95 
96 	/* Fix PCI latency-timer and cache-line-size values in Galileo
97 	 * host bridge.
98 	 */
99 	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
100 	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8);
101 
102 	/*
103 	 * The code described by the comment below has been removed
104 	 * as it causes bus mastering by the Ethernet controllers
105 	 * to break under any kind of network load. We always set
106 	 * the retry timeouts to their maximum.
107 	 *
108 	 * --x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--x--
109 	 *
110 	 * On all machines prior to Q2, we had the STOP line disconnected
111 	 * from Galileo to VIA on PCI.	The new Galileo does not function
112 	 * correctly unless we have it connected.
113 	 *
114 	 * Therefore we must set the disconnect/retry cycle values to
115 	 * something sensible when using the new Galileo.
116 	 */
117 
118 	printk(KERN_INFO "Galileo: revision %u\n", dev->revision);
119 
120 #if 0
121 	if (dev->revision >= 0x10) {
122 		/* New Galileo, assumes PCI stop line to VIA is connected. */
123 		GT_WRITE(GT_PCI0_TOR_OFS, 0x4020);
124 	} else if (dev->revision == 0x1 || dev->revision == 0x2)
125 #endif
126 	{
127 		signed int timeo;
128 		/* XXX WE MUST DO THIS ELSE GALILEO LOCKS UP! -DaveM */
129 		timeo = GT_READ(GT_PCI0_TOR_OFS);
130 		/* Old Galileo, assumes PCI STOP line to VIA is disconnected. */
131 		GT_WRITE(GT_PCI0_TOR_OFS,
132 			(0xff << 16) |		/* retry count */
133 			(0xff << 8) |		/* timeout 1   */
134 			0xff);			/* timeout 0   */
135 
136 		/* enable PCI retry exceeded interrupt */
137 		GT_WRITE(GT_INTRMASK_OFS, GT_INTR_RETRYCTR0_MSK | GT_READ(GT_INTRMASK_OFS));
138 	}
139 }
140 
141 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_GT64111,
142 	 qube_raq_galileo_fixup);
143 
144 int cobalt_board_id;
145 
qube_raq_via_board_id_fixup(struct pci_dev * dev)146 static void qube_raq_via_board_id_fixup(struct pci_dev *dev)
147 {
148 	u8 id;
149 	int retval;
150 
151 	retval = pci_read_config_byte(dev, VIA_COBALT_BRD_ID_REG, &id);
152 	if (retval) {
153 		panic("Cannot read board ID");
154 		return;
155 	}
156 
157 	cobalt_board_id = VIA_COBALT_BRD_REG_to_ID(id);
158 
159 	printk(KERN_INFO "Cobalt board ID: %d\n", cobalt_board_id);
160 }
161 
162 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0,
163 	 qube_raq_via_board_id_fixup);
164 
165 static char irq_tab_qube1[] = {
166   [COBALT_PCICONF_CPU]	   = 0,
167   [COBALT_PCICONF_ETH0]	   = QUBE1_ETH0_IRQ,
168   [COBALT_PCICONF_RAQSCSI] = SCSI_IRQ,
169   [COBALT_PCICONF_VIA]	   = 0,
170   [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ,
171   [COBALT_PCICONF_ETH1]	   = 0
172 };
173 
174 static char irq_tab_cobalt[] = {
175   [COBALT_PCICONF_CPU]	   = 0,
176   [COBALT_PCICONF_ETH0]	   = ETH0_IRQ,
177   [COBALT_PCICONF_RAQSCSI] = SCSI_IRQ,
178   [COBALT_PCICONF_VIA]	   = 0,
179   [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ,
180   [COBALT_PCICONF_ETH1]	   = ETH1_IRQ
181 };
182 
183 static char irq_tab_raq2[] = {
184   [COBALT_PCICONF_CPU]	   = 0,
185   [COBALT_PCICONF_ETH0]	   = ETH0_IRQ,
186   [COBALT_PCICONF_RAQSCSI] = RAQ2_SCSI_IRQ,
187   [COBALT_PCICONF_VIA]	   = 0,
188   [COBALT_PCICONF_PCISLOT] = PCISLOT_IRQ,
189   [COBALT_PCICONF_ETH1]	   = ETH1_IRQ
190 };
191 
pcibios_map_irq(const struct pci_dev * dev,u8 slot,u8 pin)192 int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
193 {
194 	if (cobalt_board_id <= COBALT_BRD_ID_QUBE1)
195 		return irq_tab_qube1[slot];
196 
197 	if (cobalt_board_id == COBALT_BRD_ID_RAQ2)
198 		return irq_tab_raq2[slot];
199 
200 	return irq_tab_cobalt[slot];
201 }
202 
203 /* Do platform specific device initialization at pci_enable_device() time */
pcibios_plat_dev_init(struct pci_dev * dev)204 int pcibios_plat_dev_init(struct pci_dev *dev)
205 {
206 	return 0;
207 }
208