1 /*
2 * Copyright (c) 2019, Intel Corporation. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <common/debug.h>
8 #include <errno.h>
9 #include <lib/mmio.h>
10
11 #include "socfpga_mailbox.h"
12 #include "socfpga_reset_manager.h"
13 #include "socfpga_system_manager.h"
14
15
deassert_peripheral_reset(void)16 void deassert_peripheral_reset(void)
17 {
18 mmio_clrbits_32(SOCFPGA_RSTMGR(PER1MODRST),
19 RSTMGR_FIELD(PER1, WATCHDOG0) |
20 RSTMGR_FIELD(PER1, WATCHDOG1) |
21 RSTMGR_FIELD(PER1, WATCHDOG2) |
22 RSTMGR_FIELD(PER1, WATCHDOG3) |
23 RSTMGR_FIELD(PER1, L4SYSTIMER0) |
24 RSTMGR_FIELD(PER1, L4SYSTIMER1) |
25 RSTMGR_FIELD(PER1, SPTIMER0) |
26 RSTMGR_FIELD(PER1, SPTIMER1) |
27 RSTMGR_FIELD(PER1, I2C0) |
28 RSTMGR_FIELD(PER1, I2C1) |
29 RSTMGR_FIELD(PER1, I2C2) |
30 RSTMGR_FIELD(PER1, I2C3) |
31 RSTMGR_FIELD(PER1, I2C4) |
32 RSTMGR_FIELD(PER1, UART0) |
33 RSTMGR_FIELD(PER1, UART1) |
34 RSTMGR_FIELD(PER1, GPIO0) |
35 RSTMGR_FIELD(PER1, GPIO1));
36
37 mmio_clrbits_32(SOCFPGA_RSTMGR(PER0MODRST),
38 RSTMGR_FIELD(PER0, EMAC0OCP) |
39 RSTMGR_FIELD(PER0, EMAC1OCP) |
40 RSTMGR_FIELD(PER0, EMAC2OCP) |
41 RSTMGR_FIELD(PER0, USB0OCP) |
42 RSTMGR_FIELD(PER0, USB1OCP) |
43 RSTMGR_FIELD(PER0, NANDOCP) |
44 RSTMGR_FIELD(PER0, SDMMCOCP) |
45 RSTMGR_FIELD(PER0, DMAOCP));
46
47 mmio_clrbits_32(SOCFPGA_RSTMGR(PER0MODRST),
48 RSTMGR_FIELD(PER0, EMAC0) |
49 RSTMGR_FIELD(PER0, EMAC1) |
50 RSTMGR_FIELD(PER0, EMAC2) |
51 RSTMGR_FIELD(PER0, USB0) |
52 RSTMGR_FIELD(PER0, USB1) |
53 RSTMGR_FIELD(PER0, NAND) |
54 RSTMGR_FIELD(PER0, SDMMC) |
55 RSTMGR_FIELD(PER0, DMA) |
56 RSTMGR_FIELD(PER0, SPIM0) |
57 RSTMGR_FIELD(PER0, SPIM1) |
58 RSTMGR_FIELD(PER0, SPIS0) |
59 RSTMGR_FIELD(PER0, SPIS1) |
60 RSTMGR_FIELD(PER0, EMACPTP) |
61 RSTMGR_FIELD(PER0, DMAIF0) |
62 RSTMGR_FIELD(PER0, DMAIF1) |
63 RSTMGR_FIELD(PER0, DMAIF2) |
64 RSTMGR_FIELD(PER0, DMAIF3) |
65 RSTMGR_FIELD(PER0, DMAIF4) |
66 RSTMGR_FIELD(PER0, DMAIF5) |
67 RSTMGR_FIELD(PER0, DMAIF6) |
68 RSTMGR_FIELD(PER0, DMAIF7));
69
70 #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX
71 mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST),
72 RSTMGR_FIELD(BRG, MPFE));
73 #endif
74 }
75
config_hps_hs_before_warm_reset(void)76 void config_hps_hs_before_warm_reset(void)
77 {
78 uint32_t or_mask = 0;
79
80 or_mask |= RSTMGR_HDSKEN_SDRSELFREFEN;
81 or_mask |= RSTMGR_HDSKEN_FPGAHSEN;
82 or_mask |= RSTMGR_HDSKEN_ETRSTALLEN;
83 or_mask |= RSTMGR_HDSKEN_L2FLUSHEN;
84 or_mask |= RSTMGR_HDSKEN_L3NOC_DBG;
85 or_mask |= RSTMGR_HDSKEN_DEBUG_L3NOC;
86
87 mmio_setbits_32(SOCFPGA_RSTMGR(HDSKEN), or_mask);
88 }
89
poll_idle_status(uint32_t addr,uint32_t mask,uint32_t match)90 static int poll_idle_status(uint32_t addr, uint32_t mask, uint32_t match)
91 {
92 int time_out = 1000;
93
94 while (time_out--) {
95 if ((mmio_read_32(addr) & mask) == match) {
96 return 0;
97 }
98 }
99 return -ETIMEDOUT;
100 }
101
socfpga_bridges_enable(void)102 int socfpga_bridges_enable(void)
103 {
104 /* Clear idle request */
105 mmio_setbits_32(SOCFPGA_SYSMGR(NOC_IDLEREQ_CLR), ~0);
106
107 /* De-assert all bridges */
108 mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST), ~0);
109
110 /* Wait until idle ack becomes 0 */
111 return poll_idle_status(SOCFPGA_SYSMGR(NOC_IDLEACK),
112 IDLE_DATA_MASK, 0);
113 }
114
socfpga_bridges_disable(void)115 int socfpga_bridges_disable(void)
116 {
117 /* Set idle request */
118 mmio_write_32(SOCFPGA_SYSMGR(NOC_IDLEREQ_SET), ~0);
119
120 /* Enable NOC timeout */
121 mmio_setbits_32(SOCFPGA_SYSMGR(NOC_TIMEOUT), 1);
122
123 /* Wait until each idle ack bit toggle to 1 */
124 if (poll_idle_status(SOCFPGA_SYSMGR(NOC_IDLEACK),
125 IDLE_DATA_MASK, IDLE_DATA_MASK))
126 return -ETIMEDOUT;
127
128 /* Wait until each idle status bit toggle to 1 */
129 if (poll_idle_status(SOCFPGA_SYSMGR(NOC_IDLESTATUS),
130 IDLE_DATA_MASK, IDLE_DATA_MASK))
131 return -ETIMEDOUT;
132
133 /* Assert all bridges */
134 #if PLATFORM_MODEL == PLAT_SOCFPGA_STRATIX10
135 mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
136 ~(RSTMGR_FIELD(BRG, DDRSCH) | RSTMGR_FIELD(BRG, FPGA2SOC)));
137 #elif PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX
138 mmio_setbits_32(SOCFPGA_RSTMGR(BRGMODRST),
139 ~(RSTMGR_FIELD(BRG, MPFE) | RSTMGR_FIELD(BRG, FPGA2SOC)));
140 #endif
141
142 /* Disable NOC timeout */
143 mmio_clrbits_32(SOCFPGA_SYSMGR(NOC_TIMEOUT), 1);
144
145 return 0;
146 }
147