1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * From Coreboot file of same name
4 *
5 * Copyright (C) 2007-2009 coresystems GmbH
6 * Copyright (C) 2011 The Chromium Authors
7 */
8
9 #include <common.h>
10 #include <cpu.h>
11 #include <dm.h>
12 #include <fdtdec.h>
13 #include <log.h>
14 #include <malloc.h>
15 #include <asm/cpu.h>
16 #include <asm/cpu_common.h>
17 #include <asm/cpu_x86.h>
18 #include <asm/global_data.h>
19 #include <asm/msr.h>
20 #include <asm/msr-index.h>
21 #include <asm/mtrr.h>
22 #include <asm/processor.h>
23 #include <asm/speedstep.h>
24 #include <asm/turbo.h>
25 #include <asm/arch/model_206ax.h>
26
27 DECLARE_GLOBAL_DATA_PTR;
28
enable_vmx(void)29 static void enable_vmx(void)
30 {
31 struct cpuid_result regs;
32 #ifdef CONFIG_ENABLE_VMX
33 int enable = true;
34 #else
35 int enable = false;
36 #endif
37 msr_t msr;
38
39 regs = cpuid(1);
40 /* Check that the VMX is supported before reading or writing the MSR. */
41 if (!((regs.ecx & CPUID_VMX) || (regs.ecx & CPUID_SMX)))
42 return;
43
44 msr = msr_read(MSR_IA32_FEATURE_CONTROL);
45
46 if (msr.lo & (1 << 0)) {
47 debug("VMX is locked, so %s will do nothing\n", __func__);
48 /* VMX locked. If we set it again we get an illegal
49 * instruction
50 */
51 return;
52 }
53
54 /* The IA32_FEATURE_CONTROL MSR may initialize with random values.
55 * It must be cleared regardless of VMX config setting.
56 */
57 msr.hi = 0;
58 msr.lo = 0;
59
60 debug("%s VMX\n", enable ? "Enabling" : "Disabling");
61
62 /*
63 * Even though the Intel manual says you must set the lock bit in
64 * addition to the VMX bit in order for VMX to work, it is incorrect.
65 * Thus we leave it unlocked for the OS to manage things itself.
66 * This is good for a few reasons:
67 * - No need to reflash the bios just to toggle the lock bit.
68 * - The VMX bits really really should match each other across cores,
69 * so hard locking it on one while another has the opposite setting
70 * can easily lead to crashes as code using VMX migrates between
71 * them.
72 * - Vendors that want to "upsell" from a bios that disables+locks to
73 * one that doesn't is sleazy.
74 * By leaving this to the OS (e.g. Linux), people can do exactly what
75 * they want on the fly, and do it correctly (e.g. across multiple
76 * cores).
77 */
78 if (enable) {
79 msr.lo |= (1 << 2);
80 if (regs.ecx & CPUID_SMX)
81 msr.lo |= (1 << 1);
82 }
83
84 msr_write(MSR_IA32_FEATURE_CONTROL, msr);
85 }
86
87 /* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */
88 static const u8 power_limit_time_sec_to_msr[] = {
89 [0] = 0x00,
90 [1] = 0x0a,
91 [2] = 0x0b,
92 [3] = 0x4b,
93 [4] = 0x0c,
94 [5] = 0x2c,
95 [6] = 0x4c,
96 [7] = 0x6c,
97 [8] = 0x0d,
98 [10] = 0x2d,
99 [12] = 0x4d,
100 [14] = 0x6d,
101 [16] = 0x0e,
102 [20] = 0x2e,
103 [24] = 0x4e,
104 [28] = 0x6e,
105 [32] = 0x0f,
106 [40] = 0x2f,
107 [48] = 0x4f,
108 [56] = 0x6f,
109 [64] = 0x10,
110 [80] = 0x30,
111 [96] = 0x50,
112 [112] = 0x70,
113 [128] = 0x11,
114 };
115
116 /* Convert POWER_LIMIT_1_TIME MSR value to seconds */
117 static const u8 power_limit_time_msr_to_sec[] = {
118 [0x00] = 0,
119 [0x0a] = 1,
120 [0x0b] = 2,
121 [0x4b] = 3,
122 [0x0c] = 4,
123 [0x2c] = 5,
124 [0x4c] = 6,
125 [0x6c] = 7,
126 [0x0d] = 8,
127 [0x2d] = 10,
128 [0x4d] = 12,
129 [0x6d] = 14,
130 [0x0e] = 16,
131 [0x2e] = 20,
132 [0x4e] = 24,
133 [0x6e] = 28,
134 [0x0f] = 32,
135 [0x2f] = 40,
136 [0x4f] = 48,
137 [0x6f] = 56,
138 [0x10] = 64,
139 [0x30] = 80,
140 [0x50] = 96,
141 [0x70] = 112,
142 [0x11] = 128,
143 };
144
cpu_ivybridge_config_tdp_levels(void)145 bool cpu_ivybridge_config_tdp_levels(void)
146 {
147 struct cpuid_result result;
148
149 /* Minimum CPU revision */
150 result = cpuid(1);
151 if (result.eax < IVB_CONFIG_TDP_MIN_CPUID)
152 return false;
153
154 return cpu_config_tdp_levels();
155 }
156
157 /*
158 * Configure processor power limits if possible
159 * This must be done AFTER set of BIOS_RESET_CPL
160 */
set_power_limits(u8 power_limit_1_time)161 void set_power_limits(u8 power_limit_1_time)
162 {
163 msr_t msr = msr_read(MSR_PLATFORM_INFO);
164 msr_t limit;
165 unsigned power_unit;
166 unsigned tdp, min_power, max_power, max_time;
167 u8 power_limit_1_val;
168
169 if (power_limit_1_time > ARRAY_SIZE(power_limit_time_sec_to_msr))
170 return;
171
172 if (!(msr.lo & PLATFORM_INFO_SET_TDP))
173 return;
174
175 /* Get units */
176 msr = msr_read(MSR_PKG_POWER_SKU_UNIT);
177 power_unit = 2 << ((msr.lo & 0xf) - 1);
178
179 /* Get power defaults for this SKU */
180 msr = msr_read(MSR_PKG_POWER_SKU);
181 tdp = msr.lo & 0x7fff;
182 min_power = (msr.lo >> 16) & 0x7fff;
183 max_power = msr.hi & 0x7fff;
184 max_time = (msr.hi >> 16) & 0x7f;
185
186 debug("CPU TDP: %u Watts\n", tdp / power_unit);
187
188 if (power_limit_time_msr_to_sec[max_time] > power_limit_1_time)
189 power_limit_1_time = power_limit_time_msr_to_sec[max_time];
190
191 if (min_power > 0 && tdp < min_power)
192 tdp = min_power;
193
194 if (max_power > 0 && tdp > max_power)
195 tdp = max_power;
196
197 power_limit_1_val = power_limit_time_sec_to_msr[power_limit_1_time];
198
199 /* Set long term power limit to TDP */
200 limit.lo = 0;
201 limit.lo |= tdp & PKG_POWER_LIMIT_MASK;
202 limit.lo |= PKG_POWER_LIMIT_EN;
203 limit.lo |= (power_limit_1_val & PKG_POWER_LIMIT_TIME_MASK) <<
204 PKG_POWER_LIMIT_TIME_SHIFT;
205
206 /* Set short term power limit to 1.25 * TDP */
207 limit.hi = 0;
208 limit.hi |= ((tdp * 125) / 100) & PKG_POWER_LIMIT_MASK;
209 limit.hi |= PKG_POWER_LIMIT_EN;
210 /* Power limit 2 time is only programmable on SNB EP/EX */
211
212 msr_write(MSR_PKG_POWER_LIMIT, limit);
213
214 /* Use nominal TDP values for CPUs with configurable TDP */
215 if (cpu_ivybridge_config_tdp_levels()) {
216 msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
217 limit.hi = 0;
218 limit.lo = msr.lo & 0xff;
219 msr_write(MSR_TURBO_ACTIVATION_RATIO, limit);
220 }
221 }
222
configure_c_states(void)223 static void configure_c_states(void)
224 {
225 struct cpuid_result result;
226 msr_t msr;
227
228 msr = msr_read(MSR_PMG_CST_CONFIG_CTL);
229 msr.lo |= (1 << 28); /* C1 Auto Undemotion Enable */
230 msr.lo |= (1 << 27); /* C3 Auto Undemotion Enable */
231 msr.lo |= (1 << 26); /* C1 Auto Demotion Enable */
232 msr.lo |= (1 << 25); /* C3 Auto Demotion Enable */
233 msr.lo &= ~(1 << 10); /* Disable IO MWAIT redirection */
234 msr.lo |= 7; /* No package C-state limit */
235 msr_write(MSR_PMG_CST_CONFIG_CTL, msr);
236
237 msr = msr_read(MSR_PMG_IO_CAPTURE_ADR);
238 msr.lo &= ~0x7ffff;
239 msr.lo |= (PMB0_BASE + 4); /* LVL_2 base address */
240 msr.lo |= (2 << 16); /* CST Range: C7 is max C-state */
241 msr_write(MSR_PMG_IO_CAPTURE_ADR, msr);
242
243 msr = msr_read(MSR_MISC_PWR_MGMT);
244 msr.lo &= ~(1 << 0); /* Enable P-state HW_ALL coordination */
245 msr_write(MSR_MISC_PWR_MGMT, msr);
246
247 msr = msr_read(MSR_POWER_CTL);
248 msr.lo |= (1 << 18); /* Enable Energy Perf Bias MSR 0x1b0 */
249 msr.lo |= (1 << 1); /* C1E Enable */
250 msr.lo |= (1 << 0); /* Bi-directional PROCHOT# */
251 msr_write(MSR_POWER_CTL, msr);
252
253 /* C3 Interrupt Response Time Limit */
254 msr.hi = 0;
255 msr.lo = IRTL_VALID | IRTL_1024_NS | 0x50;
256 msr_write(MSR_PKGC3_IRTL, msr);
257
258 /* C6 Interrupt Response Time Limit */
259 msr.hi = 0;
260 msr.lo = IRTL_VALID | IRTL_1024_NS | 0x68;
261 msr_write(MSR_PKGC6_IRTL, msr);
262
263 /* C7 Interrupt Response Time Limit */
264 msr.hi = 0;
265 msr.lo = IRTL_VALID | IRTL_1024_NS | 0x6D;
266 msr_write(MSR_PKGC7_IRTL, msr);
267
268 /* Primary Plane Current Limit */
269 msr = msr_read(MSR_PP0_CURRENT_CONFIG);
270 msr.lo &= ~0x1fff;
271 msr.lo |= PP0_CURRENT_LIMIT;
272 msr_write(MSR_PP0_CURRENT_CONFIG, msr);
273
274 /* Secondary Plane Current Limit */
275 msr = msr_read(MSR_PP1_CURRENT_CONFIG);
276 msr.lo &= ~0x1fff;
277 result = cpuid(1);
278 if (result.eax >= 0x30600)
279 msr.lo |= PP1_CURRENT_LIMIT_IVB;
280 else
281 msr.lo |= PP1_CURRENT_LIMIT_SNB;
282 msr_write(MSR_PP1_CURRENT_CONFIG, msr);
283 }
284
configure_misc(void)285 static void configure_misc(void)
286 {
287 msr_t msr;
288
289 msr = msr_read(IA32_MISC_ENABLE);
290 msr.lo |= (1 << 0); /* Fast String enable */
291 msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */
292 msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */
293 msr_write(IA32_MISC_ENABLE, msr);
294
295 /* Disable Thermal interrupts */
296 msr.lo = 0;
297 msr.hi = 0;
298 msr_write(IA32_THERM_INTERRUPT, msr);
299
300 /* Enable package critical interrupt only */
301 msr.lo = 1 << 4;
302 msr.hi = 0;
303 msr_write(IA32_PACKAGE_THERM_INTERRUPT, msr);
304 }
305
enable_lapic_tpr(void)306 static void enable_lapic_tpr(void)
307 {
308 msr_t msr;
309
310 msr = msr_read(MSR_PIC_MSG_CONTROL);
311 msr.lo &= ~(1 << 10); /* Enable APIC TPR updates */
312 msr_write(MSR_PIC_MSG_CONTROL, msr);
313 }
314
configure_dca_cap(void)315 static void configure_dca_cap(void)
316 {
317 struct cpuid_result cpuid_regs;
318 msr_t msr;
319
320 /* Check feature flag in CPUID.(EAX=1):ECX[18]==1 */
321 cpuid_regs = cpuid(1);
322 if (cpuid_regs.ecx & (1 << 18)) {
323 msr = msr_read(IA32_PLATFORM_DCA_CAP);
324 msr.lo |= 1;
325 msr_write(IA32_PLATFORM_DCA_CAP, msr);
326 }
327 }
328
set_max_ratio(void)329 static void set_max_ratio(void)
330 {
331 msr_t msr;
332 uint ratio;
333
334 /* Check for configurable TDP option */
335 if (cpu_ivybridge_config_tdp_levels()) {
336 /* Set to nominal TDP ratio */
337 msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
338 ratio = msr.lo & 0xff;
339 } else {
340 /* Platform Info bits 15:8 give max ratio */
341 msr = msr_read(MSR_PLATFORM_INFO);
342 ratio = (msr.lo & 0xff00) >> 8;
343 }
344 cpu_set_perf_control(ratio);
345 }
346
set_energy_perf_bias(u8 policy)347 static void set_energy_perf_bias(u8 policy)
348 {
349 msr_t msr;
350
351 /* Energy Policy is bits 3:0 */
352 msr = msr_read(IA32_ENERGY_PERFORMANCE_BIAS);
353 msr.lo &= ~0xf;
354 msr.lo |= policy & 0xf;
355 msr_write(IA32_ENERGY_PERFORMANCE_BIAS, msr);
356
357 debug("model_x06ax: energy policy set to %u\n", policy);
358 }
359
configure_mca(void)360 static void configure_mca(void)
361 {
362 msr_t msr;
363 int i;
364
365 msr.lo = 0;
366 msr.hi = 0;
367 /* This should only be done on a cold boot */
368 for (i = 0; i < 7; i++)
369 msr_write(IA32_MC0_STATUS + (i * 4), msr);
370 }
371
model_206ax_init(struct udevice * dev)372 static int model_206ax_init(struct udevice *dev)
373 {
374 int ret;
375
376 /* Clear out pending MCEs */
377 configure_mca();
378
379 /* Enable the local cpu apics */
380 enable_lapic_tpr();
381
382 /* Enable virtualization if enabled in CMOS */
383 enable_vmx();
384
385 /* Configure C States */
386 configure_c_states();
387
388 /* Configure Enhanced SpeedStep and Thermal Sensors */
389 configure_misc();
390
391 /* Thermal throttle activation offset */
392 ret = cpu_configure_thermal_target(dev);
393 if (ret) {
394 debug("Cannot set thermal target\n");
395 if (ret != -ENOENT)
396 return ret;
397 }
398
399 /* Enable Direct Cache Access */
400 configure_dca_cap();
401
402 /* Set energy policy */
403 set_energy_perf_bias(ENERGY_POLICY_NORMAL);
404
405 /* Set Max Ratio */
406 set_max_ratio();
407
408 /* Enable Turbo */
409 turbo_enable();
410
411 return 0;
412 }
413
model_206ax_get_info(const struct udevice * dev,struct cpu_info * info)414 static int model_206ax_get_info(const struct udevice *dev,
415 struct cpu_info *info)
416 {
417 return cpu_intel_get_info(info, INTEL_BCLK_MHZ);
418
419 return 0;
420 }
421
model_206ax_get_count(const struct udevice * dev)422 static int model_206ax_get_count(const struct udevice *dev)
423 {
424 return 4;
425 }
426
cpu_x86_model_206ax_probe(struct udevice * dev)427 static int cpu_x86_model_206ax_probe(struct udevice *dev)
428 {
429 if (dev_seq(dev) == 0)
430 model_206ax_init(dev);
431
432 return 0;
433 }
434
435 static const struct cpu_ops cpu_x86_model_206ax_ops = {
436 .get_desc = cpu_x86_get_desc,
437 .get_info = model_206ax_get_info,
438 .get_count = model_206ax_get_count,
439 .get_vendor = cpu_x86_get_vendor,
440 };
441
442 static const struct udevice_id cpu_x86_model_206ax_ids[] = {
443 { .compatible = "intel,core-gen3" },
444 { }
445 };
446
447 U_BOOT_DRIVER(cpu_x86_model_206ax_drv) = {
448 .name = "cpu_x86_model_206ax",
449 .id = UCLASS_CPU,
450 .of_match = cpu_x86_model_206ax_ids,
451 .bind = cpu_x86_bind,
452 .probe = cpu_x86_model_206ax_probe,
453 .ops = &cpu_x86_model_206ax_ops,
454 .flags = DM_FLAG_PRE_RELOC,
455 };
456