1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2// 3// Device Tree Include file for Layerscape-LX2160A family SoC. 4// 5// Copyright 2018-2020 NXP 6 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9 10/memreserve/ 0x80000000 0x00010000; 11 12/ { 13 compatible = "fsl,lx2160a"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 aliases { 19 rtc1 = &ftm_alarm0; 20 }; 21 22 cpus { 23 #address-cells = <1>; 24 #size-cells = <0>; 25 26 // 8 clusters having 2 Cortex-A72 cores each 27 cpu0: cpu@0 { 28 device_type = "cpu"; 29 compatible = "arm,cortex-a72"; 30 enable-method = "psci"; 31 reg = <0x0>; 32 clocks = <&clockgen 1 0>; 33 d-cache-size = <0x8000>; 34 d-cache-line-size = <64>; 35 d-cache-sets = <128>; 36 i-cache-size = <0xC000>; 37 i-cache-line-size = <64>; 38 i-cache-sets = <192>; 39 next-level-cache = <&cluster0_l2>; 40 cpu-idle-states = <&cpu_pw15>; 41 #cooling-cells = <2>; 42 }; 43 44 cpu1: cpu@1 { 45 device_type = "cpu"; 46 compatible = "arm,cortex-a72"; 47 enable-method = "psci"; 48 reg = <0x1>; 49 clocks = <&clockgen 1 0>; 50 d-cache-size = <0x8000>; 51 d-cache-line-size = <64>; 52 d-cache-sets = <128>; 53 i-cache-size = <0xC000>; 54 i-cache-line-size = <64>; 55 i-cache-sets = <192>; 56 next-level-cache = <&cluster0_l2>; 57 cpu-idle-states = <&cpu_pw15>; 58 #cooling-cells = <2>; 59 }; 60 61 cpu100: cpu@100 { 62 device_type = "cpu"; 63 compatible = "arm,cortex-a72"; 64 enable-method = "psci"; 65 reg = <0x100>; 66 clocks = <&clockgen 1 1>; 67 d-cache-size = <0x8000>; 68 d-cache-line-size = <64>; 69 d-cache-sets = <128>; 70 i-cache-size = <0xC000>; 71 i-cache-line-size = <64>; 72 i-cache-sets = <192>; 73 next-level-cache = <&cluster1_l2>; 74 cpu-idle-states = <&cpu_pw15>; 75 #cooling-cells = <2>; 76 }; 77 78 cpu101: cpu@101 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a72"; 81 enable-method = "psci"; 82 reg = <0x101>; 83 clocks = <&clockgen 1 1>; 84 d-cache-size = <0x8000>; 85 d-cache-line-size = <64>; 86 d-cache-sets = <128>; 87 i-cache-size = <0xC000>; 88 i-cache-line-size = <64>; 89 i-cache-sets = <192>; 90 next-level-cache = <&cluster1_l2>; 91 cpu-idle-states = <&cpu_pw15>; 92 #cooling-cells = <2>; 93 }; 94 95 cpu200: cpu@200 { 96 device_type = "cpu"; 97 compatible = "arm,cortex-a72"; 98 enable-method = "psci"; 99 reg = <0x200>; 100 clocks = <&clockgen 1 2>; 101 d-cache-size = <0x8000>; 102 d-cache-line-size = <64>; 103 d-cache-sets = <128>; 104 i-cache-size = <0xC000>; 105 i-cache-line-size = <64>; 106 i-cache-sets = <192>; 107 next-level-cache = <&cluster2_l2>; 108 cpu-idle-states = <&cpu_pw15>; 109 #cooling-cells = <2>; 110 }; 111 112 cpu201: cpu@201 { 113 device_type = "cpu"; 114 compatible = "arm,cortex-a72"; 115 enable-method = "psci"; 116 reg = <0x201>; 117 clocks = <&clockgen 1 2>; 118 d-cache-size = <0x8000>; 119 d-cache-line-size = <64>; 120 d-cache-sets = <128>; 121 i-cache-size = <0xC000>; 122 i-cache-line-size = <64>; 123 i-cache-sets = <192>; 124 next-level-cache = <&cluster2_l2>; 125 cpu-idle-states = <&cpu_pw15>; 126 #cooling-cells = <2>; 127 }; 128 129 cpu300: cpu@300 { 130 device_type = "cpu"; 131 compatible = "arm,cortex-a72"; 132 enable-method = "psci"; 133 reg = <0x300>; 134 clocks = <&clockgen 1 3>; 135 d-cache-size = <0x8000>; 136 d-cache-line-size = <64>; 137 d-cache-sets = <128>; 138 i-cache-size = <0xC000>; 139 i-cache-line-size = <64>; 140 i-cache-sets = <192>; 141 next-level-cache = <&cluster3_l2>; 142 cpu-idle-states = <&cpu_pw15>; 143 #cooling-cells = <2>; 144 }; 145 146 cpu301: cpu@301 { 147 device_type = "cpu"; 148 compatible = "arm,cortex-a72"; 149 enable-method = "psci"; 150 reg = <0x301>; 151 clocks = <&clockgen 1 3>; 152 d-cache-size = <0x8000>; 153 d-cache-line-size = <64>; 154 d-cache-sets = <128>; 155 i-cache-size = <0xC000>; 156 i-cache-line-size = <64>; 157 i-cache-sets = <192>; 158 next-level-cache = <&cluster3_l2>; 159 cpu-idle-states = <&cpu_pw15>; 160 #cooling-cells = <2>; 161 }; 162 163 cpu400: cpu@400 { 164 device_type = "cpu"; 165 compatible = "arm,cortex-a72"; 166 enable-method = "psci"; 167 reg = <0x400>; 168 clocks = <&clockgen 1 4>; 169 d-cache-size = <0x8000>; 170 d-cache-line-size = <64>; 171 d-cache-sets = <128>; 172 i-cache-size = <0xC000>; 173 i-cache-line-size = <64>; 174 i-cache-sets = <192>; 175 next-level-cache = <&cluster4_l2>; 176 cpu-idle-states = <&cpu_pw15>; 177 #cooling-cells = <2>; 178 }; 179 180 cpu401: cpu@401 { 181 device_type = "cpu"; 182 compatible = "arm,cortex-a72"; 183 enable-method = "psci"; 184 reg = <0x401>; 185 clocks = <&clockgen 1 4>; 186 d-cache-size = <0x8000>; 187 d-cache-line-size = <64>; 188 d-cache-sets = <128>; 189 i-cache-size = <0xC000>; 190 i-cache-line-size = <64>; 191 i-cache-sets = <192>; 192 next-level-cache = <&cluster4_l2>; 193 cpu-idle-states = <&cpu_pw15>; 194 #cooling-cells = <2>; 195 }; 196 197 cpu500: cpu@500 { 198 device_type = "cpu"; 199 compatible = "arm,cortex-a72"; 200 enable-method = "psci"; 201 reg = <0x500>; 202 clocks = <&clockgen 1 5>; 203 d-cache-size = <0x8000>; 204 d-cache-line-size = <64>; 205 d-cache-sets = <128>; 206 i-cache-size = <0xC000>; 207 i-cache-line-size = <64>; 208 i-cache-sets = <192>; 209 next-level-cache = <&cluster5_l2>; 210 cpu-idle-states = <&cpu_pw15>; 211 #cooling-cells = <2>; 212 }; 213 214 cpu501: cpu@501 { 215 device_type = "cpu"; 216 compatible = "arm,cortex-a72"; 217 enable-method = "psci"; 218 reg = <0x501>; 219 clocks = <&clockgen 1 5>; 220 d-cache-size = <0x8000>; 221 d-cache-line-size = <64>; 222 d-cache-sets = <128>; 223 i-cache-size = <0xC000>; 224 i-cache-line-size = <64>; 225 i-cache-sets = <192>; 226 next-level-cache = <&cluster5_l2>; 227 cpu-idle-states = <&cpu_pw15>; 228 #cooling-cells = <2>; 229 }; 230 231 cpu600: cpu@600 { 232 device_type = "cpu"; 233 compatible = "arm,cortex-a72"; 234 enable-method = "psci"; 235 reg = <0x600>; 236 clocks = <&clockgen 1 6>; 237 d-cache-size = <0x8000>; 238 d-cache-line-size = <64>; 239 d-cache-sets = <128>; 240 i-cache-size = <0xC000>; 241 i-cache-line-size = <64>; 242 i-cache-sets = <192>; 243 next-level-cache = <&cluster6_l2>; 244 cpu-idle-states = <&cpu_pw15>; 245 #cooling-cells = <2>; 246 }; 247 248 cpu601: cpu@601 { 249 device_type = "cpu"; 250 compatible = "arm,cortex-a72"; 251 enable-method = "psci"; 252 reg = <0x601>; 253 clocks = <&clockgen 1 6>; 254 d-cache-size = <0x8000>; 255 d-cache-line-size = <64>; 256 d-cache-sets = <128>; 257 i-cache-size = <0xC000>; 258 i-cache-line-size = <64>; 259 i-cache-sets = <192>; 260 next-level-cache = <&cluster6_l2>; 261 cpu-idle-states = <&cpu_pw15>; 262 #cooling-cells = <2>; 263 }; 264 265 cpu700: cpu@700 { 266 device_type = "cpu"; 267 compatible = "arm,cortex-a72"; 268 enable-method = "psci"; 269 reg = <0x700>; 270 clocks = <&clockgen 1 7>; 271 d-cache-size = <0x8000>; 272 d-cache-line-size = <64>; 273 d-cache-sets = <128>; 274 i-cache-size = <0xC000>; 275 i-cache-line-size = <64>; 276 i-cache-sets = <192>; 277 next-level-cache = <&cluster7_l2>; 278 cpu-idle-states = <&cpu_pw15>; 279 #cooling-cells = <2>; 280 }; 281 282 cpu701: cpu@701 { 283 device_type = "cpu"; 284 compatible = "arm,cortex-a72"; 285 enable-method = "psci"; 286 reg = <0x701>; 287 clocks = <&clockgen 1 7>; 288 d-cache-size = <0x8000>; 289 d-cache-line-size = <64>; 290 d-cache-sets = <128>; 291 i-cache-size = <0xC000>; 292 i-cache-line-size = <64>; 293 i-cache-sets = <192>; 294 next-level-cache = <&cluster7_l2>; 295 cpu-idle-states = <&cpu_pw15>; 296 #cooling-cells = <2>; 297 }; 298 299 cluster0_l2: l2-cache0 { 300 compatible = "cache"; 301 cache-size = <0x100000>; 302 cache-line-size = <64>; 303 cache-sets = <1024>; 304 cache-level = <2>; 305 }; 306 307 cluster1_l2: l2-cache1 { 308 compatible = "cache"; 309 cache-size = <0x100000>; 310 cache-line-size = <64>; 311 cache-sets = <1024>; 312 cache-level = <2>; 313 }; 314 315 cluster2_l2: l2-cache2 { 316 compatible = "cache"; 317 cache-size = <0x100000>; 318 cache-line-size = <64>; 319 cache-sets = <1024>; 320 cache-level = <2>; 321 }; 322 323 cluster3_l2: l2-cache3 { 324 compatible = "cache"; 325 cache-size = <0x100000>; 326 cache-line-size = <64>; 327 cache-sets = <1024>; 328 cache-level = <2>; 329 }; 330 331 cluster4_l2: l2-cache4 { 332 compatible = "cache"; 333 cache-size = <0x100000>; 334 cache-line-size = <64>; 335 cache-sets = <1024>; 336 cache-level = <2>; 337 }; 338 339 cluster5_l2: l2-cache5 { 340 compatible = "cache"; 341 cache-size = <0x100000>; 342 cache-line-size = <64>; 343 cache-sets = <1024>; 344 cache-level = <2>; 345 }; 346 347 cluster6_l2: l2-cache6 { 348 compatible = "cache"; 349 cache-size = <0x100000>; 350 cache-line-size = <64>; 351 cache-sets = <1024>; 352 cache-level = <2>; 353 }; 354 355 cluster7_l2: l2-cache7 { 356 compatible = "cache"; 357 cache-size = <0x100000>; 358 cache-line-size = <64>; 359 cache-sets = <1024>; 360 cache-level = <2>; 361 }; 362 363 cpu_pw15: cpu-pw15 { 364 compatible = "arm,idle-state"; 365 idle-state-name = "PW15"; 366 arm,psci-suspend-param = <0x0>; 367 entry-latency-us = <2000>; 368 exit-latency-us = <2000>; 369 min-residency-us = <6000>; 370 }; 371 }; 372 373 gic: interrupt-controller@6000000 { 374 compatible = "arm,gic-v3"; 375 reg = <0x0 0x06000000 0 0x10000>, // GIC Dist 376 <0x0 0x06200000 0 0x200000>, // GICR (RD_base + 377 // SGI_base) 378 <0x0 0x0c0c0000 0 0x2000>, // GICC 379 <0x0 0x0c0d0000 0 0x1000>, // GICH 380 <0x0 0x0c0e0000 0 0x20000>; // GICV 381 #interrupt-cells = <3>; 382 #address-cells = <2>; 383 #size-cells = <2>; 384 ranges; 385 interrupt-controller; 386 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 387 388 its: gic-its@6020000 { 389 compatible = "arm,gic-v3-its"; 390 msi-controller; 391 reg = <0x0 0x6020000 0 0x20000>; 392 }; 393 }; 394 395 timer { 396 compatible = "arm,armv8-timer"; 397 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, 398 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, 399 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, 400 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; 401 }; 402 403 pmu { 404 compatible = "arm,cortex-a72-pmu"; 405 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 406 }; 407 408 psci { 409 compatible = "arm,psci-0.2"; 410 method = "smc"; 411 }; 412 413 memory@80000000 { 414 // DRAM space - 1, size : 2 GB DRAM 415 device_type = "memory"; 416 reg = <0x00000000 0x80000000 0 0x80000000>; 417 }; 418 419 ddr1: memory-controller@1080000 { 420 compatible = "fsl,qoriq-memory-controller"; 421 reg = <0x0 0x1080000 0x0 0x1000>; 422 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 423 little-endian; 424 }; 425 426 ddr2: memory-controller@1090000 { 427 compatible = "fsl,qoriq-memory-controller"; 428 reg = <0x0 0x1090000 0x0 0x1000>; 429 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 430 little-endian; 431 }; 432 433 // One clock unit-sysclk node which bootloader require during DT fix-up 434 sysclk: sysclk { 435 compatible = "fixed-clock"; 436 #clock-cells = <0>; 437 clock-frequency = <100000000>; // fixed up by bootloader 438 clock-output-names = "sysclk"; 439 }; 440 441 thermal-zones { 442 core_thermal1: core-thermal1 { 443 polling-delay-passive = <1000>; 444 polling-delay = <5000>; 445 thermal-sensors = <&tmu 0>; 446 447 trips { 448 core_cluster_alert: core-cluster-alert { 449 temperature = <85000>; 450 hysteresis = <2000>; 451 type = "passive"; 452 }; 453 454 core_cluster_crit: core-cluster-crit { 455 temperature = <95000>; 456 hysteresis = <2000>; 457 type = "critical"; 458 }; 459 }; 460 461 }; 462 }; 463 464 soc { 465 compatible = "simple-bus"; 466 #address-cells = <2>; 467 #size-cells = <2>; 468 ranges; 469 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; 470 471 crypto: crypto@8000000 { 472 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; 473 fsl,sec-era = <10>; 474 #address-cells = <1>; 475 #size-cells = <1>; 476 ranges = <0x0 0x00 0x8000000 0x100000>; 477 reg = <0x00 0x8000000 0x0 0x100000>; 478 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 479 dma-coherent; 480 status = "disabled"; 481 482 sec_jr0: jr@10000 { 483 compatible = "fsl,sec-v5.0-job-ring", 484 "fsl,sec-v4.0-job-ring"; 485 reg = <0x10000 0x10000>; 486 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 487 status = "okay"; secure-status = "disabled"; /* NS-only */ 488 }; 489 490 sec_jr1: jr@20000 { 491 compatible = "fsl,sec-v5.0-job-ring", 492 "fsl,sec-v4.0-job-ring"; 493 reg = <0x20000 0x10000>; 494 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 495 status = "okay"; secure-status = "disabled"; /* NS-only */ 496 }; 497 498 sec_jr2: jr@30000 { 499 compatible = "fsl,sec-v5.0-job-ring", 500 "fsl,sec-v4.0-job-ring"; 501 reg = <0x30000 0x10000>; 502 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 503 status = "disabled"; secure-status = "okay"; /* S-only */ 504 }; 505 506 sec_jr3: jr@40000 { 507 compatible = "fsl,sec-v5.0-job-ring", 508 "fsl,sec-v4.0-job-ring"; 509 reg = <0x40000 0x10000>; 510 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 511 status = "okay"; secure-status = "disabled"; /* workaround for ATF */ 512 }; 513 }; 514 515 clockgen: clock-controller@1300000 { 516 compatible = "fsl,lx2160a-clockgen"; 517 reg = <0 0x1300000 0 0xa0000>; 518 #clock-cells = <2>; 519 clocks = <&sysclk>; 520 }; 521 522 dcfg: syscon@1e00000 { 523 compatible = "fsl,lx2160a-dcfg", "syscon"; 524 reg = <0x0 0x1e00000 0x0 0x10000>; 525 little-endian; 526 }; 527 528 /* WRIOP0: 0x8b8_0000, E-MDIO1: 0x1_6000 */ 529 emdio1: mdio@8b96000 { 530 compatible = "fsl,fman-memac-mdio"; 531 reg = <0x0 0x8b96000 0x0 0x1000>; 532 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 533 #address-cells = <1>; 534 #size-cells = <0>; 535 little-endian; /* force the driver in LE mode */ 536 status = "disabled"; 537 }; 538 539 /* WRIOP0: 0x8b8_0000, E-MDIO2: 0x1_7000 */ 540 emdio2: mdio@8b97000 { 541 compatible = "fsl,fman-memac-mdio"; 542 reg = <0x0 0x8b97000 0x0 0x1000>; 543 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 544 #address-cells = <1>; 545 #size-cells = <0>; 546 little-endian; /* force the driver in LE mode */ 547 status = "disabled"; 548 }; 549 550 i2c0: i2c@2000000 { 551 compatible = "fsl,vf610-i2c"; 552 #address-cells = <1>; 553 #size-cells = <0>; 554 reg = <0x0 0x2000000 0x0 0x10000>; 555 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 556 clock-names = "i2c"; 557 clocks = <&clockgen 4 15>; 558 scl-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; 559 status = "disabled"; 560 }; 561 562 i2c1: i2c@2010000 { 563 compatible = "fsl,vf610-i2c"; 564 #address-cells = <1>; 565 #size-cells = <0>; 566 reg = <0x0 0x2010000 0x0 0x10000>; 567 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 568 clock-names = "i2c"; 569 clocks = <&clockgen 4 15>; 570 status = "disabled"; 571 }; 572 573 i2c2: i2c@2020000 { 574 compatible = "fsl,vf610-i2c"; 575 #address-cells = <1>; 576 #size-cells = <0>; 577 reg = <0x0 0x2020000 0x0 0x10000>; 578 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 579 clock-names = "i2c"; 580 clocks = <&clockgen 4 15>; 581 status = "disabled"; 582 }; 583 584 i2c3: i2c@2030000 { 585 compatible = "fsl,vf610-i2c"; 586 #address-cells = <1>; 587 #size-cells = <0>; 588 reg = <0x0 0x2030000 0x0 0x10000>; 589 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 590 clock-names = "i2c"; 591 clocks = <&clockgen 4 15>; 592 status = "disabled"; 593 }; 594 595 i2c4: i2c@2040000 { 596 compatible = "fsl,vf610-i2c"; 597 #address-cells = <1>; 598 #size-cells = <0>; 599 reg = <0x0 0x2040000 0x0 0x10000>; 600 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 601 clock-names = "i2c"; 602 clocks = <&clockgen 4 15>; 603 scl-gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>; 604 status = "disabled"; 605 }; 606 607 i2c5: i2c@2050000 { 608 compatible = "fsl,vf610-i2c"; 609 #address-cells = <1>; 610 #size-cells = <0>; 611 reg = <0x0 0x2050000 0x0 0x10000>; 612 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 613 clock-names = "i2c"; 614 clocks = <&clockgen 4 15>; 615 status = "disabled"; 616 }; 617 618 i2c6: i2c@2060000 { 619 compatible = "fsl,vf610-i2c"; 620 #address-cells = <1>; 621 #size-cells = <0>; 622 reg = <0x0 0x2060000 0x0 0x10000>; 623 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 624 clock-names = "i2c"; 625 clocks = <&clockgen 4 15>; 626 status = "disabled"; 627 }; 628 629 i2c7: i2c@2070000 { 630 compatible = "fsl,vf610-i2c"; 631 #address-cells = <1>; 632 #size-cells = <0>; 633 reg = <0x0 0x2070000 0x0 0x10000>; 634 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 635 clock-names = "i2c"; 636 clocks = <&clockgen 4 15>; 637 status = "disabled"; 638 }; 639 640 fspi: spi@20c0000 { 641 compatible = "nxp,lx2160a-fspi"; 642 #address-cells = <1>; 643 #size-cells = <0>; 644 reg = <0x0 0x20c0000 0x0 0x10000>, 645 <0x0 0x20000000 0x0 0x10000000>; 646 reg-names = "fspi_base", "fspi_mmap"; 647 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 648 clocks = <&clockgen 4 3>, <&clockgen 4 3>; 649 clock-names = "fspi_en", "fspi"; 650 status = "disabled"; 651 }; 652 653 dspi0: spi@2100000 { 654 compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi"; 655 #address-cells = <1>; 656 #size-cells = <0>; 657 reg = <0x0 0x2100000 0x0 0x10000>; 658 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 659 clocks = <&clockgen 4 7>; 660 clock-names = "dspi"; 661 spi-num-chipselects = <5>; 662 bus-num = <0>; 663 status = "disabled"; 664 }; 665 666 dspi1: spi@2110000 { 667 compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi"; 668 #address-cells = <1>; 669 #size-cells = <0>; 670 reg = <0x0 0x2110000 0x0 0x10000>; 671 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 672 clocks = <&clockgen 4 7>; 673 clock-names = "dspi"; 674 spi-num-chipselects = <5>; 675 bus-num = <1>; 676 status = "disabled"; 677 }; 678 679 dspi2: spi@2120000 { 680 compatible = "fsl,lx2160a-dspi", "fsl,ls2085a-dspi"; 681 #address-cells = <1>; 682 #size-cells = <0>; 683 reg = <0x0 0x2120000 0x0 0x10000>; 684 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 685 clocks = <&clockgen 4 7>; 686 clock-names = "dspi"; 687 spi-num-chipselects = <5>; 688 bus-num = <2>; 689 status = "disabled"; 690 }; 691 692 esdhc0: esdhc@2140000 { 693 compatible = "fsl,esdhc"; 694 reg = <0x0 0x2140000 0x0 0x10000>; 695 interrupts = <0 28 0x4>; /* Level high type */ 696 clocks = <&clockgen 4 1>; 697 voltage-ranges = <1800 1800 3300 3300>; 698 sdhci,auto-cmd12; 699 little-endian; 700 bus-width = <4>; 701 status = "disabled"; 702 }; 703 704 esdhc1: esdhc@2150000 { 705 compatible = "fsl,esdhc"; 706 reg = <0x0 0x2150000 0x0 0x10000>; 707 interrupts = <0 63 0x4>; /* Level high type */ 708 clocks = <&clockgen 4 1>; 709 voltage-ranges = <1800 1800 3300 3300>; 710 sdhci,auto-cmd12; 711 broken-cd; 712 little-endian; 713 bus-width = <4>; 714 status = "disabled"; 715 }; 716 717 can0: can@2180000 { 718 compatible = "fsl,lx2160ar1-flexcan"; 719 reg = <0x0 0x2180000 0x0 0x10000>; 720 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 721 clocks = <&sysclk>, <&clockgen 4 7>; 722 clock-names = "ipg", "per"; 723 status = "disabled"; 724 }; 725 726 can1: can@2190000 { 727 compatible = "fsl,lx2160ar1-flexcan"; 728 reg = <0x0 0x2190000 0x0 0x10000>; 729 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 730 clocks = <&sysclk>, <&clockgen 4 7>; 731 clock-names = "ipg", "per"; 732 status = "disabled"; 733 }; 734 735 tmu: tmu@1f80000 { 736 compatible = "fsl,qoriq-tmu"; 737 reg = <0x0 0x1f80000 0x0 0x10000>; 738 interrupts = <0 23 0x4>; 739 fsl,tmu-range = <0x800000E6 0x8001017D>; 740 fsl,tmu-calibration = 741 /* Calibration data group 1 */ 742 <0x00000000 0x00000035 743 /* Calibration data group 2 */ 744 0x00010001 0x00000154>; 745 little-endian; 746 #thermal-sensor-cells = <1>; 747 }; 748 749 uart0: serial@21c0000 { 750 compatible = "arm,sbsa-uart","arm,pl011"; 751 reg = <0x0 0x21c0000 0x0 0x1000>; 752 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 753 current-speed = <115200>; 754 status = "disabled"; 755 }; 756 757 uart1: serial@21d0000 { 758 compatible = "arm,sbsa-uart","arm,pl011"; 759 reg = <0x0 0x21d0000 0x0 0x1000>; 760 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 761 current-speed = <115200>; 762 status = "disabled"; 763 }; 764 765 uart2: serial@21e0000 { 766 compatible = "arm,sbsa-uart","arm,pl011"; 767 reg = <0x0 0x21e0000 0x0 0x1000>; 768 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 769 current-speed = <115200>; 770 status = "disabled"; 771 }; 772 773 uart3: serial@21f0000 { 774 compatible = "arm,sbsa-uart","arm,pl011"; 775 reg = <0x0 0x21f0000 0x0 0x1000>; 776 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 777 current-speed = <115200>; 778 status = "disabled"; 779 }; 780 781 gpio0: gpio@2300000 { 782 compatible = "fsl,qoriq-gpio"; 783 reg = <0x0 0x2300000 0x0 0x10000>; 784 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 785 gpio-controller; 786 little-endian; 787 #gpio-cells = <2>; 788 interrupt-controller; 789 #interrupt-cells = <2>; 790 }; 791 792 gpio1: gpio@2310000 { 793 compatible = "fsl,qoriq-gpio"; 794 reg = <0x0 0x2310000 0x0 0x10000>; 795 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 796 gpio-controller; 797 little-endian; 798 #gpio-cells = <2>; 799 interrupt-controller; 800 #interrupt-cells = <2>; 801 }; 802 803 gpio2: gpio@2320000 { 804 compatible = "fsl,qoriq-gpio"; 805 reg = <0x0 0x2320000 0x0 0x10000>; 806 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 807 gpio-controller; 808 little-endian; 809 #gpio-cells = <2>; 810 interrupt-controller; 811 #interrupt-cells = <2>; 812 }; 813 814 gpio3: gpio@2330000 { 815 compatible = "fsl,qoriq-gpio"; 816 reg = <0x0 0x2330000 0x0 0x10000>; 817 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 818 gpio-controller; 819 little-endian; 820 #gpio-cells = <2>; 821 interrupt-controller; 822 #interrupt-cells = <2>; 823 }; 824 825 watchdog@23a0000 { 826 compatible = "arm,sbsa-gwdt"; 827 reg = <0x0 0x23a0000 0 0x1000>, 828 <0x0 0x2390000 0 0x1000>; 829 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 830 timeout-sec = <30>; 831 }; 832 833 rcpm: rcpm@1e34040 { 834 compatible = "fsl,lx2160a-rcpm", "fsl,qoriq-rcpm-2.1+"; 835 reg = <0x0 0x1e34040 0x0 0x1c>; 836 #fsl,rcpm-wakeup-cells = <7>; 837 little-endian; 838 }; 839 840 ftm_alarm0: timer@2800000 { 841 compatible = "fsl,lx2160a-ftm-alarm"; 842 reg = <0x0 0x2800000 0x0 0x10000>; 843 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>; 844 interrupts = <0 44 4>; 845 }; 846 847 usb0: usb@3100000 { 848 compatible = "fsl,lx2160a-dwc3", "snps,dwc3"; 849 reg = <0x0 0x3100000 0x0 0x10000>; 850 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 851 dr_mode = "host"; 852 snps,quirk-frame-length-adjustment = <0x20>; 853 usb3-lpm-capable; 854 snps,dis-u1u2-when-u3-quirk; 855 snps,dis_rxdet_inp3_quirk; 856 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 857 snps,host-vbus-glitches; 858 dma-coherent; 859 status = "disabled"; 860 }; 861 862 usb1: usb@3110000 { 863 compatible = "fsl,lx2160a-dwc3", "snps,dwc3"; 864 reg = <0x0 0x3110000 0x0 0x10000>; 865 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 866 dr_mode = "host"; 867 snps,quirk-frame-length-adjustment = <0x20>; 868 usb3-lpm-capable; 869 snps,dis-u1u2-when-u3-quirk; 870 snps,dis_rxdet_inp3_quirk; 871 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 872 snps,host-vbus-glitches; 873 status = "disabled"; 874 }; 875 876 sata0: sata@3200000 { 877 compatible = "fsl,lx2160a-ahci"; 878 reg = <0x0 0x3200000 0x0 0x10000>, 879 <0x7 0x100520 0x0 0x4>; 880 reg-names = "ahci", "sata-ecc"; 881 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 882 clocks = <&clockgen 4 3>; 883 dma-coherent; 884 status = "disabled"; 885 }; 886 887 sata1: sata@3210000 { 888 compatible = "fsl,lx2160a-ahci"; 889 reg = <0x0 0x3210000 0x0 0x10000>, 890 <0x7 0x100520 0x0 0x4>; 891 reg-names = "ahci", "sata-ecc"; 892 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 893 clocks = <&clockgen 4 3>; 894 dma-coherent; 895 status = "disabled"; 896 }; 897 898 sata2: sata@3220000 { 899 compatible = "fsl,lx2160a-ahci"; 900 reg = <0x0 0x3220000 0x0 0x10000>, 901 <0x7 0x100520 0x0 0x4>; 902 reg-names = "ahci", "sata-ecc"; 903 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 904 clocks = <&clockgen 4 3>; 905 dma-coherent; 906 status = "disabled"; 907 }; 908 909 sata3: sata@3230000 { 910 compatible = "fsl,lx2160a-ahci"; 911 reg = <0x0 0x3230000 0x0 0x10000>, 912 <0x7 0x100520 0x0 0x4>; 913 reg-names = "ahci", "sata-ecc"; 914 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 915 clocks = <&clockgen 4 3>; 916 dma-coherent; 917 status = "disabled"; 918 }; 919 920 pcie@3400000 { 921 compatible = "fsl,lx2160a-pcie"; 922 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ 923 0x80 0x00000000 0x0 0x00001000>; /* configuration space */ 924 reg-names = "csr_axi_slave", "config_axi_slave"; 925 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 926 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 927 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 928 interrupt-names = "aer", "pme", "intr"; 929 #address-cells = <3>; 930 #size-cells = <2>; 931 device_type = "pci"; 932 dma-coherent; 933 apio-wins = <8>; 934 ppio-wins = <8>; 935 bus-range = <0x0 0xff>; 936 ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 937 msi-parent = <&its>; 938 iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */ 939 #interrupt-cells = <1>; 940 interrupt-map-mask = <0 0 0 7>; 941 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 942 <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 943 <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 944 <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 945 status = "disabled"; 946 }; 947 948 pcie_ep@3400000 { 949 compatible = "fsl,lx2160a-pcie-ep"; 950 reg = <0x00 0x03400000 0x0 0x00100000 951 0x80 0x00000000 0x8 0x00000000>; 952 reg-names = "regs", "addr_space"; 953 num-ob-windows = <256>; 954 status = "disabled"; 955 }; 956 957 pcie@3500000 { 958 compatible = "fsl,lx2160a-pcie"; 959 reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ 960 0x88 0x00000000 0x0 0x00001000>; /* configuration space */ 961 reg-names = "csr_axi_slave", "config_axi_slave"; 962 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 963 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 964 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 965 interrupt-names = "aer", "pme", "intr"; 966 #address-cells = <3>; 967 #size-cells = <2>; 968 device_type = "pci"; 969 dma-coherent; 970 apio-wins = <8>; 971 ppio-wins = <8>; 972 bus-range = <0x0 0xff>; 973 ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 974 msi-parent = <&its>; 975 iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */ 976 #interrupt-cells = <1>; 977 interrupt-map-mask = <0 0 0 7>; 978 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 979 <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 980 <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 981 <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 982 status = "disabled"; 983 }; 984 985 pcie_ep@3500000 { 986 compatible = "fsl,lx2160a-pcie-ep"; 987 reg = <0x00 0x03500000 0x0 0x00100000 988 0x88 0x00000000 0x8 0x00000000>; 989 reg-names = "regs", "addr_space"; 990 num-ob-windows = <256>; 991 status = "disabled"; 992 }; 993 994 pcie@3600000 { 995 compatible = "fsl,lx2160a-pcie"; 996 reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ 997 0x90 0x00000000 0x0 0x00001000>; /* configuration space */ 998 reg-names = "csr_axi_slave", "config_axi_slave"; 999 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1000 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1001 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1002 interrupt-names = "aer", "pme", "intr"; 1003 #address-cells = <3>; 1004 #size-cells = <2>; 1005 device_type = "pci"; 1006 dma-coherent; 1007 apio-wins = <8>; 1008 ppio-wins = <8>; 1009 bus-range = <0x0 0xff>; 1010 ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1011 msi-parent = <&its>; 1012 iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */ 1013 #interrupt-cells = <1>; 1014 interrupt-map-mask = <0 0 0 7>; 1015 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1016 <0000 0 0 2 &gic 0 0 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1017 <0000 0 0 3 &gic 0 0 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1018 <0000 0 0 4 &gic 0 0 GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1019 status = "disabled"; 1020 }; 1021 1022 pcie_ep@3600000 { 1023 compatible = "fsl,lx2160a-pcie-ep"; 1024 reg = <0x00 0x03600000 0x0 0x00100000 1025 0x90 0x00000000 0x8 0x00000000>; 1026 reg-names = "regs", "addr_space"; 1027 num-ob-windows = <256>; 1028 max-functions = <2>; 1029 status = "disabled"; 1030 }; 1031 1032 pcie@3700000 { 1033 compatible = "fsl,lx2160a-pcie"; 1034 reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */ 1035 0x98 0x00000000 0x0 0x00001000>; /* configuration space */ 1036 reg-names = "csr_axi_slave", "config_axi_slave"; 1037 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1038 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1039 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1040 interrupt-names = "aer", "pme", "intr"; 1041 #address-cells = <3>; 1042 #size-cells = <2>; 1043 device_type = "pci"; 1044 dma-coherent; 1045 apio-wins = <8>; 1046 ppio-wins = <8>; 1047 bus-range = <0x0 0xff>; 1048 ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1049 msi-parent = <&its>; 1050 iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */ 1051 #interrupt-cells = <1>; 1052 interrupt-map-mask = <0 0 0 7>; 1053 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1054 <0000 0 0 2 &gic 0 0 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1055 <0000 0 0 3 &gic 0 0 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1056 <0000 0 0 4 &gic 0 0 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1057 status = "disabled"; 1058 }; 1059 1060 pcie_ep@3700000 { 1061 compatible = "fsl,lx2160a-pcie-ep"; 1062 reg = <0x00 0x03700000 0x0 0x00100000 1063 0x98 0x00000000 0x8 0x00000000>; 1064 reg-names = "regs", "addr_space"; 1065 num-ob-windows = <256>; 1066 status = "disabled"; 1067 }; 1068 1069 pcie@3800000 { 1070 compatible = "fsl,lx2160a-pcie"; 1071 reg = <0x00 0x03800000 0x0 0x00100000 /* controller registers */ 1072 0xa0 0x00000000 0x0 0x00001000>; /* configuration space */ 1073 reg-names = "csr_axi_slave", "config_axi_slave"; 1074 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1075 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1076 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1077 interrupt-names = "aer", "pme", "intr"; 1078 #address-cells = <3>; 1079 #size-cells = <2>; 1080 device_type = "pci"; 1081 dma-coherent; 1082 apio-wins = <8>; 1083 ppio-wins = <8>; 1084 bus-range = <0x0 0xff>; 1085 ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1086 msi-parent = <&its>; 1087 iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */ 1088 #interrupt-cells = <1>; 1089 interrupt-map-mask = <0 0 0 7>; 1090 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 1091 <0000 0 0 2 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1092 <0000 0 0 3 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1093 <0000 0 0 4 &gic 0 0 GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 1094 status = "disabled"; 1095 }; 1096 1097 pcie_ep@3800000 { 1098 compatible = "fsl,lx2160a-pcie-ep"; 1099 reg = <0x00 0x03800000 0x0 0x00100000 1100 0xa0 0x00000000 0x8 0x00000000>; 1101 reg-names = "regs", "addr_space"; 1102 num-ob-windows = <256>; 1103 max-functions = <2>; 1104 status = "disabled"; 1105 }; 1106 1107 pcie@3900000 { 1108 compatible = "fsl,lx2160a-pcie"; 1109 reg = <0x00 0x03900000 0x0 0x00100000 /* controller registers */ 1110 0xa8 0x00000000 0x0 0x00001000>; /* configuration space */ 1111 reg-names = "csr_axi_slave", "config_axi_slave"; 1112 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */ 1113 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ 1114 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 1115 interrupt-names = "aer", "pme", "intr"; 1116 #address-cells = <3>; 1117 #size-cells = <2>; 1118 device_type = "pci"; 1119 dma-coherent; 1120 apio-wins = <8>; 1121 ppio-wins = <8>; 1122 bus-range = <0x0 0xff>; 1123 ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ 1124 msi-parent = <&its>; 1125 iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */ 1126 #interrupt-cells = <1>; 1127 interrupt-map-mask = <0 0 0 7>; 1128 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1129 <0000 0 0 2 &gic 0 0 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1130 <0000 0 0 3 &gic 0 0 GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1131 <0000 0 0 4 &gic 0 0 GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1132 status = "disabled"; 1133 }; 1134 1135 pcie_ep@3900000 { 1136 compatible = "fsl,lx2160a-pcie-ep"; 1137 reg = <0x00 0x03900000 0x0 0x00100000 1138 0xa8 0x00000000 0x8 0x00000000>; 1139 reg-names = "regs", "addr_space"; 1140 num-ob-windows = <256>; 1141 status = "disabled"; 1142 }; 1143 1144 smmu: iommu@5000000 { 1145 compatible = "arm,mmu-500"; 1146 reg = <0 0x5000000 0 0x800000>; 1147 #iommu-cells = <1>; 1148 #global-interrupts = <14>; 1149 // global secure fault 1150 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 1151 // combined secure 1152 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 1153 // global non-secure fault 1154 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 1155 // combined non-secure 1156 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1157 // performance counter interrupts 0-9 1158 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 1159 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 1160 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 1161 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 1162 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, 1163 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 1164 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 1165 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 1166 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 1167 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 1168 // per context interrupt, 64 interrupts 1169 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1170 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1171 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1172 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1173 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 1174 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 1175 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 1176 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 1177 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 1178 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1179 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 1180 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 1181 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 1182 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 1183 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 1184 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 1185 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 1186 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1187 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 1188 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, 1189 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, 1190 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 1191 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 1192 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 1193 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1194 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 1195 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, 1196 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 1197 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, 1198 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 1199 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1200 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 1201 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 1202 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, 1203 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 1204 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 1205 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 1206 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 1207 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 1208 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 1209 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1210 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 1211 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 1212 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1213 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 1214 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 1215 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 1216 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 1217 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, 1218 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 1219 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 1220 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 1221 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 1222 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 1223 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 1224 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 1225 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 1226 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 1227 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 1228 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 1229 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 1230 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 1231 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 1232 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 1233 dma-coherent; 1234 }; 1235 1236 console@8340020 { 1237 compatible = "fsl,dpaa2-console"; 1238 reg = <0x00000000 0x08340020 0 0x2>; 1239 }; 1240 1241 ptp-timer@8b95000 { 1242 compatible = "fsl,dpaa2-ptp"; 1243 reg = <0x0 0x8b95000 0x0 0x100>; 1244 clocks = <&clockgen 4 1>; 1245 little-endian; 1246 fsl,extts-fifo; 1247 }; 1248 1249 fsl_mc: fsl-mc@80c000000 { 1250 compatible = "fsl,qoriq-mc"; 1251 reg = <0x00000008 0x0c000000 0 0x40>, 1252 <0x00000000 0x08340000 0 0x40000>; 1253 msi-parent = <&its>; 1254 /* iommu-map property is fixed up by u-boot */ 1255 iommu-map = <0 &smmu 0 0>; 1256 dma-coherent; 1257 #address-cells = <3>; 1258 #size-cells = <1>; 1259 1260 /* 1261 * Region type 0x0 - MC portals 1262 * Region type 0x1 - QBMAN portals 1263 */ 1264 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 1265 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; 1266 1267 /* 1268 * Define the maximum number of MACs present on the SoC. 1269 */ 1270 dpmacs { 1271 #address-cells = <1>; 1272 #size-cells = <0>; 1273 1274 dpmac1: dpmac@1 { 1275 compatible = "fsl,qoriq-mc-dpmac"; 1276 reg = <0x1>; 1277 }; 1278 1279 dpmac2: dpmac@2 { 1280 compatible = "fsl,qoriq-mc-dpmac"; 1281 reg = <0x2>; 1282 }; 1283 1284 dpmac3: dpmac@3 { 1285 compatible = "fsl,qoriq-mc-dpmac"; 1286 reg = <0x3>; 1287 }; 1288 1289 dpmac4: dpmac@4 { 1290 compatible = "fsl,qoriq-mc-dpmac"; 1291 reg = <0x4>; 1292 }; 1293 1294 dpmac5: dpmac@5 { 1295 compatible = "fsl,qoriq-mc-dpmac"; 1296 reg = <0x5>; 1297 }; 1298 1299 dpmac6: dpmac@6 { 1300 compatible = "fsl,qoriq-mc-dpmac"; 1301 reg = <0x6>; 1302 }; 1303 1304 dpmac7: dpmac@7 { 1305 compatible = "fsl,qoriq-mc-dpmac"; 1306 reg = <0x7>; 1307 }; 1308 1309 dpmac8: dpmac@8 { 1310 compatible = "fsl,qoriq-mc-dpmac"; 1311 reg = <0x8>; 1312 }; 1313 1314 dpmac9: dpmac@9 { 1315 compatible = "fsl,qoriq-mc-dpmac"; 1316 reg = <0x9>; 1317 }; 1318 1319 dpmac10: dpmac@a { 1320 compatible = "fsl,qoriq-mc-dpmac"; 1321 reg = <0xa>; 1322 }; 1323 1324 dpmac11: dpmac@b { 1325 compatible = "fsl,qoriq-mc-dpmac"; 1326 reg = <0xb>; 1327 }; 1328 1329 dpmac12: dpmac@c { 1330 compatible = "fsl,qoriq-mc-dpmac"; 1331 reg = <0xc>; 1332 }; 1333 1334 dpmac13: dpmac@d { 1335 compatible = "fsl,qoriq-mc-dpmac"; 1336 reg = <0xd>; 1337 }; 1338 1339 dpmac14: dpmac@e { 1340 compatible = "fsl,qoriq-mc-dpmac"; 1341 reg = <0xe>; 1342 }; 1343 1344 dpmac15: dpmac@f { 1345 compatible = "fsl,qoriq-mc-dpmac"; 1346 reg = <0xf>; 1347 }; 1348 1349 dpmac16: dpmac@10 { 1350 compatible = "fsl,qoriq-mc-dpmac"; 1351 reg = <0x10>; 1352 }; 1353 1354 dpmac17: dpmac@11 { 1355 compatible = "fsl,qoriq-mc-dpmac"; 1356 reg = <0x11>; 1357 }; 1358 1359 dpmac18: dpmac@12 { 1360 compatible = "fsl,qoriq-mc-dpmac"; 1361 reg = <0x12>; 1362 }; 1363 }; 1364 }; 1365 }; 1366 1367 firmware { 1368 optee { 1369 compatible = "linaro,optee-tz"; 1370 method = "smc"; 1371 }; 1372 }; 1373}; 1374