1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include <linux/slab.h>
27
28 #include "dm_services.h"
29 #include "dm_helpers.h"
30 #include "gpio_service_interface.h"
31 #include "include/ddc_service_types.h"
32 #include "include/grph_object_id.h"
33 #include "include/dpcd_defs.h"
34 #include "include/logger_interface.h"
35 #include "include/vector.h"
36 #include "core_types.h"
37 #include "dc_link_ddc.h"
38 #include "dce/dce_aux.h"
39 #include "dmub/inc/dmub_cmd.h"
40
41 #define DC_LOGGER_INIT(logger)
42
43 static const uint8_t DP_VGA_DONGLE_BRANCH_DEV_NAME[] = "DpVga";
44 /* DP to Dual link DVI converter */
45 static const uint8_t DP_DVI_CONVERTER_ID_4[] = "m2DVIa";
46 static const uint8_t DP_DVI_CONVERTER_ID_5[] = "3393N2";
47
48 #define AUX_POWER_UP_WA_DELAY 500
49 #define I2C_OVER_AUX_DEFER_WA_DELAY 70
50 #define DPVGA_DONGLE_AUX_DEFER_WA_DELAY 40
51 #define I2C_OVER_AUX_DEFER_WA_DELAY_1MS 1
52
53 /* CV smart dongle slave address for retrieving supported HDTV modes*/
54 #define CV_SMART_DONGLE_ADDRESS 0x20
55 /* DVI-HDMI dongle slave address for retrieving dongle signature*/
56 #define DVI_HDMI_DONGLE_ADDRESS 0x68
57 struct dvi_hdmi_dongle_signature_data {
58 int8_t vendor[3];/* "AMD" */
59 uint8_t version[2];
60 uint8_t size;
61 int8_t id[11];/* "6140063500G"*/
62 };
63 /* DP-HDMI dongle slave address for retrieving dongle signature*/
64 #define DP_HDMI_DONGLE_ADDRESS 0x40
65 static const uint8_t dp_hdmi_dongle_signature_str[] = "DP-HDMI ADAPTOR";
66 #define DP_HDMI_DONGLE_SIGNATURE_EOT 0x04
67
68 struct dp_hdmi_dongle_signature_data {
69 int8_t id[15];/* "DP-HDMI ADAPTOR"*/
70 uint8_t eot;/* end of transmition '\x4' */
71 };
72
73 /* SCDC Address defines (HDMI 2.0)*/
74 #define HDMI_SCDC_WRITE_UPDATE_0_ARRAY 3
75 #define HDMI_SCDC_ADDRESS 0x54
76 #define HDMI_SCDC_SINK_VERSION 0x01
77 #define HDMI_SCDC_SOURCE_VERSION 0x02
78 #define HDMI_SCDC_UPDATE_0 0x10
79 #define HDMI_SCDC_TMDS_CONFIG 0x20
80 #define HDMI_SCDC_SCRAMBLER_STATUS 0x21
81 #define HDMI_SCDC_CONFIG_0 0x30
82 #define HDMI_SCDC_STATUS_FLAGS 0x40
83 #define HDMI_SCDC_ERR_DETECT 0x50
84 #define HDMI_SCDC_TEST_CONFIG 0xC0
85
86 union hdmi_scdc_update_read_data {
87 uint8_t byte[2];
88 struct {
89 uint8_t STATUS_UPDATE:1;
90 uint8_t CED_UPDATE:1;
91 uint8_t RR_TEST:1;
92 uint8_t RESERVED:5;
93 uint8_t RESERVED2:8;
94 } fields;
95 };
96
97 union hdmi_scdc_status_flags_data {
98 uint8_t byte[2];
99 struct {
100 uint8_t CLOCK_DETECTED:1;
101 uint8_t CH0_LOCKED:1;
102 uint8_t CH1_LOCKED:1;
103 uint8_t CH2_LOCKED:1;
104 uint8_t RESERVED:4;
105 uint8_t RESERVED2:8;
106 uint8_t RESERVED3:8;
107
108 } fields;
109 };
110
111 union hdmi_scdc_ced_data {
112 uint8_t byte[7];
113 struct {
114 uint8_t CH0_8LOW:8;
115 uint8_t CH0_7HIGH:7;
116 uint8_t CH0_VALID:1;
117 uint8_t CH1_8LOW:8;
118 uint8_t CH1_7HIGH:7;
119 uint8_t CH1_VALID:1;
120 uint8_t CH2_8LOW:8;
121 uint8_t CH2_7HIGH:7;
122 uint8_t CH2_VALID:1;
123 uint8_t CHECKSUM:8;
124 uint8_t RESERVED:8;
125 uint8_t RESERVED2:8;
126 uint8_t RESERVED3:8;
127 uint8_t RESERVED4:4;
128 } fields;
129 };
130
131 struct i2c_payloads {
132 struct vector payloads;
133 };
134
135 struct aux_payloads {
136 struct vector payloads;
137 };
138
dal_ddc_i2c_payloads_create(struct dc_context * ctx,struct i2c_payloads * payloads,uint32_t count)139 static bool dal_ddc_i2c_payloads_create(
140 struct dc_context *ctx,
141 struct i2c_payloads *payloads,
142 uint32_t count)
143 {
144 if (dal_vector_construct(
145 &payloads->payloads, ctx, count, sizeof(struct i2c_payload)))
146 return true;
147
148 return false;
149 }
150
dal_ddc_i2c_payloads_get(struct i2c_payloads * p)151 static struct i2c_payload *dal_ddc_i2c_payloads_get(struct i2c_payloads *p)
152 {
153 return (struct i2c_payload *)p->payloads.container;
154 }
155
dal_ddc_i2c_payloads_get_count(struct i2c_payloads * p)156 static uint32_t dal_ddc_i2c_payloads_get_count(struct i2c_payloads *p)
157 {
158 return p->payloads.count;
159 }
160
161 #define DDC_MIN(a, b) (((a) < (b)) ? (a) : (b))
162
dal_ddc_i2c_payloads_add(struct i2c_payloads * payloads,uint32_t address,uint32_t len,uint8_t * data,bool write)163 void dal_ddc_i2c_payloads_add(
164 struct i2c_payloads *payloads,
165 uint32_t address,
166 uint32_t len,
167 uint8_t *data,
168 bool write)
169 {
170 uint32_t payload_size = EDID_SEGMENT_SIZE;
171 uint32_t pos;
172
173 for (pos = 0; pos < len; pos += payload_size) {
174 struct i2c_payload payload = {
175 .write = write,
176 .address = address,
177 .length = DDC_MIN(payload_size, len - pos),
178 .data = data + pos };
179 dal_vector_append(&payloads->payloads, &payload);
180 }
181
182 }
183
ddc_service_construct(struct ddc_service * ddc_service,struct ddc_service_init_data * init_data)184 static void ddc_service_construct(
185 struct ddc_service *ddc_service,
186 struct ddc_service_init_data *init_data)
187 {
188 enum connector_id connector_id =
189 dal_graphics_object_id_get_connector_id(init_data->id);
190
191 struct gpio_service *gpio_service = init_data->ctx->gpio_service;
192 struct graphics_object_i2c_info i2c_info;
193 struct gpio_ddc_hw_info hw_info;
194 struct dc_bios *dcb = init_data->ctx->dc_bios;
195
196 ddc_service->link = init_data->link;
197 ddc_service->ctx = init_data->ctx;
198
199 if (init_data->is_dpia_link ||
200 dcb->funcs->get_i2c_info(dcb, init_data->id, &i2c_info) != BP_RESULT_OK) {
201 ddc_service->ddc_pin = NULL;
202 } else {
203 DC_LOGGER_INIT(ddc_service->ctx->logger);
204 DC_LOG_DC("BIOS object table - i2c_line: %d", i2c_info.i2c_line);
205 DC_LOG_DC("BIOS object table - i2c_engine_id: %d", i2c_info.i2c_engine_id);
206
207 hw_info.ddc_channel = i2c_info.i2c_line;
208 if (ddc_service->link != NULL)
209 hw_info.hw_supported = i2c_info.i2c_hw_assist;
210 else
211 hw_info.hw_supported = false;
212
213 ddc_service->ddc_pin = dal_gpio_create_ddc(
214 gpio_service,
215 i2c_info.gpio_info.clk_a_register_index,
216 1 << i2c_info.gpio_info.clk_a_shift,
217 &hw_info);
218 }
219
220 ddc_service->flags.EDID_QUERY_DONE_ONCE = false;
221 ddc_service->flags.FORCE_READ_REPEATED_START = false;
222 ddc_service->flags.EDID_STRESS_READ = false;
223
224 ddc_service->flags.IS_INTERNAL_DISPLAY =
225 connector_id == CONNECTOR_ID_EDP ||
226 connector_id == CONNECTOR_ID_LVDS;
227
228 ddc_service->wa.raw = 0;
229 }
230
dal_ddc_service_create(struct ddc_service_init_data * init_data)231 struct ddc_service *dal_ddc_service_create(
232 struct ddc_service_init_data *init_data)
233 {
234 struct ddc_service *ddc_service;
235
236 ddc_service = kzalloc(sizeof(struct ddc_service), GFP_KERNEL);
237
238 if (!ddc_service)
239 return NULL;
240
241 ddc_service_construct(ddc_service, init_data);
242 return ddc_service;
243 }
244
ddc_service_destruct(struct ddc_service * ddc)245 static void ddc_service_destruct(struct ddc_service *ddc)
246 {
247 if (ddc->ddc_pin)
248 dal_gpio_destroy_ddc(&ddc->ddc_pin);
249 }
250
dal_ddc_service_destroy(struct ddc_service ** ddc)251 void dal_ddc_service_destroy(struct ddc_service **ddc)
252 {
253 if (!ddc || !*ddc) {
254 BREAK_TO_DEBUGGER();
255 return;
256 }
257 ddc_service_destruct(*ddc);
258 kfree(*ddc);
259 *ddc = NULL;
260 }
261
dal_ddc_service_get_type(struct ddc_service * ddc)262 enum ddc_service_type dal_ddc_service_get_type(struct ddc_service *ddc)
263 {
264 return DDC_SERVICE_TYPE_CONNECTOR;
265 }
266
dal_ddc_service_set_transaction_type(struct ddc_service * ddc,enum ddc_transaction_type type)267 void dal_ddc_service_set_transaction_type(
268 struct ddc_service *ddc,
269 enum ddc_transaction_type type)
270 {
271 ddc->transaction_type = type;
272 }
273
dal_ddc_service_is_in_aux_transaction_mode(struct ddc_service * ddc)274 bool dal_ddc_service_is_in_aux_transaction_mode(struct ddc_service *ddc)
275 {
276 switch (ddc->transaction_type) {
277 case DDC_TRANSACTION_TYPE_I2C_OVER_AUX:
278 case DDC_TRANSACTION_TYPE_I2C_OVER_AUX_WITH_DEFER:
279 case DDC_TRANSACTION_TYPE_I2C_OVER_AUX_RETRY_DEFER:
280 return true;
281 default:
282 break;
283 }
284 return false;
285 }
286
ddc_service_set_dongle_type(struct ddc_service * ddc,enum display_dongle_type dongle_type)287 void ddc_service_set_dongle_type(struct ddc_service *ddc,
288 enum display_dongle_type dongle_type)
289 {
290 ddc->dongle_type = dongle_type;
291 }
292
defer_delay_converter_wa(struct ddc_service * ddc,uint32_t defer_delay)293 static uint32_t defer_delay_converter_wa(
294 struct ddc_service *ddc,
295 uint32_t defer_delay)
296 {
297 struct dc_link *link = ddc->link;
298
299 if (link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_VGA_CONVERTER &&
300 link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_0080E1 &&
301 !memcmp(link->dpcd_caps.branch_dev_name,
302 DP_VGA_DONGLE_BRANCH_DEV_NAME,
303 sizeof(link->dpcd_caps.branch_dev_name)))
304
305 return defer_delay > DPVGA_DONGLE_AUX_DEFER_WA_DELAY ?
306 defer_delay : DPVGA_DONGLE_AUX_DEFER_WA_DELAY;
307
308 if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_0080E1 &&
309 !memcmp(link->dpcd_caps.branch_dev_name,
310 DP_DVI_CONVERTER_ID_4,
311 sizeof(link->dpcd_caps.branch_dev_name)))
312 return defer_delay > I2C_OVER_AUX_DEFER_WA_DELAY ?
313 defer_delay : I2C_OVER_AUX_DEFER_WA_DELAY;
314 if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_006037 &&
315 !memcmp(link->dpcd_caps.branch_dev_name,
316 DP_DVI_CONVERTER_ID_5,
317 sizeof(link->dpcd_caps.branch_dev_name)))
318 return defer_delay > I2C_OVER_AUX_DEFER_WA_DELAY_1MS ?
319 I2C_OVER_AUX_DEFER_WA_DELAY_1MS : defer_delay;
320
321 return defer_delay;
322 }
323
324 #define DP_TRANSLATOR_DELAY 5
325
get_defer_delay(struct ddc_service * ddc)326 uint32_t get_defer_delay(struct ddc_service *ddc)
327 {
328 uint32_t defer_delay = 0;
329
330 switch (ddc->transaction_type) {
331 case DDC_TRANSACTION_TYPE_I2C_OVER_AUX:
332 if ((DISPLAY_DONGLE_DP_VGA_CONVERTER == ddc->dongle_type) ||
333 (DISPLAY_DONGLE_DP_DVI_CONVERTER == ddc->dongle_type) ||
334 (DISPLAY_DONGLE_DP_HDMI_CONVERTER ==
335 ddc->dongle_type)) {
336
337 defer_delay = DP_TRANSLATOR_DELAY;
338
339 defer_delay =
340 defer_delay_converter_wa(ddc, defer_delay);
341
342 } else /*sink has a delay different from an Active Converter*/
343 defer_delay = 0;
344 break;
345 case DDC_TRANSACTION_TYPE_I2C_OVER_AUX_WITH_DEFER:
346 defer_delay = DP_TRANSLATOR_DELAY;
347 break;
348 default:
349 break;
350 }
351 return defer_delay;
352 }
353
i2c_read(struct ddc_service * ddc,uint32_t address,uint8_t * buffer,uint32_t len)354 static bool i2c_read(
355 struct ddc_service *ddc,
356 uint32_t address,
357 uint8_t *buffer,
358 uint32_t len)
359 {
360 uint8_t offs_data = 0;
361 struct i2c_payload payloads[2] = {
362 {
363 .write = true,
364 .address = address,
365 .length = 1,
366 .data = &offs_data },
367 {
368 .write = false,
369 .address = address,
370 .length = len,
371 .data = buffer } };
372
373 struct i2c_command command = {
374 .payloads = payloads,
375 .number_of_payloads = 2,
376 .engine = DDC_I2C_COMMAND_ENGINE,
377 .speed = ddc->ctx->dc->caps.i2c_speed_in_khz };
378
379 return dm_helpers_submit_i2c(
380 ddc->ctx,
381 ddc->link,
382 &command);
383 }
384
dal_ddc_service_i2c_query_dp_dual_mode_adaptor(struct ddc_service * ddc,struct display_sink_capability * sink_cap)385 void dal_ddc_service_i2c_query_dp_dual_mode_adaptor(
386 struct ddc_service *ddc,
387 struct display_sink_capability *sink_cap)
388 {
389 uint8_t i;
390 bool is_valid_hdmi_signature;
391 enum display_dongle_type *dongle = &sink_cap->dongle_type;
392 uint8_t type2_dongle_buf[DP_ADAPTOR_TYPE2_SIZE];
393 bool is_type2_dongle = false;
394 int retry_count = 2;
395 struct dp_hdmi_dongle_signature_data *dongle_signature;
396
397 /* Assume we have no valid DP passive dongle connected */
398 *dongle = DISPLAY_DONGLE_NONE;
399 sink_cap->max_hdmi_pixel_clock = DP_ADAPTOR_HDMI_SAFE_MAX_TMDS_CLK;
400
401 /* Read DP-HDMI dongle I2c (no response interpreted as DP-DVI dongle)*/
402 if (!i2c_read(
403 ddc,
404 DP_HDMI_DONGLE_ADDRESS,
405 type2_dongle_buf,
406 sizeof(type2_dongle_buf))) {
407 /* Passive HDMI dongles can sometimes fail here without retrying*/
408 while (retry_count > 0) {
409 if (i2c_read(ddc,
410 DP_HDMI_DONGLE_ADDRESS,
411 type2_dongle_buf,
412 sizeof(type2_dongle_buf)))
413 break;
414 retry_count--;
415 }
416 if (retry_count == 0) {
417 *dongle = DISPLAY_DONGLE_DP_DVI_DONGLE;
418 sink_cap->max_hdmi_pixel_clock = DP_ADAPTOR_DVI_MAX_TMDS_CLK;
419
420 CONN_DATA_DETECT(ddc->link, type2_dongle_buf, sizeof(type2_dongle_buf),
421 "DP-DVI passive dongle %dMhz: ",
422 DP_ADAPTOR_DVI_MAX_TMDS_CLK / 1000);
423 return;
424 }
425 }
426
427 /* Check if Type 2 dongle.*/
428 if (type2_dongle_buf[DP_ADAPTOR_TYPE2_REG_ID] == DP_ADAPTOR_TYPE2_ID)
429 is_type2_dongle = true;
430
431 dongle_signature =
432 (struct dp_hdmi_dongle_signature_data *)type2_dongle_buf;
433
434 is_valid_hdmi_signature = true;
435
436 /* Check EOT */
437 if (dongle_signature->eot != DP_HDMI_DONGLE_SIGNATURE_EOT) {
438 is_valid_hdmi_signature = false;
439 }
440
441 /* Check signature */
442 for (i = 0; i < sizeof(dongle_signature->id); ++i) {
443 /* If its not the right signature,
444 * skip mismatch in subversion byte.*/
445 if (dongle_signature->id[i] !=
446 dp_hdmi_dongle_signature_str[i] && i != 3) {
447
448 if (is_type2_dongle) {
449 is_valid_hdmi_signature = false;
450 break;
451 }
452
453 }
454 }
455
456 if (is_type2_dongle) {
457 uint32_t max_tmds_clk =
458 type2_dongle_buf[DP_ADAPTOR_TYPE2_REG_MAX_TMDS_CLK];
459
460 max_tmds_clk = max_tmds_clk * 2 + max_tmds_clk / 2;
461
462 if (0 == max_tmds_clk ||
463 max_tmds_clk < DP_ADAPTOR_TYPE2_MIN_TMDS_CLK ||
464 max_tmds_clk > DP_ADAPTOR_TYPE2_MAX_TMDS_CLK) {
465 *dongle = DISPLAY_DONGLE_DP_DVI_DONGLE;
466
467 CONN_DATA_DETECT(ddc->link, type2_dongle_buf,
468 sizeof(type2_dongle_buf),
469 "DP-DVI passive dongle %dMhz: ",
470 DP_ADAPTOR_DVI_MAX_TMDS_CLK / 1000);
471 } else {
472 if (is_valid_hdmi_signature == true) {
473 *dongle = DISPLAY_DONGLE_DP_HDMI_DONGLE;
474
475 CONN_DATA_DETECT(ddc->link, type2_dongle_buf,
476 sizeof(type2_dongle_buf),
477 "Type 2 DP-HDMI passive dongle %dMhz: ",
478 max_tmds_clk);
479 } else {
480 *dongle = DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE;
481
482 CONN_DATA_DETECT(ddc->link, type2_dongle_buf,
483 sizeof(type2_dongle_buf),
484 "Type 2 DP-HDMI passive dongle (no signature) %dMhz: ",
485 max_tmds_clk);
486
487 }
488
489 /* Multiply by 1000 to convert to kHz. */
490 sink_cap->max_hdmi_pixel_clock =
491 max_tmds_clk * 1000;
492 }
493
494 } else {
495 if (is_valid_hdmi_signature == true) {
496 *dongle = DISPLAY_DONGLE_DP_HDMI_DONGLE;
497
498 CONN_DATA_DETECT(ddc->link, type2_dongle_buf,
499 sizeof(type2_dongle_buf),
500 "Type 1 DP-HDMI passive dongle %dMhz: ",
501 sink_cap->max_hdmi_pixel_clock / 1000);
502 } else {
503 *dongle = DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE;
504
505 CONN_DATA_DETECT(ddc->link, type2_dongle_buf,
506 sizeof(type2_dongle_buf),
507 "Type 1 DP-HDMI passive dongle (no signature) %dMhz: ",
508 sink_cap->max_hdmi_pixel_clock / 1000);
509 }
510 }
511
512 return;
513 }
514
515 enum {
516 DP_SINK_CAP_SIZE =
517 DP_EDP_CONFIGURATION_CAP - DP_DPCD_REV + 1
518 };
519
dal_ddc_service_query_ddc_data(struct ddc_service * ddc,uint32_t address,uint8_t * write_buf,uint32_t write_size,uint8_t * read_buf,uint32_t read_size)520 bool dal_ddc_service_query_ddc_data(
521 struct ddc_service *ddc,
522 uint32_t address,
523 uint8_t *write_buf,
524 uint32_t write_size,
525 uint8_t *read_buf,
526 uint32_t read_size)
527 {
528 bool success = true;
529 uint32_t payload_size =
530 dal_ddc_service_is_in_aux_transaction_mode(ddc) ?
531 DEFAULT_AUX_MAX_DATA_SIZE : EDID_SEGMENT_SIZE;
532
533 uint32_t write_payloads =
534 (write_size + payload_size - 1) / payload_size;
535
536 uint32_t read_payloads =
537 (read_size + payload_size - 1) / payload_size;
538
539 uint32_t payloads_num = write_payloads + read_payloads;
540
541
542 if (write_size > EDID_SEGMENT_SIZE || read_size > EDID_SEGMENT_SIZE)
543 return false;
544
545 if (!payloads_num)
546 return false;
547
548 /*TODO: len of payload data for i2c and aux is uint8!!!!,
549 * but we want to read 256 over i2c!!!!*/
550 if (dal_ddc_service_is_in_aux_transaction_mode(ddc)) {
551 struct aux_payload payload;
552
553 payload.i2c_over_aux = true;
554 payload.address = address;
555 payload.reply = NULL;
556 payload.defer_delay = get_defer_delay(ddc);
557 payload.write_status_update = false;
558
559 if (write_size != 0) {
560 payload.write = true;
561 /* should not set mot (middle of transaction) to 0
562 * if there are pending read payloads
563 */
564 payload.mot = !(read_size == 0);
565 payload.length = write_size;
566 payload.data = write_buf;
567
568 success = dal_ddc_submit_aux_command(ddc, &payload);
569 }
570
571 if (read_size != 0 && success) {
572 payload.write = false;
573 /* should set mot (middle of transaction) to 0
574 * since it is the last payload to send
575 */
576 payload.mot = false;
577 payload.length = read_size;
578 payload.data = read_buf;
579
580 success = dal_ddc_submit_aux_command(ddc, &payload);
581 }
582 } else {
583 struct i2c_command command = {0};
584 struct i2c_payloads payloads;
585
586 if (!dal_ddc_i2c_payloads_create(ddc->ctx, &payloads, payloads_num))
587 return false;
588
589 command.payloads = dal_ddc_i2c_payloads_get(&payloads);
590 command.number_of_payloads = 0;
591 command.engine = DDC_I2C_COMMAND_ENGINE;
592 command.speed = ddc->ctx->dc->caps.i2c_speed_in_khz;
593
594 dal_ddc_i2c_payloads_add(
595 &payloads, address, write_size, write_buf, true);
596
597 dal_ddc_i2c_payloads_add(
598 &payloads, address, read_size, read_buf, false);
599
600 command.number_of_payloads =
601 dal_ddc_i2c_payloads_get_count(&payloads);
602
603 success = dm_helpers_submit_i2c(
604 ddc->ctx,
605 ddc->link,
606 &command);
607
608 dal_vector_destruct(&payloads.payloads);
609 }
610
611 return success;
612 }
613
dal_ddc_submit_aux_command(struct ddc_service * ddc,struct aux_payload * payload)614 bool dal_ddc_submit_aux_command(struct ddc_service *ddc,
615 struct aux_payload *payload)
616 {
617 uint32_t retrieved = 0;
618 bool ret = false;
619
620 if (!ddc)
621 return false;
622
623 if (!payload)
624 return false;
625
626 do {
627 struct aux_payload current_payload;
628 bool is_end_of_payload = (retrieved + DEFAULT_AUX_MAX_DATA_SIZE) >=
629 payload->length ? true : false;
630 uint32_t payload_length = is_end_of_payload ?
631 payload->length - retrieved : DEFAULT_AUX_MAX_DATA_SIZE;
632
633 current_payload.address = payload->address;
634 current_payload.data = &payload->data[retrieved];
635 current_payload.defer_delay = payload->defer_delay;
636 current_payload.i2c_over_aux = payload->i2c_over_aux;
637 current_payload.length = payload_length;
638 /* set mot (middle of transaction) to false if it is the last payload */
639 current_payload.mot = is_end_of_payload ? payload->mot:true;
640 current_payload.write_status_update = false;
641 current_payload.reply = payload->reply;
642 current_payload.write = payload->write;
643
644 ret = dc_link_aux_transfer_with_retries(ddc, ¤t_payload);
645
646 retrieved += payload_length;
647 } while (retrieved < payload->length && ret == true);
648
649 return ret;
650 }
651
652 /* dc_link_aux_transfer_raw() - Attempt to transfer
653 * the given aux payload. This function does not perform
654 * retries or handle error states. The reply is returned
655 * in the payload->reply and the result through
656 * *operation_result. Returns the number of bytes transferred,
657 * or -1 on a failure.
658 */
dc_link_aux_transfer_raw(struct ddc_service * ddc,struct aux_payload * payload,enum aux_return_code_type * operation_result)659 int dc_link_aux_transfer_raw(struct ddc_service *ddc,
660 struct aux_payload *payload,
661 enum aux_return_code_type *operation_result)
662 {
663 if (ddc->ctx->dc->debug.enable_dmub_aux_for_legacy_ddc ||
664 !ddc->ddc_pin) {
665 return dce_aux_transfer_dmub_raw(ddc, payload, operation_result);
666 } else {
667 return dce_aux_transfer_raw(ddc, payload, operation_result);
668 }
669 }
670
671 /* dc_link_aux_transfer_with_retries() - Attempt to submit an
672 * aux payload, retrying on timeouts, defers, and busy states
673 * as outlined in the DP spec. Returns true if the request
674 * was successful.
675 *
676 * Unless you want to implement your own retry semantics, this
677 * is probably the one you want.
678 */
dc_link_aux_transfer_with_retries(struct ddc_service * ddc,struct aux_payload * payload)679 bool dc_link_aux_transfer_with_retries(struct ddc_service *ddc,
680 struct aux_payload *payload)
681 {
682 return dce_aux_transfer_with_retries(ddc, payload);
683 }
684
685
dc_link_aux_try_to_configure_timeout(struct ddc_service * ddc,uint32_t timeout)686 bool dc_link_aux_try_to_configure_timeout(struct ddc_service *ddc,
687 uint32_t timeout)
688 {
689 bool result = false;
690 struct ddc *ddc_pin = ddc->ddc_pin;
691
692 /* Do not try to access nonexistent DDC pin. */
693 if (ddc->link->ep_type != DISPLAY_ENDPOINT_PHY)
694 return true;
695
696 if (ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]->funcs->configure_timeout) {
697 ddc->ctx->dc->res_pool->engines[ddc_pin->pin_data->en]->funcs->configure_timeout(ddc, timeout);
698 result = true;
699 }
700 return result;
701 }
702
703 /*test only function*/
dal_ddc_service_set_ddc_pin(struct ddc_service * ddc_service,struct ddc * ddc)704 void dal_ddc_service_set_ddc_pin(
705 struct ddc_service *ddc_service,
706 struct ddc *ddc)
707 {
708 ddc_service->ddc_pin = ddc;
709 }
710
dal_ddc_service_get_ddc_pin(struct ddc_service * ddc_service)711 struct ddc *dal_ddc_service_get_ddc_pin(struct ddc_service *ddc_service)
712 {
713 return ddc_service->ddc_pin;
714 }
715
dal_ddc_service_write_scdc_data(struct ddc_service * ddc_service,uint32_t pix_clk,bool lte_340_scramble)716 void dal_ddc_service_write_scdc_data(struct ddc_service *ddc_service,
717 uint32_t pix_clk,
718 bool lte_340_scramble)
719 {
720 bool over_340_mhz = pix_clk > 340000 ? 1 : 0;
721 uint8_t slave_address = HDMI_SCDC_ADDRESS;
722 uint8_t offset = HDMI_SCDC_SINK_VERSION;
723 uint8_t sink_version = 0;
724 uint8_t write_buffer[2] = {0};
725 /*Lower than 340 Scramble bit from SCDC caps*/
726
727 if (ddc_service->link->local_sink &&
728 ddc_service->link->local_sink->edid_caps.panel_patch.skip_scdc_overwrite)
729 return;
730
731 dal_ddc_service_query_ddc_data(ddc_service, slave_address, &offset,
732 sizeof(offset), &sink_version, sizeof(sink_version));
733 if (sink_version == 1) {
734 /*Source Version = 1*/
735 write_buffer[0] = HDMI_SCDC_SOURCE_VERSION;
736 write_buffer[1] = 1;
737 dal_ddc_service_query_ddc_data(ddc_service, slave_address,
738 write_buffer, sizeof(write_buffer), NULL, 0);
739 /*Read Request from SCDC caps*/
740 }
741 write_buffer[0] = HDMI_SCDC_TMDS_CONFIG;
742
743 if (over_340_mhz) {
744 write_buffer[1] = 3;
745 } else if (lte_340_scramble) {
746 write_buffer[1] = 1;
747 } else {
748 write_buffer[1] = 0;
749 }
750 dal_ddc_service_query_ddc_data(ddc_service, slave_address, write_buffer,
751 sizeof(write_buffer), NULL, 0);
752 }
753
dal_ddc_service_read_scdc_data(struct ddc_service * ddc_service)754 void dal_ddc_service_read_scdc_data(struct ddc_service *ddc_service)
755 {
756 uint8_t slave_address = HDMI_SCDC_ADDRESS;
757 uint8_t offset = HDMI_SCDC_TMDS_CONFIG;
758 uint8_t tmds_config = 0;
759
760 if (ddc_service->link->local_sink &&
761 ddc_service->link->local_sink->edid_caps.panel_patch.skip_scdc_overwrite)
762 return;
763
764 dal_ddc_service_query_ddc_data(ddc_service, slave_address, &offset,
765 sizeof(offset), &tmds_config, sizeof(tmds_config));
766 if (tmds_config & 0x1) {
767 union hdmi_scdc_status_flags_data status_data = {0};
768 uint8_t scramble_status = 0;
769
770 offset = HDMI_SCDC_SCRAMBLER_STATUS;
771 dal_ddc_service_query_ddc_data(ddc_service, slave_address,
772 &offset, sizeof(offset), &scramble_status,
773 sizeof(scramble_status));
774 offset = HDMI_SCDC_STATUS_FLAGS;
775 dal_ddc_service_query_ddc_data(ddc_service, slave_address,
776 &offset, sizeof(offset), status_data.byte,
777 sizeof(status_data.byte));
778 }
779 }
780
781