1 /*
2 * Copyright 2019-2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25 #include "resource.h"
26 #include "clk_mgr.h"
27 #include "dcn20/dcn20_resource.h"
28 #include "dcn301/dcn301_resource.h"
29
30 #include "dml/dcn20/dcn20_fpu.h"
31 #include "dcn301_fpu.h"
32
33 #define TO_DCN301_RES_POOL(pool)\
34 container_of(pool, struct dcn301_resource_pool, base)
35
36 /* Based on: //vidip/dc/dcn3/doc/architecture/DCN3x_Display_Mode.xlsm#83 */
37 struct _vcs_dpi_ip_params_st dcn3_01_ip = {
38 .odm_capable = 1,
39 .gpuvm_enable = 1,
40 .hostvm_enable = 1,
41 .gpuvm_max_page_table_levels = 1,
42 .hostvm_max_page_table_levels = 2,
43 .hostvm_cached_page_table_levels = 0,
44 .pte_group_size_bytes = 2048,
45 .num_dsc = 3,
46 .rob_buffer_size_kbytes = 184,
47 .det_buffer_size_kbytes = 184,
48 .dpte_buffer_size_in_pte_reqs_luma = 64,
49 .dpte_buffer_size_in_pte_reqs_chroma = 32,
50 .pde_proc_buffer_size_64k_reqs = 48,
51 .dpp_output_buffer_pixels = 2560,
52 .opp_output_buffer_lines = 1,
53 .pixel_chunk_size_kbytes = 8,
54 .meta_chunk_size_kbytes = 2,
55 .writeback_chunk_size_kbytes = 8,
56 .line_buffer_size_bits = 789504,
57 .is_line_buffer_bpp_fixed = 0, // ?
58 .line_buffer_fixed_bpp = 48, // ?
59 .dcc_supported = true,
60 .writeback_interface_buffer_size_kbytes = 90,
61 .writeback_line_buffer_buffer_size = 656640,
62 .max_line_buffer_lines = 12,
63 .writeback_luma_buffer_size_kbytes = 12, // writeback_line_buffer_buffer_size = 656640
64 .writeback_chroma_buffer_size_kbytes = 8,
65 .writeback_chroma_line_buffer_width_pixels = 4,
66 .writeback_max_hscl_ratio = 1,
67 .writeback_max_vscl_ratio = 1,
68 .writeback_min_hscl_ratio = 1,
69 .writeback_min_vscl_ratio = 1,
70 .writeback_max_hscl_taps = 1,
71 .writeback_max_vscl_taps = 1,
72 .writeback_line_buffer_luma_buffer_size = 0,
73 .writeback_line_buffer_chroma_buffer_size = 14643,
74 .cursor_buffer_size = 8,
75 .cursor_chunk_size = 2,
76 .max_num_otg = 4,
77 .max_num_dpp = 4,
78 .max_num_wb = 1,
79 .max_dchub_pscl_bw_pix_per_clk = 4,
80 .max_pscl_lb_bw_pix_per_clk = 2,
81 .max_lb_vscl_bw_pix_per_clk = 4,
82 .max_vscl_hscl_bw_pix_per_clk = 4,
83 .max_hscl_ratio = 6,
84 .max_vscl_ratio = 6,
85 .hscl_mults = 4,
86 .vscl_mults = 4,
87 .max_hscl_taps = 8,
88 .max_vscl_taps = 8,
89 .dispclk_ramp_margin_percent = 1,
90 .underscan_factor = 1.11,
91 .min_vblank_lines = 32,
92 .dppclk_delay_subtotal = 46,
93 .dynamic_metadata_vm_enabled = true,
94 .dppclk_delay_scl_lb_only = 16,
95 .dppclk_delay_scl = 50,
96 .dppclk_delay_cnvc_formatter = 27,
97 .dppclk_delay_cnvc_cursor = 6,
98 .dispclk_delay_subtotal = 119,
99 .dcfclk_cstate_latency = 5.2, // SRExitTime
100 .max_inter_dcn_tile_repeaters = 8,
101 .max_num_hdmi_frl_outputs = 0,
102 .odm_combine_4to1_supported = true,
103
104 .xfc_supported = false,
105 .xfc_fill_bw_overhead_percent = 10.0,
106 .xfc_fill_constant_bytes = 0,
107 .gfx7_compat_tiling_supported = 0,
108 .number_of_cursors = 1,
109 };
110
111 struct _vcs_dpi_soc_bounding_box_st dcn3_01_soc = {
112 .clock_limits = {
113 {
114 .state = 0,
115 .dram_speed_mts = 2400.0,
116 .fabricclk_mhz = 600,
117 .socclk_mhz = 278.0,
118 .dcfclk_mhz = 400.0,
119 .dscclk_mhz = 206.0,
120 .dppclk_mhz = 1015.0,
121 .dispclk_mhz = 1015.0,
122 .phyclk_mhz = 600.0,
123 },
124
125 {
126 .state = 1,
127 .dram_speed_mts = 2400.0,
128 .fabricclk_mhz = 688,
129 .socclk_mhz = 278.0,
130 .dcfclk_mhz = 400.0,
131 .dscclk_mhz = 206.0,
132 .dppclk_mhz = 1015.0,
133 .dispclk_mhz = 1015.0,
134 .phyclk_mhz = 600.0,
135 },
136
137 {
138 .state = 2,
139 .dram_speed_mts = 4267.0,
140 .fabricclk_mhz = 1067,
141 .socclk_mhz = 278.0,
142 .dcfclk_mhz = 608.0,
143 .dscclk_mhz = 296.0,
144 .dppclk_mhz = 1015.0,
145 .dispclk_mhz = 1015.0,
146 .phyclk_mhz = 810.0,
147 },
148
149 {
150 .state = 3,
151 .dram_speed_mts = 4267.0,
152 .fabricclk_mhz = 1067,
153 .socclk_mhz = 715.0,
154 .dcfclk_mhz = 676.0,
155 .dscclk_mhz = 338.0,
156 .dppclk_mhz = 1015.0,
157 .dispclk_mhz = 1015.0,
158 .phyclk_mhz = 810.0,
159 },
160
161 {
162 .state = 4,
163 .dram_speed_mts = 4267.0,
164 .fabricclk_mhz = 1067,
165 .socclk_mhz = 953.0,
166 .dcfclk_mhz = 810.0,
167 .dscclk_mhz = 338.0,
168 .dppclk_mhz = 1015.0,
169 .dispclk_mhz = 1015.0,
170 .phyclk_mhz = 810.0,
171 },
172 },
173
174 .sr_exit_time_us = 9.0,
175 .sr_enter_plus_exit_time_us = 11.0,
176 .urgent_latency_us = 4.0,
177 .urgent_latency_pixel_data_only_us = 4.0,
178 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
179 .urgent_latency_vm_data_only_us = 4.0,
180 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
181 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
182 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
183 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0,
184 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 75.0,
185 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
186 .max_avg_sdp_bw_use_normal_percent = 60.0,
187 .max_avg_dram_bw_use_normal_percent = 60.0,
188 .writeback_latency_us = 12.0,
189 .max_request_size_bytes = 256,
190 .dram_channel_width_bytes = 4,
191 .fabric_datapath_to_dcn_data_return_bytes = 32,
192 .dcn_downspread_percent = 0.5,
193 .downspread_percent = 0.38,
194 .dram_page_open_time_ns = 50.0,
195 .dram_rw_turnaround_time_ns = 17.5,
196 .dram_return_buffer_per_channel_bytes = 8192,
197 .round_trip_ping_latency_dcfclk_cycles = 191,
198 .urgent_out_of_order_return_per_channel_bytes = 4096,
199 .channel_interleave_bytes = 256,
200 .num_banks = 8,
201 .num_chans = 4,
202 .gpuvm_min_page_size_bytes = 4096,
203 .hostvm_min_page_size_bytes = 4096,
204 .dram_clock_change_latency_us = 23.84,
205 .writeback_dram_clock_change_latency_us = 23.0,
206 .return_bus_width_bytes = 64,
207 .dispclk_dppclk_vco_speed_mhz = 3550,
208 .xfc_bus_transport_time_us = 20, // ?
209 .xfc_xbuf_latency_tolerance_us = 4, // ?
210 .use_urgent_burst_bw = 1, // ?
211 .num_states = 5,
212 .do_urgent_latency_adjustment = false,
213 .urgent_latency_adjustment_fabric_clock_component_us = 0,
214 .urgent_latency_adjustment_fabric_clock_reference_mhz = 0,
215 };
216
calculate_wm_set_for_vlevel(int vlevel,struct wm_range_table_entry * table_entry,struct dcn_watermarks * wm_set,struct display_mode_lib * dml,display_e2e_pipe_params_st * pipes,int pipe_cnt)217 static void calculate_wm_set_for_vlevel(int vlevel,
218 struct wm_range_table_entry *table_entry,
219 struct dcn_watermarks *wm_set,
220 struct display_mode_lib *dml,
221 display_e2e_pipe_params_st *pipes,
222 int pipe_cnt)
223 {
224 double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us;
225
226 ASSERT(vlevel < dml->soc.num_states);
227 /* only pipe 0 is read for voltage and dcf/soc clocks */
228 pipes[0].clks_cfg.voltage = vlevel;
229 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz;
230 pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz;
231
232 dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us;
233 dml->soc.sr_exit_time_us = table_entry->sr_exit_time_us;
234 dml->soc.sr_enter_plus_exit_time_us = table_entry->sr_enter_plus_exit_time_us;
235
236 wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000;
237 wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000;
238 wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000;
239 wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000;
240 wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000;
241 wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000;
242 wm_set->frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000;
243 wm_set->urgent_latency_ns = get_urgent_latency(dml, pipes, pipe_cnt) * 1000;
244 dml->soc.dram_clock_change_latency_us = dram_clock_change_latency_cached;
245
246 }
247
dcn301_update_bw_bounding_box(struct dc * dc,struct clk_bw_params * bw_params)248 void dcn301_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
249 {
250 struct dcn301_resource_pool *pool = TO_DCN301_RES_POOL(dc->res_pool);
251 struct clk_limit_table *clk_table = &bw_params->clk_table;
252 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
253 unsigned int i, closest_clk_lvl;
254 int j;
255
256 dc_assert_fp_enabled();
257
258 /* Default clock levels are used for diags, which may lead to overclocking. */
259 if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
260 dcn3_01_ip.max_num_otg = pool->base.res_cap->num_timing_generator;
261 dcn3_01_ip.max_num_dpp = pool->base.pipe_count;
262 dcn3_01_soc.num_chans = bw_params->num_channels;
263
264 ASSERT(clk_table->num_entries);
265 for (i = 0; i < clk_table->num_entries; i++) {
266 /* loop backwards*/
267 for (closest_clk_lvl = 0, j = dcn3_01_soc.num_states - 1; j >= 0; j--) {
268 if ((unsigned int) dcn3_01_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) {
269 closest_clk_lvl = j;
270 break;
271 }
272 }
273
274 clock_limits[i].state = i;
275 clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
276 clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
277 clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
278 clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2;
279
280 clock_limits[i].dispclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
281 clock_limits[i].dppclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
282 clock_limits[i].dram_bw_per_chan_gbps = dcn3_01_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
283 clock_limits[i].dscclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
284 clock_limits[i].dtbclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
285 clock_limits[i].phyclk_d18_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
286 clock_limits[i].phyclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
287 }
288
289 for (i = 0; i < clk_table->num_entries; i++)
290 dcn3_01_soc.clock_limits[i] = clock_limits[i];
291
292 if (clk_table->num_entries) {
293 dcn3_01_soc.num_states = clk_table->num_entries;
294 /* duplicate last level */
295 dcn3_01_soc.clock_limits[dcn3_01_soc.num_states] = dcn3_01_soc.clock_limits[dcn3_01_soc.num_states - 1];
296 dcn3_01_soc.clock_limits[dcn3_01_soc.num_states].state = dcn3_01_soc.num_states;
297 }
298 }
299
300 dcn3_01_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
301 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
302
303 dml_init_instance(&dc->dml, &dcn3_01_soc, &dcn3_01_ip, DML_PROJECT_DCN30);
304 }
305
dcn301_fpu_set_wm_ranges(int i,struct pp_smu_wm_range_sets * ranges,struct _vcs_dpi_soc_bounding_box_st * loaded_bb)306 void dcn301_fpu_set_wm_ranges(int i,
307 struct pp_smu_wm_range_sets *ranges,
308 struct _vcs_dpi_soc_bounding_box_st *loaded_bb)
309 {
310 dc_assert_fp_enabled();
311
312 ranges->reader_wm_sets[i].min_fill_clk_mhz = (i > 0) ? (loaded_bb->clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0;
313 ranges->reader_wm_sets[i].max_fill_clk_mhz = loaded_bb->clock_limits[i].dram_speed_mts / 16;
314 }
315
dcn301_fpu_init_soc_bounding_box(struct bp_soc_bb_info bb_info)316 void dcn301_fpu_init_soc_bounding_box(struct bp_soc_bb_info bb_info)
317 {
318 dc_assert_fp_enabled();
319
320 if (bb_info.dram_clock_change_latency_100ns > 0)
321 dcn3_01_soc.dram_clock_change_latency_us = bb_info.dram_clock_change_latency_100ns * 10;
322
323 if (bb_info.dram_sr_enter_exit_latency_100ns > 0)
324 dcn3_01_soc.sr_enter_plus_exit_time_us = bb_info.dram_sr_enter_exit_latency_100ns * 10;
325
326 if (bb_info.dram_sr_exit_latency_100ns > 0)
327 dcn3_01_soc.sr_exit_time_us = bb_info.dram_sr_exit_latency_100ns * 10;
328 }
329
dcn301_calculate_wm_and_dlg(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,int pipe_cnt,int vlevel_req)330 void dcn301_calculate_wm_and_dlg(struct dc *dc,
331 struct dc_state *context,
332 display_e2e_pipe_params_st *pipes,
333 int pipe_cnt,
334 int vlevel_req)
335 {
336 int i, pipe_idx;
337 int vlevel, vlevel_max;
338 struct wm_range_table_entry *table_entry;
339 struct clk_bw_params *bw_params = dc->clk_mgr->bw_params;
340
341 ASSERT(bw_params);
342 dc_assert_fp_enabled();
343
344 vlevel_max = bw_params->clk_table.num_entries - 1;
345
346 /* WM Set D */
347 table_entry = &bw_params->wm_table.entries[WM_D];
348 if (table_entry->wm_type == WM_TYPE_RETRAINING)
349 vlevel = 0;
350 else
351 vlevel = vlevel_max;
352 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d,
353 &context->bw_ctx.dml, pipes, pipe_cnt);
354 /* WM Set C */
355 table_entry = &bw_params->wm_table.entries[WM_C];
356 vlevel = min(max(vlevel_req, 2), vlevel_max);
357 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.c,
358 &context->bw_ctx.dml, pipes, pipe_cnt);
359 /* WM Set B */
360 table_entry = &bw_params->wm_table.entries[WM_B];
361 vlevel = min(max(vlevel_req, 1), vlevel_max);
362 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.b,
363 &context->bw_ctx.dml, pipes, pipe_cnt);
364
365 /* WM Set A */
366 table_entry = &bw_params->wm_table.entries[WM_A];
367 vlevel = min(vlevel_req, vlevel_max);
368 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.a,
369 &context->bw_ctx.dml, pipes, pipe_cnt);
370
371 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
372 if (!context->res_ctx.pipe_ctx[i].stream)
373 continue;
374
375 pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt);
376 pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
377
378 if (dc->config.forced_clocks) {
379 pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
380 pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
381 }
382 if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000)
383 pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;
384 if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
385 pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;
386 pipe_idx++;
387 }
388
389 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
390 }
391