1 /*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dccg.h"
27 #include "clk_mgr_internal.h"
28
29 #include "dcn30_clk_mgr_smu_msg.h"
30 #include "dcn20/dcn20_clk_mgr.h"
31 #include "dce100/dce_clk_mgr.h"
32 #include "reg_helper.h"
33 #include "core_types.h"
34 #include "dm_helpers.h"
35
36 #include "atomfirmware.h"
37
38
39 #include "sienna_cichlid_ip_offset.h"
40 #include "dcn/dcn_3_0_0_offset.h"
41 #include "dcn/dcn_3_0_0_sh_mask.h"
42
43 #include "nbio/nbio_7_4_offset.h"
44
45 #include "dcn/dpcs_3_0_0_offset.h"
46 #include "dcn/dpcs_3_0_0_sh_mask.h"
47
48 #include "mmhub/mmhub_2_0_0_offset.h"
49 #include "mmhub/mmhub_2_0_0_sh_mask.h"
50 /*we don't have clk folder yet*/
51 #include "dcn30/dcn30_clk_mgr.h"
52
53 #undef FN
54 #define FN(reg_name, field_name) \
55 clk_mgr->clk_mgr_shift->field_name, clk_mgr->clk_mgr_mask->field_name
56
57 #define REG(reg) \
58 (clk_mgr->regs->reg)
59
60 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
61
62 #define BASE(seg) BASE_INNER(seg)
63
64 #define SR(reg_name)\
65 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
66 mm ## reg_name
67
68 #undef CLK_SRI
69 #define CLK_SRI(reg_name, block, inst)\
70 .reg_name = mm ## block ## _ ## reg_name
71
72 static const struct clk_mgr_registers clk_mgr_regs = {
73 CLK_REG_LIST_DCN3()
74 };
75
76 static const struct clk_mgr_shift clk_mgr_shift = {
77 CLK_COMMON_MASK_SH_LIST_DCN20_BASE(__SHIFT)
78 };
79
80 static const struct clk_mgr_mask clk_mgr_mask = {
81 CLK_COMMON_MASK_SH_LIST_DCN20_BASE(_MASK)
82 };
83
84
85 /* Query SMU for all clock states for a particular clock */
dcn3_init_single_clock(struct clk_mgr_internal * clk_mgr,PPCLK_e clk,unsigned int * entry_0,unsigned int * num_levels)86 static void dcn3_init_single_clock(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, unsigned int *entry_0, unsigned int *num_levels)
87 {
88 unsigned int i;
89 char *entry_i = (char *)entry_0;
90 uint32_t ret = dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, 0xFF);
91
92 if (ret & (1 << 31))
93 /* fine-grained, only min and max */
94 *num_levels = 2;
95 else
96 /* discrete, a number of fixed states */
97 /* will set num_levels to 0 on failure */
98 *num_levels = ret & 0xFF;
99
100 /* if the initial message failed, num_levels will be 0 */
101 for (i = 0; i < *num_levels; i++) {
102 *((unsigned int *)entry_i) = (dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, i) & 0xFFFF);
103 entry_i += sizeof(clk_mgr->base.bw_params->clk_table.entries[0]);
104 }
105 }
106
dcn3_build_wm_range_table(struct clk_mgr_internal * clk_mgr)107 static noinline void dcn3_build_wm_range_table(struct clk_mgr_internal *clk_mgr)
108 {
109 /* defaults */
110 double pstate_latency_us = clk_mgr->base.ctx->dc->dml.soc.dram_clock_change_latency_us;
111 double sr_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_exit_time_us;
112 double sr_enter_plus_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_enter_plus_exit_time_us;
113 uint16_t min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz;
114
115 /* Set A - Normal - default values*/
116 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].valid = true;
117 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us = pstate_latency_us;
118 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us = sr_exit_time_us;
119 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;
120 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE;
121 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = 0;
122 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 0xFFFF;
123 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = min_uclk_mhz;
124 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_uclk = 0xFFFF;
125
126 /* Set B - Performance - higher minimum clocks */
127 // clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].valid = true;
128 // clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us = pstate_latency_us;
129 // clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us = sr_exit_time_us;
130 // clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;
131 // clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE;
132 // clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = TUNED VALUE;
133 // clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.max_dcfclk = 0xFFFF;
134 // clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_uclk = TUNED VALUE;
135 // clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.max_uclk = 0xFFFF;
136
137 /* Set C - Dummy P-State - P-State latency set to "dummy p-state" value */
138 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].valid = true;
139 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us = clk_mgr->base.ctx->dc->dml.soc.dummy_pstate_latency_us;
140 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us = sr_exit_time_us;
141 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us = sr_enter_plus_exit_time_us;
142 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.wm_type = WATERMARKS_DUMMY_PSTATE;
143 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_dcfclk = 0;
144 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_dcfclk = 0xFFFF;
145 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.min_uclk = min_uclk_mhz;
146 clk_mgr->base.bw_params->wm_table.nv_entries[WM_C].pmfw_breakdown.max_uclk = 0xFFFF;
147
148 /* Set D - MALL - SR enter and exit times adjusted for MALL */
149 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].valid = true;
150 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us = pstate_latency_us;
151 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us = 2;
152 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us = 4;
153 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.wm_type = WATERMARKS_MALL;
154 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_dcfclk = 0;
155 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_dcfclk = 0xFFFF;
156 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.min_uclk = min_uclk_mhz;
157 clk_mgr->base.bw_params->wm_table.nv_entries[WM_D].pmfw_breakdown.max_uclk = 0xFFFF;
158 }
159
dcn3_init_clocks(struct clk_mgr * clk_mgr_base)160 void dcn3_init_clocks(struct clk_mgr *clk_mgr_base)
161 {
162 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
163 unsigned int num_levels;
164
165 memset(&(clk_mgr_base->clks), 0, sizeof(struct dc_clocks));
166 clk_mgr_base->clks.p_state_change_support = true;
167 clk_mgr_base->clks.prev_p_state_change_support = true;
168 clk_mgr->smu_present = false;
169
170 if (!clk_mgr_base->bw_params)
171 return;
172
173 if (!clk_mgr_base->force_smu_not_present && dcn30_smu_get_smu_version(clk_mgr, &clk_mgr->smu_ver))
174 clk_mgr->smu_present = true;
175
176 if (!clk_mgr->smu_present)
177 return;
178
179 // do we fail if these fail? if so, how? do we not care to check?
180 dcn30_smu_check_driver_if_version(clk_mgr);
181 dcn30_smu_check_msg_header_version(clk_mgr);
182
183 /* DCFCLK */
184 dcn3_init_single_clock(clk_mgr, PPCLK_DCEFCLK,
185 &clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz,
186 &num_levels);
187
188 /* DTBCLK */
189 dcn3_init_single_clock(clk_mgr, PPCLK_DTBCLK,
190 &clk_mgr_base->bw_params->clk_table.entries[0].dtbclk_mhz,
191 &num_levels);
192
193 /* SOCCLK */
194 dcn3_init_single_clock(clk_mgr, PPCLK_SOCCLK,
195 &clk_mgr_base->bw_params->clk_table.entries[0].socclk_mhz,
196 &num_levels);
197 // DPREFCLK ???
198
199 /* DISPCLK */
200 dcn3_init_single_clock(clk_mgr, PPCLK_DISPCLK,
201 &clk_mgr_base->bw_params->clk_table.entries[0].dispclk_mhz,
202 &num_levels);
203
204 /* DPPCLK */
205 dcn3_init_single_clock(clk_mgr, PPCLK_PIXCLK,
206 &clk_mgr_base->bw_params->clk_table.entries[0].dppclk_mhz,
207 &num_levels);
208
209 /* PHYCLK */
210 dcn3_init_single_clock(clk_mgr, PPCLK_PHYCLK,
211 &clk_mgr_base->bw_params->clk_table.entries[0].phyclk_mhz,
212 &num_levels);
213
214 /* Get UCLK, update bounding box */
215 clk_mgr_base->funcs->get_memclk_states_from_smu(clk_mgr_base);
216
217 /* WM range table */
218 DC_FP_START();
219 dcn3_build_wm_range_table(clk_mgr);
220 DC_FP_END();
221 }
222
dcn30_get_vco_frequency_from_reg(struct clk_mgr_internal * clk_mgr)223 static int dcn30_get_vco_frequency_from_reg(struct clk_mgr_internal *clk_mgr)
224 {
225 /* get FbMult value */
226 struct fixed31_32 pll_req;
227 /* get FbMult value */
228 uint32_t pll_req_reg = REG_READ(CLK0_CLK_PLL_REQ);
229
230 /* set up a fixed-point number
231 * this works because the int part is on the right edge of the register
232 * and the frac part is on the left edge
233 */
234 pll_req = dc_fixpt_from_int(pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_int);
235 pll_req.value |= pll_req_reg & clk_mgr->clk_mgr_mask->FbMult_frac;
236
237 /* multiply by REFCLK period */
238 pll_req = dc_fixpt_mul_int(pll_req, clk_mgr->dfs_ref_freq_khz);
239
240 return dc_fixpt_floor(pll_req);
241 }
242
dcn3_update_clocks(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool safe_to_lower)243 static void dcn3_update_clocks(struct clk_mgr *clk_mgr_base,
244 struct dc_state *context,
245 bool safe_to_lower)
246 {
247 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
248 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
249 struct dc *dc = clk_mgr_base->ctx->dc;
250 int display_count;
251 bool update_dppclk = false;
252 bool update_dispclk = false;
253 bool enter_display_off = false;
254 bool dpp_clock_lowered = false;
255 struct dmcu *dmcu = clk_mgr_base->ctx->dc->res_pool->dmcu;
256 bool force_reset = false;
257 bool update_uclk = false;
258 bool p_state_change_support;
259 int total_plane_count;
260
261 if (dc->work_arounds.skip_clock_update || !clk_mgr->smu_present)
262 return;
263
264 if (clk_mgr_base->clks.dispclk_khz == 0 ||
265 (dc->debug.force_clock_mode & 0x1)) {
266 /* this is from resume or boot up, if forced_clock cfg option used, we bypass program dispclk and DPPCLK, but need set them for S3. */
267 force_reset = true;
268
269 dcn2_read_clocks_from_hw_dentist(clk_mgr_base);
270
271 /* force_clock_mode 0x1: force reset the clock even it is the same clock as long as it is in Passive level. */
272 }
273 display_count = clk_mgr_helper_get_active_display_cnt(dc, context);
274
275 if (display_count == 0)
276 enter_display_off = true;
277
278 if (enter_display_off == safe_to_lower)
279 dcn30_smu_set_num_of_displays(clk_mgr, display_count);
280
281 if (dc->debug.force_min_dcfclk_mhz > 0)
282 new_clocks->dcfclk_khz = (new_clocks->dcfclk_khz > (dc->debug.force_min_dcfclk_mhz * 1000)) ?
283 new_clocks->dcfclk_khz : (dc->debug.force_min_dcfclk_mhz * 1000);
284
285 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
286 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
287 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DCEFCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz));
288 }
289
290 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
291 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
292 dcn30_smu_set_min_deep_sleep_dcef_clk(clk_mgr, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_deep_sleep_khz));
293 }
294
295 if (should_set_clock(safe_to_lower, new_clocks->socclk_khz, clk_mgr_base->clks.socclk_khz))
296 /* We don't actually care about socclk, don't notify SMU of hard min */
297 clk_mgr_base->clks.socclk_khz = new_clocks->socclk_khz;
298
299 clk_mgr_base->clks.prev_p_state_change_support = clk_mgr_base->clks.p_state_change_support;
300 total_plane_count = clk_mgr_helper_get_active_plane_cnt(dc, context);
301 p_state_change_support = new_clocks->p_state_change_support || (total_plane_count == 0);
302 if (should_update_pstate_support(safe_to_lower, p_state_change_support, clk_mgr_base->clks.p_state_change_support)) {
303 clk_mgr_base->clks.p_state_change_support = p_state_change_support;
304
305 /* to disable P-State switching, set UCLK min = max */
306 if (!clk_mgr_base->clks.p_state_change_support)
307 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
308 clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz);
309 }
310
311 /* Always update saved value, even if new value not set due to P-State switching unsupported */
312 if (should_set_clock(safe_to_lower, new_clocks->dramclk_khz, clk_mgr_base->clks.dramclk_khz)) {
313 clk_mgr_base->clks.dramclk_khz = new_clocks->dramclk_khz;
314 update_uclk = true;
315 }
316
317 /* set UCLK to requested value if P-State switching is supported, or to re-enable P-State switching */
318 if (clk_mgr_base->clks.p_state_change_support &&
319 (update_uclk || !clk_mgr_base->clks.prev_p_state_change_support))
320 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
321
322 if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr_base->clks.dppclk_khz)) {
323 if (clk_mgr_base->clks.dppclk_khz > new_clocks->dppclk_khz)
324 dpp_clock_lowered = true;
325
326 clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
327 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_PIXCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dppclk_khz));
328 update_dppclk = true;
329 }
330
331 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
332 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
333 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dispclk_khz));
334 update_dispclk = true;
335 }
336
337 if (dc->config.forced_clocks == false || (force_reset && safe_to_lower)) {
338 if (dpp_clock_lowered) {
339 /* if clock is being lowered, increase DTO before lowering refclk */
340 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
341 dcn20_update_clocks_update_dentist(clk_mgr, context);
342 } else {
343 /* if clock is being raised, increase refclk before lowering DTO */
344 if (update_dppclk || update_dispclk)
345 dcn20_update_clocks_update_dentist(clk_mgr, context);
346 /* There is a check inside dcn20_update_clocks_update_dpp_dto which ensures
347 * that we do not lower dto when it is not safe to lower. We do not need to
348 * compare the current and new dppclk before calling this function.*/
349 dcn20_update_clocks_update_dpp_dto(clk_mgr, context, safe_to_lower);
350 }
351 }
352
353 if (update_dispclk && dmcu && dmcu->funcs->is_dmcu_initialized(dmcu))
354 /*update dmcu for wait_loop count*/
355 dmcu->funcs->set_psr_wait_loop(dmcu,
356 clk_mgr_base->clks.dispclk_khz / 1000 / 7);
357 }
358
359
dcn3_notify_wm_ranges(struct clk_mgr * clk_mgr_base)360 static void dcn3_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
361 {
362 unsigned int i;
363 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
364 WatermarksExternal_t *table = (WatermarksExternal_t *) clk_mgr->wm_range_table;
365
366 if (!clk_mgr->smu_present)
367 return;
368
369 if (!table)
370 // should log failure
371 return;
372
373 memset(table, 0, sizeof(*table));
374
375 /* collect valid ranges, place in pmfw table */
376 for (i = 0; i < WM_SET_COUNT; i++)
377 if (clk_mgr->base.bw_params->wm_table.nv_entries[i].valid) {
378 table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MinClock = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.min_dcfclk;
379 table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MaxClock = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.max_dcfclk;
380 table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MinUclk = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.min_uclk;
381 table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MaxUclk = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.max_uclk;
382 table->Watermarks.WatermarkRow[WM_DCEFCLK][i].WmSetting = i;
383 table->Watermarks.WatermarkRow[WM_DCEFCLK][i].Flags = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.wm_type;
384 }
385
386 dcn30_smu_set_dram_addr_high(clk_mgr, clk_mgr->wm_range_table_addr >> 32);
387 dcn30_smu_set_dram_addr_low(clk_mgr, clk_mgr->wm_range_table_addr & 0xFFFFFFFF);
388 dcn30_smu_transfer_wm_table_dram_2_smu(clk_mgr);
389 }
390
391 /* Set min memclk to minimum, either constrained by the current mode or DPM0 */
dcn3_set_hard_min_memclk(struct clk_mgr * clk_mgr_base,bool current_mode)392 static void dcn3_set_hard_min_memclk(struct clk_mgr *clk_mgr_base, bool current_mode)
393 {
394 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
395
396 if (!clk_mgr->smu_present)
397 return;
398
399 if (current_mode) {
400 if (clk_mgr_base->clks.p_state_change_support)
401 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
402 khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
403 else
404 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
405 clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz);
406 } else {
407 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
408 clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz);
409 }
410 }
411
412 /* Set max memclk to highest DPM value */
dcn3_set_hard_max_memclk(struct clk_mgr * clk_mgr_base)413 static void dcn3_set_hard_max_memclk(struct clk_mgr *clk_mgr_base)
414 {
415 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
416
417 if (!clk_mgr->smu_present)
418 return;
419
420 dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK,
421 clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz);
422 }
423
424 /* Get current memclk states, update bounding box */
dcn3_get_memclk_states_from_smu(struct clk_mgr * clk_mgr_base)425 static void dcn3_get_memclk_states_from_smu(struct clk_mgr *clk_mgr_base)
426 {
427 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
428 unsigned int num_levels;
429
430 if (!clk_mgr->smu_present)
431 return;
432
433 /* Refresh memclk states */
434 dcn3_init_single_clock(clk_mgr, PPCLK_UCLK,
435 &clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz,
436 &num_levels);
437 clk_mgr_base->bw_params->clk_table.num_entries = num_levels ? num_levels : 1;
438
439 /* Refresh bounding box */
440 clk_mgr_base->ctx->dc->res_pool->funcs->update_bw_bounding_box(
441 clk_mgr->base.ctx->dc, clk_mgr_base->bw_params);
442 }
443
dcn3_is_smu_present(struct clk_mgr * clk_mgr_base)444 static bool dcn3_is_smu_present(struct clk_mgr *clk_mgr_base)
445 {
446 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
447 return clk_mgr->smu_present;
448 }
449
dcn3_are_clock_states_equal(struct dc_clocks * a,struct dc_clocks * b)450 static bool dcn3_are_clock_states_equal(struct dc_clocks *a,
451 struct dc_clocks *b)
452 {
453 if (a->dispclk_khz != b->dispclk_khz)
454 return false;
455 else if (a->dppclk_khz != b->dppclk_khz)
456 return false;
457 else if (a->dcfclk_khz != b->dcfclk_khz)
458 return false;
459 else if (a->dcfclk_deep_sleep_khz != b->dcfclk_deep_sleep_khz)
460 return false;
461 else if (a->dramclk_khz != b->dramclk_khz)
462 return false;
463 else if (a->p_state_change_support != b->p_state_change_support)
464 return false;
465
466 return true;
467 }
468
dcn3_enable_pme_wa(struct clk_mgr * clk_mgr_base)469 static void dcn3_enable_pme_wa(struct clk_mgr *clk_mgr_base)
470 {
471 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
472
473 if (!clk_mgr->smu_present)
474 return;
475
476 dcn30_smu_set_pme_workaround(clk_mgr);
477 }
478
479 /* Notify clk_mgr of a change in link rate, update phyclk frequency if necessary */
dcn30_notify_link_rate_change(struct clk_mgr * clk_mgr_base,struct dc_link * link)480 static void dcn30_notify_link_rate_change(struct clk_mgr *clk_mgr_base, struct dc_link *link)
481 {
482 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
483 unsigned int i, max_phyclk_req = clk_mgr_base->bw_params->clk_table.entries[0].phyclk_mhz * 1000;
484
485 if (!clk_mgr->smu_present)
486 return;
487
488 clk_mgr->cur_phyclk_req_table[link->link_index] = link->cur_link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
489
490 for (i = 0; i < MAX_PIPES * 2; i++) {
491 if (clk_mgr->cur_phyclk_req_table[i] > max_phyclk_req)
492 max_phyclk_req = clk_mgr->cur_phyclk_req_table[i];
493 }
494
495 if (max_phyclk_req != clk_mgr_base->clks.phyclk_khz) {
496 clk_mgr_base->clks.phyclk_khz = max_phyclk_req;
497 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_PHYCLK, khz_to_mhz_ceil(clk_mgr_base->clks.phyclk_khz));
498 }
499 }
500
501 static struct clk_mgr_funcs dcn3_funcs = {
502 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
503 .update_clocks = dcn3_update_clocks,
504 .init_clocks = dcn3_init_clocks,
505 .notify_wm_ranges = dcn3_notify_wm_ranges,
506 .set_hard_min_memclk = dcn3_set_hard_min_memclk,
507 .set_hard_max_memclk = dcn3_set_hard_max_memclk,
508 .get_memclk_states_from_smu = dcn3_get_memclk_states_from_smu,
509 .are_clock_states_equal = dcn3_are_clock_states_equal,
510 .enable_pme_wa = dcn3_enable_pme_wa,
511 .notify_link_rate_change = dcn30_notify_link_rate_change,
512 .is_smu_present = dcn3_is_smu_present
513 };
514
dcn3_init_clocks_fpga(struct clk_mgr * clk_mgr)515 static void dcn3_init_clocks_fpga(struct clk_mgr *clk_mgr)
516 {
517 dcn2_init_clocks(clk_mgr);
518
519 /* TODO: Implement the functions and remove the ifndef guard */
520 }
521
522 struct clk_mgr_funcs dcn3_fpga_funcs = {
523 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
524 .update_clocks = dcn2_update_clocks_fpga,
525 .init_clocks = dcn3_init_clocks_fpga,
526 };
527
528 /*todo for dcn30 for clk register offset*/
dcn3_clk_mgr_construct(struct dc_context * ctx,struct clk_mgr_internal * clk_mgr,struct pp_smu_funcs * pp_smu,struct dccg * dccg)529 void dcn3_clk_mgr_construct(
530 struct dc_context *ctx,
531 struct clk_mgr_internal *clk_mgr,
532 struct pp_smu_funcs *pp_smu,
533 struct dccg *dccg)
534 {
535 clk_mgr->base.ctx = ctx;
536 clk_mgr->base.funcs = &dcn3_funcs;
537 clk_mgr->regs = &clk_mgr_regs;
538 clk_mgr->clk_mgr_shift = &clk_mgr_shift;
539 clk_mgr->clk_mgr_mask = &clk_mgr_mask;
540
541 clk_mgr->dccg = dccg;
542 clk_mgr->dfs_bypass_disp_clk = 0;
543
544 clk_mgr->dprefclk_ss_percentage = 0;
545 clk_mgr->dprefclk_ss_divider = 1000;
546 clk_mgr->ss_on_dprefclk = false;
547 clk_mgr->dfs_ref_freq_khz = 100000;
548
549 clk_mgr->base.dprefclk_khz = 730000; // 700 MHz planned if VCO is 3.85 GHz, will be retrieved
550
551 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment)) {
552 clk_mgr->base.funcs = &dcn3_fpga_funcs;
553 clk_mgr->base.dentist_vco_freq_khz = 3650000;
554
555 } else {
556 struct clk_state_registers_and_bypass s = { 0 };
557
558 /* integer part is now VCO frequency in kHz */
559 clk_mgr->base.dentist_vco_freq_khz = dcn30_get_vco_frequency_from_reg(clk_mgr);
560
561 /* in case we don't get a value from the register, use default */
562 if (clk_mgr->base.dentist_vco_freq_khz == 0)
563 clk_mgr->base.dentist_vco_freq_khz = 3650000;
564 /* Convert dprefclk units from MHz to KHz */
565 /* Value already divided by 10, some resolution lost */
566
567 /*TODO: uncomment assert once dcn3_dump_clk_registers is implemented */
568 //ASSERT(s.dprefclk != 0);
569 if (s.dprefclk != 0)
570 clk_mgr->base.dprefclk_khz = s.dprefclk * 1000;
571 }
572
573 clk_mgr->dfs_bypass_enabled = false;
574
575 clk_mgr->smu_present = false;
576
577 dce_clock_read_ss_info(clk_mgr);
578
579 clk_mgr->base.bw_params = kzalloc(sizeof(*clk_mgr->base.bw_params), GFP_KERNEL);
580
581 /* need physical address of table to give to PMFW */
582 clk_mgr->wm_range_table = dm_helpers_allocate_gpu_mem(clk_mgr->base.ctx,
583 DC_MEM_ALLOC_TYPE_GART, sizeof(WatermarksExternal_t),
584 &clk_mgr->wm_range_table_addr);
585 }
586
dcn3_clk_mgr_destroy(struct clk_mgr_internal * clk_mgr)587 void dcn3_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr)
588 {
589 kfree(clk_mgr->base.bw_params);
590
591 if (clk_mgr->wm_range_table)
592 dm_helpers_free_gpu_mem(clk_mgr->base.ctx, DC_MEM_ALLOC_TYPE_GART,
593 clk_mgr->wm_range_table);
594 }
595