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Searched defs:ddr_type (Results 1 – 17 of 17) sorted by relevance

/u-boot/arch/mips/mach-mtmips/mt7628/
A Dddr.c75 static void mt7628_ddr_pad_ldo_config(int ddr_type, int pkg_type) in mt7628_ddr_pad_ldo_config()
134 int ddr_type, pkg_type, lspd; in mt7628_ddr_init() local
/u-boot/arch/arm/mach-stm32mp/include/mach/
A Dddr.h10 enum ddr_type { enum
/u-boot/drivers/ram/octeon/
A Ddimm_spd_eeprom.c293 int ddr_type) in get_dimm_ecc()
299 int ddr_type) in get_dimm_module_type()
327 int dimm, const char **dimm_types, int ddr_type, in report_common_dimm()
398 int ddr_type; in report_dimm() local
A Docteon_ddr.c156 int ddr_type; in octeon3_refclock() local
433 int ddr_type; in initialize_ddr_clock() local
1566 int ddr_type) in validate_ddr3_rlevel_bitmask()
/u-boot/drivers/ddr/marvell/a38x/
A Dddr3_init.c9 static char *ddr_type = "DDR3"; variable
A Dmv_ddr_plat.c1101 static int ddr3_restore_and_set_final_windows(u32 *win, const char *ddr_type) in ddr3_restore_and_set_final_windows()
1209 int mv_ddr_pre_training_soc_config(const char *ddr_type) in mv_ddr_pre_training_soc_config()
1319 int mv_ddr_post_training_soc_config(const char *ddr_type) in mv_ddr_post_training_soc_config()
/u-boot/board/st/common/
A Dstpmic1.c18 int board_ddr_power_init(enum ddr_type ddr_type) in board_ddr_power_init()
/u-boot/arch/mips/mach-mtmips/mt7620/
A Ddram.c71 int ddr_type, aux; in mt7620_dram_init() local
/u-boot/drivers/ddr/imx/imx8m/
A Dddrphy_utils.c218 unsigned int i, ddr_type, tmp; in get_trained_CDD() local
273 unsigned int i, ddr_type; in update_umctl2_rank_space_setting() local
/u-boot/arch/x86/include/asm/arch-quark/
A Dmrc.h114 uint8_t ddr_type; /* DDR3, DDR3L */ member
/u-boot/arch/x86/include/asm/
A Dglobal_data.h24 uint16_t ddr_type; member
/u-boot/drivers/ram/
A Dmpc83xx_sdram.c321 u32 dso, pz_override, nz_override, odt_term, ddr_type, mvref_sel, m_odr; in mpc83xx_sdram_probe() local
/u-boot/drivers/ram/stm32mp1/
A Dstm32mp1_ddr.c668 __weak int board_ddr_power_init(enum ddr_type ddr_type) in board_ddr_power_init()
/u-boot/drivers/ddr/fsl/
A Dctrl_regs.c2609 u32 sdram_cfg, i, tmp, lanes, ddr_type; in erratum_a009942_check_cpo() local
/u-boot/arch/arm/include/asm/arch-rockchip/
A Dsdram_rk3036.h317 u32 ddr_type; member
/u-boot/arch/mips/mach-octeon/include/mach/
A Docteon_ddr.h768 enum ddr_type { enum
/u-boot/arch/arm/include/asm/arch-mx6/
A Dmx6-ddr.h428 u8 ddr_type; /* DDR type: DDR3(0) or LPDDR2(1) */ member

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