1 /* 2 * Copyright 2021 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 #ifndef DIMM_H 9 #define DIMM_H 10 11 #define SPD_MEMTYPE_DDR4 0x0C 12 13 #define DDR4_SPD_MODULETYPE_MASK 0x0f 14 #define DDR4_SPD_MODULETYPE_EXT 0x00 15 #define DDR4_SPD_RDIMM 0x01 16 #define DDR4_SPD_UDIMM 0x02 17 #define DDR4_SPD_SO_DIMM 0x03 18 #define DDR4_SPD_LRDIMM 0x04 19 #define DDR4_SPD_MINI_RDIMM 0x05 20 #define DDR4_SPD_MINI_UDIMM 0x06 21 #define DDR4_SPD_72B_SO_RDIMM 0x08 22 #define DDR4_SPD_72B_SO_UDIMM 0x09 23 #define DDR4_SPD_16B_SO_DIMM 0x0c 24 #define DDR4_SPD_32B_SO_DIMM 0x0d 25 26 #define SPD_SPA0_ADDRESS 0x36 27 #define SPD_SPA1_ADDRESS 0x37 28 29 #define spd_to_ps(mtb, ftb) \ 30 ((mtb) * pdimm->mtb_ps + ((ftb) * pdimm->ftb_10th_ps) / 10) 31 32 #ifdef DDR_DEBUG 33 #define dump_spd(spd, len) { \ 34 register int i; \ 35 register unsigned char *buf = (void *)(spd); \ 36 \ 37 for (i = 0; i < (len); i++) { \ 38 print_uint(i); \ 39 puts("\t: 0x"); \ 40 print_hex(buf[i]); \ 41 puts("\n"); \ 42 } \ 43 } 44 #else 45 #define dump_spd(spd, len) {} 46 #endif 47 48 /* From JEEC Standard No. 21-C release 23A */ 49 struct ddr4_spd { 50 /* General Section: Bytes 0-127 */ 51 unsigned char info_size_crc; /* 0 # bytes */ 52 unsigned char spd_rev; /* 1 Total # bytes of SPD */ 53 unsigned char mem_type; /* 2 Key Byte / mem type */ 54 unsigned char module_type; /* 3 Key Byte / Module Type */ 55 unsigned char density_banks; /* 4 Density and Banks */ 56 unsigned char addressing; /* 5 Addressing */ 57 unsigned char package_type; /* 6 Package type */ 58 unsigned char opt_feature; /* 7 Optional features */ 59 unsigned char thermal_ref; /* 8 Thermal and refresh */ 60 unsigned char oth_opt_features; /* 9 Other optional features */ 61 unsigned char res_10; /* 10 Reserved */ 62 unsigned char module_vdd; /* 11 Module nominal voltage */ 63 unsigned char organization; /* 12 Module Organization */ 64 unsigned char bus_width; /* 13 Module Memory Bus Width */ 65 unsigned char therm_sensor; /* 14 Module Thermal Sensor */ 66 unsigned char ext_type; /* 15 Extended module type */ 67 unsigned char res_16; 68 unsigned char timebases; /* 17 MTb and FTB */ 69 unsigned char tck_min; /* 18 tCKAVGmin */ 70 unsigned char tck_max; /* 19 TCKAVGmax */ 71 unsigned char caslat_b1; /* 20 CAS latencies, 1st byte */ 72 unsigned char caslat_b2; /* 21 CAS latencies, 2nd byte */ 73 unsigned char caslat_b3; /* 22 CAS latencies, 3rd byte */ 74 unsigned char caslat_b4; /* 23 CAS latencies, 4th byte */ 75 unsigned char taa_min; /* 24 Min CAS Latency Time */ 76 unsigned char trcd_min; /* 25 Min RAS# to CAS# Delay Time */ 77 unsigned char trp_min; /* 26 Min Row Precharge Delay Time */ 78 unsigned char tras_trc_ext; /* 27 Upper Nibbles for tRAS and tRC */ 79 unsigned char tras_min_lsb; /* 28 tRASmin, lsb */ 80 unsigned char trc_min_lsb; /* 29 tRCmin, lsb */ 81 unsigned char trfc1_min_lsb; /* 30 Min Refresh Recovery Delay Time */ 82 unsigned char trfc1_min_msb; /* 31 Min Refresh Recovery Delay Time */ 83 unsigned char trfc2_min_lsb; /* 32 Min Refresh Recovery Delay Time */ 84 unsigned char trfc2_min_msb; /* 33 Min Refresh Recovery Delay Time */ 85 unsigned char trfc4_min_lsb; /* 34 Min Refresh Recovery Delay Time */ 86 unsigned char trfc4_min_msb; /* 35 Min Refresh Recovery Delay Time */ 87 unsigned char tfaw_msb; /* 36 Upper Nibble for tFAW */ 88 unsigned char tfaw_min; /* 37 tFAW, lsb */ 89 unsigned char trrds_min; /* 38 tRRD_Smin, MTB */ 90 unsigned char trrdl_min; /* 39 tRRD_Lmin, MTB */ 91 unsigned char tccdl_min; /* 40 tCCS_Lmin, MTB */ 92 unsigned char res_41[60-41]; /* 41 Rserved */ 93 unsigned char mapping[78-60]; /* 60~77 Connector to SDRAM bit map */ 94 unsigned char res_78[117-78]; /* 78~116, Reserved */ 95 signed char fine_tccdl_min; /* 117 Fine offset for tCCD_Lmin */ 96 signed char fine_trrdl_min; /* 118 Fine offset for tRRD_Lmin */ 97 signed char fine_trrds_min; /* 119 Fine offset for tRRD_Smin */ 98 signed char fine_trc_min; /* 120 Fine offset for tRCmin */ 99 signed char fine_trp_min; /* 121 Fine offset for tRPmin */ 100 signed char fine_trcd_min; /* 122 Fine offset for tRCDmin */ 101 signed char fine_taa_min; /* 123 Fine offset for tAAmin */ 102 signed char fine_tck_max; /* 124 Fine offset for tCKAVGmax */ 103 signed char fine_tck_min; /* 125 Fine offset for tCKAVGmin */ 104 /* CRC: Bytes 126-127 */ 105 unsigned char crc[2]; /* 126-127 SPD CRC */ 106 107 /* Module-Specific Section: Bytes 128-255 */ 108 union { 109 struct { 110 /* 128 (Unbuffered) Module Nominal Height */ 111 unsigned char mod_height; 112 /* 129 (Unbuffered) Module Maximum Thickness */ 113 unsigned char mod_thickness; 114 /* 130 (Unbuffered) Reference Raw Card Used */ 115 unsigned char ref_raw_card; 116 /* 131 (Unbuffered) Address Mapping from 117 * Edge Connector to DRAM 118 */ 119 unsigned char addr_mapping; 120 /* 132~253 (Unbuffered) Reserved */ 121 unsigned char res_132[254-132]; 122 /* 254~255 CRC */ 123 unsigned char crc[2]; 124 } unbuffered; 125 struct { 126 /* 128 (Registered) Module Nominal Height */ 127 unsigned char mod_height; 128 /* 129 (Registered) Module Maximum Thickness */ 129 unsigned char mod_thickness; 130 /* 130 (Registered) Reference Raw Card Used */ 131 unsigned char ref_raw_card; 132 /* 131 DIMM Module Attributes */ 133 unsigned char modu_attr; 134 /* 132 RDIMM Thermal Heat Spreader Solution */ 135 unsigned char thermal; 136 /* 133 Register Manufacturer ID Code, LSB */ 137 unsigned char reg_id_lo; 138 /* 134 Register Manufacturer ID Code, MSB */ 139 unsigned char reg_id_hi; 140 /* 135 Register Revision Number */ 141 unsigned char reg_rev; 142 /* 136 Address mapping from register to DRAM */ 143 unsigned char reg_map; 144 unsigned char ca_stren; 145 unsigned char clk_stren; 146 /* 139~253 Reserved */ 147 unsigned char res_139[254-139]; 148 /* 254~255 CRC */ 149 unsigned char crc[2]; 150 } registered; 151 struct { 152 /* 128 (Loadreduced) Module Nominal Height */ 153 unsigned char mod_height; 154 /* 129 (Loadreduced) Module Maximum Thickness */ 155 unsigned char mod_thickness; 156 /* 130 (Loadreduced) Reference Raw Card Used */ 157 unsigned char ref_raw_card; 158 /* 131 DIMM Module Attributes */ 159 unsigned char modu_attr; 160 /* 132 RDIMM Thermal Heat Spreader Solution */ 161 unsigned char thermal; 162 /* 133 Register Manufacturer ID Code, LSB */ 163 unsigned char reg_id_lo; 164 /* 134 Register Manufacturer ID Code, MSB */ 165 unsigned char reg_id_hi; 166 /* 135 Register Revision Number */ 167 unsigned char reg_rev; 168 /* 136 Address mapping from register to DRAM */ 169 unsigned char reg_map; 170 /* 137 Register Output Drive Strength for CMD/Add*/ 171 unsigned char reg_drv; 172 /* 138 Register Output Drive Strength for CK */ 173 unsigned char reg_drv_ck; 174 /* 139 Data Buffer Revision Number */ 175 unsigned char data_buf_rev; 176 /* 140 DRAM VrefDQ for Package Rank 0 */ 177 unsigned char vrefqe_r0; 178 /* 141 DRAM VrefDQ for Package Rank 1 */ 179 unsigned char vrefqe_r1; 180 /* 142 DRAM VrefDQ for Package Rank 2 */ 181 unsigned char vrefqe_r2; 182 /* 143 DRAM VrefDQ for Package Rank 3 */ 183 unsigned char vrefqe_r3; 184 /* 144 Data Buffer VrefDQ for DRAM Interface */ 185 unsigned char data_intf; 186 /* 187 * 145 Data Buffer MDQ Drive Strength and RTT 188 * for data rate <= 1866 189 */ 190 unsigned char data_drv_1866; 191 /* 192 * 146 Data Buffer MDQ Drive Strength and RTT 193 * for 1866 < data rate <= 2400 194 */ 195 unsigned char data_drv_2400; 196 /* 197 * 147 Data Buffer MDQ Drive Strength and RTT 198 * for 2400 < data rate <= 3200 199 */ 200 unsigned char data_drv_3200; 201 /* 148 DRAM Drive Strength */ 202 unsigned char dram_drv; 203 /* 204 * 149 DRAM ODT (RTT_WR, RTT_NOM) 205 * for data rate <= 1866 206 */ 207 unsigned char dram_odt_1866; 208 /* 209 * 150 DRAM ODT (RTT_WR, RTT_NOM) 210 * for 1866 < data rate <= 2400 211 */ 212 unsigned char dram_odt_2400; 213 /* 214 * 151 DRAM ODT (RTT_WR, RTT_NOM) 215 * for 2400 < data rate <= 3200 216 */ 217 unsigned char dram_odt_3200; 218 /* 219 * 152 DRAM ODT (RTT_PARK) 220 * for data rate <= 1866 221 */ 222 unsigned char dram_odt_park_1866; 223 /* 224 * 153 DRAM ODT (RTT_PARK) 225 * for 1866 < data rate <= 2400 226 */ 227 unsigned char dram_odt_park_2400; 228 /* 229 * 154 DRAM ODT (RTT_PARK) 230 * for 2400 < data rate <= 3200 231 */ 232 unsigned char dram_odt_park_3200; 233 unsigned char res_155[254-155]; /* Reserved */ 234 /* 254~255 CRC */ 235 unsigned char crc[2]; 236 } loadreduced; 237 unsigned char uc[128]; /* 128-255 Module-Specific Section */ 238 } mod_section; 239 240 unsigned char res_256[320-256]; /* 256~319 Reserved */ 241 242 /* Module supplier's data: Byte 320~383 */ 243 unsigned char mmid_lsb; /* 320 Module MfgID Code LSB */ 244 unsigned char mmid_msb; /* 321 Module MfgID Code MSB */ 245 unsigned char mloc; /* 322 Mfg Location */ 246 unsigned char mdate[2]; /* 323~324 Mfg Date */ 247 unsigned char sernum[4]; /* 325~328 Module Serial Number */ 248 unsigned char mpart[20]; /* 329~348 Mfg's Module Part Number */ 249 unsigned char mrev; /* 349 Module Revision Code */ 250 unsigned char dmid_lsb; /* 350 DRAM MfgID Code LSB */ 251 unsigned char dmid_msb; /* 351 DRAM MfgID Code MSB */ 252 unsigned char stepping; /* 352 DRAM stepping */ 253 unsigned char msd[29]; /* 353~381 Mfg's Specific Data */ 254 unsigned char res_382[2]; /* 382~383 Reserved */ 255 }; 256 257 /* Parameters for a DDR dimm computed from the SPD */ 258 struct dimm_params { 259 /* DIMM organization parameters */ 260 char mpart[19]; /* guaranteed null terminated */ 261 262 unsigned int n_ranks; 263 unsigned int die_density; 264 unsigned long long rank_density; 265 unsigned long long capacity; 266 unsigned int primary_sdram_width; 267 unsigned int ec_sdram_width; 268 unsigned int rdimm; 269 unsigned int package_3ds; /* number of dies in 3DS */ 270 unsigned int device_width; /* x4, x8, x16 components */ 271 unsigned int rc; 272 273 /* SDRAM device parameters */ 274 unsigned int n_row_addr; 275 unsigned int n_col_addr; 276 unsigned int edc_config; /* 0 = none, 1 = parity, 2 = ECC */ 277 unsigned int bank_addr_bits; 278 unsigned int bank_group_bits; 279 unsigned int burst_lengths_bitmask; /* BL=4 bit 2, BL=8 = bit 3 */ 280 281 /* mirrored DIMMs */ 282 unsigned int mirrored_dimm; /* only for ddr3 */ 283 284 /* DIMM timing parameters */ 285 286 int mtb_ps; /* medium timebase ps */ 287 int ftb_10th_ps; /* fine timebase, in 1/10 ps */ 288 int taa_ps; /* minimum CAS latency time */ 289 int tfaw_ps; /* four active window delay */ 290 291 /* 292 * SDRAM clock periods 293 * The range for these are 1000-10000 so a short should be sufficient 294 */ 295 int tckmin_x_ps; 296 int tckmax_ps; 297 298 /* SPD-defined CAS latencies */ 299 unsigned int caslat_x; 300 301 /* basic timing parameters */ 302 int trcd_ps; 303 int trp_ps; 304 int tras_ps; 305 306 int trfc1_ps; 307 int trfc2_ps; 308 int trfc4_ps; 309 int trrds_ps; 310 int trrdl_ps; 311 int tccdl_ps; 312 int trfc_slr_ps; 313 314 int trc_ps; /* maximum = 254 ns + .75 ns = 254750 ps */ 315 int twr_ps; /* 15ns for all speed bins */ 316 317 unsigned int refresh_rate_ps; 318 unsigned int extended_op_srt; 319 320 /* RDIMM */ 321 unsigned char rcw[16]; /* Register Control Word 0-15 */ 322 unsigned int dq_mapping[18]; 323 unsigned int dq_mapping_ors; 324 }; 325 326 int read_spd(unsigned char chip, void *buf, int len); 327 int crc16(unsigned char *ptr, int count); 328 int cal_dimm_params(const struct ddr4_spd *spd, struct dimm_params *pdimm); 329 330 #endif /* DIMM_H */ 331