Searched defs:div0 (Results 1 – 4 of 4) sorted by relevance
| /u-boot/drivers/clk/ |
| A D | clk_zynq.c | 230 u32 clk_ctrl, div0, div1; in zynq_clk_get_dci_rate() local
246 u32 clk_ctrl, div0; in zynq_clk_get_peripheral_rate() local
292 u32 *div0, u32 *div1) in zynq_clk_calc_peripheral_two_divs()
321 u32 clk_ctrl, div0 = 0, div1 = 0; in zynq_clk_set_peripheral_rate() local
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| A D | clk_zynqmp.c | 429 u32 clk_ctrl, div0; in zynqmp_clk_get_peripheral_rate() local
464 u32 clk_ctrl, div0; in zynqmp_clk_get_wdt_rate() local
505 u32 *div0, u32 *div1) in zynqmp_clk_calc_peripheral_two_divs()
534 u32 clk_ctrl, div0 = 0, div1 = 0; in zynqmp_clk_set_peripheral_rate() local
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| /u-boot/arch/arm/mach-s5pc1xx/include/mach/ |
| A D | clock.h | 28 unsigned int div0; member
64 unsigned int div0; member
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| /u-boot/arch/arm/include/asm/arch-sunxi/ |
| A D | clock_sun50i_h6.h | 245 #define CCM_PLL5_CTRL_DIV2(div0) ((div0) << 1) argument
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