Searched defs:div1 (Results 1 – 8 of 8) sorted by relevance
| /u-boot/arch/arm/mach-sunxi/ |
| A D | clock_sun8i_a83t.c | 112 unsigned int div1 = 0, div2 = 0; in clock_set_pll5() local
131 int div1 = ((rval & CCM_PLL6_CTRL_DIV1_MASK) >> in clock_get_pll6() local
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| A D | clock_sun50i_h6.c | 98 int div1 = ((rval & CCM_PLL6_CTRL_DIV1_MASK) >> in clock_get_pll6() local
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| /u-boot/drivers/clk/ |
| A D | clk_zynq.c | 230 u32 clk_ctrl, div0, div1; in zynq_clk_get_dci_rate() local
247 u32 div1 = 1; in zynq_clk_get_peripheral_rate() local
292 u32 *div0, u32 *div1) in zynq_clk_calc_peripheral_two_divs()
321 u32 clk_ctrl, div0 = 0, div1 = 0; in zynq_clk_set_peripheral_rate() local
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| A D | clk_zynqmp.c | 430 u32 div1 = 1; in zynqmp_clk_get_peripheral_rate() local
465 u32 div1 = 1; in zynqmp_clk_get_wdt_rate() local
505 u32 *div0, u32 *div1) in zynqmp_clk_calc_peripheral_two_divs()
534 u32 clk_ctrl, div0 = 0, div1 = 0; in zynqmp_clk_set_peripheral_rate() local
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| /u-boot/drivers/clk/imx/ |
| A D | clk-composite-8m.c | 62 int div1, div2; in imx8m_clk_composite_compute_dividers() local
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| /u-boot/arch/arm/mach-s5pc1xx/include/mach/ |
| A D | clock.h | 29 unsigned int div1; member
65 unsigned int div1; member
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| /u-boot/arch/arm/mach-keystone/include/mach/ |
| A D | clock_defs.h | 24 u32 div1; /* 18 */ member
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| /u-boot/arch/arm/include/asm/arch-sunxi/ |
| A D | clock_sun50i_h6.h | 244 #define CCM_PLL5_CTRL_DIV1(div1) ((div1) << 0) argument
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