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Searched defs:divn (Results 1 – 8 of 8) sorted by relevance

/u-boot/arch/arm/mach-uniphier/clk/
A Dpll-base-ld20.c33 unsigned int ssc_rate, unsigned int divn) in uniphier_ld20_sscpll_init()
/u-boot/arch/arm/mach-tegra/
A Dcpu.c172 int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm, in pllx_set_rate()
A Dclock.c92 int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn, in clock_ll_read_pll()
116 unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn, in clock_start_pll()
/u-boot/arch/arm/include/asm/arch-tegra/
A Dwarmboot.h73 u32 divn:10; member
/u-boot/arch/arm/mach-tegra/tegra20/
A Dwarmboot.c154 u32 divm, divn, divp, cpcon, lfcon; in warmboot_save_sdram_params() local
/u-boot/drivers/clk/
A Dclk_stm32mp1.c903 int divm, divn; in pll_get_fvco() local
1324 u32 divm, divn, divp, frac; in stm32mp1_pll1_opp() local
1698 int divm, divn, divy; in pll_set_rate() local
A Dclk_stm32h7.c326 u16 divn; member
/u-boot/arch/arm/mach-tegra/tegra124/
A Dclock.c1069 u32 divm, divn, divp, cpcon; in clock_set_display_rate() local

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