1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * PCI autoconfiguration library
4 *
5 * Author: Matt Porter <mporter@mvista.com>
6 *
7 * Copyright 2000 MontaVista Software Inc.
8 */
9
10 #include <common.h>
11 #include <dm.h>
12 #include <errno.h>
13 #include <log.h>
14 #include <pci.h>
15
16 /* the user can define CONFIG_SYS_PCI_CACHE_LINE_SIZE to avoid problems */
17 #ifndef CONFIG_SYS_PCI_CACHE_LINE_SIZE
18 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8
19 #endif
20
dm_pciauto_setup_device(struct udevice * dev,int bars_num,struct pci_region * mem,struct pci_region * prefetch,struct pci_region * io)21 static void dm_pciauto_setup_device(struct udevice *dev, int bars_num,
22 struct pci_region *mem,
23 struct pci_region *prefetch,
24 struct pci_region *io)
25 {
26 u32 bar_response;
27 pci_size_t bar_size;
28 u16 cmdstat = 0;
29 int bar, bar_nr = 0;
30 u8 header_type;
31 int rom_addr;
32 pci_addr_t bar_value;
33 struct pci_region *bar_res = NULL;
34 int found_mem64 = 0;
35 u16 class;
36
37 dm_pci_read_config16(dev, PCI_COMMAND, &cmdstat);
38 cmdstat = (cmdstat & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) |
39 PCI_COMMAND_MASTER;
40
41 for (bar = PCI_BASE_ADDRESS_0;
42 bar < PCI_BASE_ADDRESS_0 + (bars_num * 4); bar += 4) {
43 int ret = 0;
44
45 /* Tickle the BAR and get the response */
46 dm_pci_write_config32(dev, bar, 0xffffffff);
47 dm_pci_read_config32(dev, bar, &bar_response);
48
49 /* If BAR is not implemented (or invalid) go to the next BAR */
50 if (!bar_response || bar_response == 0xffffffff)
51 continue;
52
53 found_mem64 = 0;
54
55 /* Check the BAR type and set our address mask */
56 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
57 bar_size = bar_response & PCI_BASE_ADDRESS_IO_MASK;
58 bar_size &= ~(bar_size - 1);
59
60 bar_res = io;
61
62 debug("PCI Autoconfig: BAR %d, I/O, size=0x%llx, ",
63 bar_nr, (unsigned long long)bar_size);
64 } else {
65 if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
66 PCI_BASE_ADDRESS_MEM_TYPE_64) {
67 u32 bar_response_upper;
68 u64 bar64;
69
70 dm_pci_write_config32(dev, bar + 4, 0xffffffff);
71 dm_pci_read_config32(dev, bar + 4,
72 &bar_response_upper);
73
74 bar64 = ((u64)bar_response_upper << 32) |
75 bar_response;
76
77 bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK)
78 + 1;
79 found_mem64 = 1;
80 } else {
81 bar_size = (u32)(~(bar_response &
82 PCI_BASE_ADDRESS_MEM_MASK) + 1);
83 }
84
85 if (prefetch &&
86 (bar_response & PCI_BASE_ADDRESS_MEM_PREFETCH))
87 bar_res = prefetch;
88 else
89 bar_res = mem;
90
91 debug("PCI Autoconfig: BAR %d, %s, size=0x%llx, ",
92 bar_nr, bar_res == prefetch ? "Prf" : "Mem",
93 (unsigned long long)bar_size);
94 }
95
96 ret = pciauto_region_allocate(bar_res, bar_size,
97 &bar_value, found_mem64);
98 if (ret)
99 printf("PCI: Failed autoconfig bar %x\n", bar);
100
101 if (!ret) {
102 /* Write it out and update our limit */
103 dm_pci_write_config32(dev, bar, (u32)bar_value);
104
105 if (found_mem64) {
106 bar += 4;
107 #ifdef CONFIG_SYS_PCI_64BIT
108 dm_pci_write_config32(dev, bar,
109 (u32)(bar_value >> 32));
110 #else
111 /*
112 * If we are a 64-bit decoder then increment to
113 * the upper 32 bits of the bar and force it to
114 * locate in the lower 4GB of memory.
115 */
116 dm_pci_write_config32(dev, bar, 0x00000000);
117 #endif
118 }
119 }
120
121 cmdstat |= (bar_response & PCI_BASE_ADDRESS_SPACE) ?
122 PCI_COMMAND_IO : PCI_COMMAND_MEMORY;
123
124 debug("\n");
125
126 bar_nr++;
127 }
128
129 /* Configure the expansion ROM address */
130 dm_pci_read_config8(dev, PCI_HEADER_TYPE, &header_type);
131 header_type &= 0x7f;
132 if (header_type != PCI_HEADER_TYPE_CARDBUS) {
133 rom_addr = (header_type == PCI_HEADER_TYPE_NORMAL) ?
134 PCI_ROM_ADDRESS : PCI_ROM_ADDRESS1;
135 dm_pci_write_config32(dev, rom_addr, 0xfffffffe);
136 dm_pci_read_config32(dev, rom_addr, &bar_response);
137 if (bar_response) {
138 bar_size = -(bar_response & ~1);
139 debug("PCI Autoconfig: ROM, size=%#x, ",
140 (unsigned int)bar_size);
141 if (pciauto_region_allocate(mem, bar_size, &bar_value,
142 false) == 0) {
143 dm_pci_write_config32(dev, rom_addr, bar_value);
144 }
145 cmdstat |= PCI_COMMAND_MEMORY;
146 debug("\n");
147 }
148 }
149
150 /* PCI_COMMAND_IO must be set for VGA device */
151 dm_pci_read_config16(dev, PCI_CLASS_DEVICE, &class);
152 if (class == PCI_CLASS_DISPLAY_VGA)
153 cmdstat |= PCI_COMMAND_IO;
154
155 dm_pci_write_config16(dev, PCI_COMMAND, cmdstat);
156 dm_pci_write_config8(dev, PCI_CACHE_LINE_SIZE,
157 CONFIG_SYS_PCI_CACHE_LINE_SIZE);
158 dm_pci_write_config8(dev, PCI_LATENCY_TIMER, 0x80);
159 }
160
dm_pciauto_prescan_setup_bridge(struct udevice * dev,int sub_bus)161 void dm_pciauto_prescan_setup_bridge(struct udevice *dev, int sub_bus)
162 {
163 struct pci_region *pci_mem;
164 struct pci_region *pci_prefetch;
165 struct pci_region *pci_io;
166 u16 cmdstat, prefechable_64;
167 struct udevice *ctlr = pci_get_controller(dev);
168 struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr);
169
170 pci_mem = ctlr_hose->pci_mem;
171 pci_prefetch = ctlr_hose->pci_prefetch;
172 pci_io = ctlr_hose->pci_io;
173
174 dm_pci_read_config16(dev, PCI_COMMAND, &cmdstat);
175 dm_pci_read_config16(dev, PCI_PREF_MEMORY_BASE, &prefechable_64);
176 prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
177
178 /* Configure bus number registers */
179 dm_pci_write_config8(dev, PCI_PRIMARY_BUS,
180 PCI_BUS(dm_pci_get_bdf(dev)) - dev_seq(ctlr));
181 dm_pci_write_config8(dev, PCI_SECONDARY_BUS, sub_bus - dev_seq(ctlr));
182 dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, 0xff);
183
184 if (pci_mem) {
185 /* Round memory allocator to 1MB boundary */
186 pciauto_region_align(pci_mem, 0x100000);
187
188 /*
189 * Set up memory and I/O filter limits, assume 32-bit
190 * I/O space
191 */
192 dm_pci_write_config16(dev, PCI_MEMORY_BASE,
193 (pci_mem->bus_lower & 0xfff00000) >> 16);
194
195 cmdstat |= PCI_COMMAND_MEMORY;
196 }
197
198 if (pci_prefetch) {
199 /* Round memory allocator to 1MB boundary */
200 pciauto_region_align(pci_prefetch, 0x100000);
201
202 /*
203 * Set up memory and I/O filter limits, assume 32-bit
204 * I/O space
205 */
206 dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE,
207 (pci_prefetch->bus_lower & 0xfff00000) >> 16);
208 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
209 #ifdef CONFIG_SYS_PCI_64BIT
210 dm_pci_write_config32(dev, PCI_PREF_BASE_UPPER32,
211 pci_prefetch->bus_lower >> 32);
212 #else
213 dm_pci_write_config32(dev, PCI_PREF_BASE_UPPER32, 0x0);
214 #endif
215
216 cmdstat |= PCI_COMMAND_MEMORY;
217 } else {
218 /* We don't support prefetchable memory for now, so disable */
219 dm_pci_write_config16(dev, PCI_PREF_MEMORY_BASE, 0x1000);
220 dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT, 0x0);
221 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64) {
222 dm_pci_write_config16(dev, PCI_PREF_BASE_UPPER32, 0x0);
223 dm_pci_write_config16(dev, PCI_PREF_LIMIT_UPPER32, 0x0);
224 }
225 }
226
227 if (pci_io) {
228 /* Round I/O allocator to 4KB boundary */
229 pciauto_region_align(pci_io, 0x1000);
230
231 dm_pci_write_config8(dev, PCI_IO_BASE,
232 (pci_io->bus_lower & 0x0000f000) >> 8);
233 dm_pci_write_config16(dev, PCI_IO_BASE_UPPER16,
234 (pci_io->bus_lower & 0xffff0000) >> 16);
235
236 cmdstat |= PCI_COMMAND_IO;
237 }
238
239 /* Enable memory and I/O accesses, enable bus master */
240 dm_pci_write_config16(dev, PCI_COMMAND, cmdstat | PCI_COMMAND_MASTER);
241 }
242
dm_pciauto_postscan_setup_bridge(struct udevice * dev,int sub_bus)243 void dm_pciauto_postscan_setup_bridge(struct udevice *dev, int sub_bus)
244 {
245 struct pci_region *pci_mem;
246 struct pci_region *pci_prefetch;
247 struct pci_region *pci_io;
248 struct udevice *ctlr = pci_get_controller(dev);
249 struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr);
250
251 pci_mem = ctlr_hose->pci_mem;
252 pci_prefetch = ctlr_hose->pci_prefetch;
253 pci_io = ctlr_hose->pci_io;
254
255 /* Configure bus number registers */
256 dm_pci_write_config8(dev, PCI_SUBORDINATE_BUS, sub_bus - dev_seq(ctlr));
257
258 if (pci_mem) {
259 /* Round memory allocator to 1MB boundary */
260 pciauto_region_align(pci_mem, 0x100000);
261
262 dm_pci_write_config16(dev, PCI_MEMORY_LIMIT,
263 (pci_mem->bus_lower - 1) >> 16);
264 }
265
266 if (pci_prefetch) {
267 u16 prefechable_64;
268
269 dm_pci_read_config16(dev, PCI_PREF_MEMORY_LIMIT,
270 &prefechable_64);
271 prefechable_64 &= PCI_PREF_RANGE_TYPE_MASK;
272
273 /* Round memory allocator to 1MB boundary */
274 pciauto_region_align(pci_prefetch, 0x100000);
275
276 dm_pci_write_config16(dev, PCI_PREF_MEMORY_LIMIT,
277 (pci_prefetch->bus_lower - 1) >> 16);
278 if (prefechable_64 == PCI_PREF_RANGE_TYPE_64)
279 #ifdef CONFIG_SYS_PCI_64BIT
280 dm_pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32,
281 (pci_prefetch->bus_lower - 1) >> 32);
282 #else
283 dm_pci_write_config32(dev, PCI_PREF_LIMIT_UPPER32, 0x0);
284 #endif
285 }
286
287 if (pci_io) {
288 /* Round I/O allocator to 4KB boundary */
289 pciauto_region_align(pci_io, 0x1000);
290
291 dm_pci_write_config8(dev, PCI_IO_LIMIT,
292 ((pci_io->bus_lower - 1) & 0x0000f000) >> 8);
293 dm_pci_write_config16(dev, PCI_IO_LIMIT_UPPER16,
294 ((pci_io->bus_lower - 1) & 0xffff0000) >> 16);
295 }
296 }
297
298 /*
299 * HJF: Changed this to return int. I think this is required
300 * to get the correct result when scanning bridges
301 */
dm_pciauto_config_device(struct udevice * dev)302 int dm_pciauto_config_device(struct udevice *dev)
303 {
304 struct pci_region *pci_mem;
305 struct pci_region *pci_prefetch;
306 struct pci_region *pci_io;
307 unsigned int sub_bus = PCI_BUS(dm_pci_get_bdf(dev));
308 unsigned short class;
309 struct udevice *ctlr = pci_get_controller(dev);
310 struct pci_controller *ctlr_hose = dev_get_uclass_priv(ctlr);
311 int ret;
312
313 pci_mem = ctlr_hose->pci_mem;
314 pci_prefetch = ctlr_hose->pci_prefetch;
315 pci_io = ctlr_hose->pci_io;
316
317 dm_pci_read_config16(dev, PCI_CLASS_DEVICE, &class);
318
319 switch (class) {
320 case PCI_CLASS_BRIDGE_PCI:
321 debug("PCI Autoconfig: Found P2P bridge, device %d\n",
322 PCI_DEV(dm_pci_get_bdf(dev)));
323
324 dm_pciauto_setup_device(dev, 2, pci_mem, pci_prefetch, pci_io);
325
326 ret = dm_pci_hose_probe_bus(dev);
327 if (ret < 0)
328 return log_msg_ret("probe", ret);
329 sub_bus = ret;
330 break;
331
332 case PCI_CLASS_BRIDGE_CARDBUS:
333 /*
334 * just do a minimal setup of the bridge,
335 * let the OS take care of the rest
336 */
337 dm_pciauto_setup_device(dev, 0, pci_mem, pci_prefetch, pci_io);
338
339 debug("PCI Autoconfig: Found P2CardBus bridge, device %d\n",
340 PCI_DEV(dm_pci_get_bdf(dev)));
341
342 break;
343
344 #if defined(CONFIG_PCIAUTO_SKIP_HOST_BRIDGE)
345 case PCI_CLASS_BRIDGE_OTHER:
346 debug("PCI Autoconfig: Skipping bridge device %d\n",
347 PCI_DEV(dm_pci_get_bdf(dev)));
348 break;
349 #endif
350 #if defined(CONFIG_ARCH_MPC834X) && !defined(CONFIG_TARGET_VME8349) && \
351 !defined(CONFIG_TARGET_CADDY2)
352 case PCI_CLASS_BRIDGE_OTHER:
353 /*
354 * The host/PCI bridge 1 seems broken in 8349 - it presents
355 * itself as 'PCI_CLASS_BRIDGE_OTHER' and appears as an _agent_
356 * device claiming resources io/mem/irq.. we only allow for
357 * the PIMMR window to be allocated (BAR0 - 1MB size)
358 */
359 debug("PCI Autoconfig: Broken bridge found, only minimal config\n");
360 dm_pciauto_setup_device(dev, 0, hose->pci_mem,
361 hose->pci_prefetch, hose->pci_io);
362 break;
363 #endif
364
365 case PCI_CLASS_PROCESSOR_POWERPC: /* an agent or end-point */
366 debug("PCI AutoConfig: Found PowerPC device\n");
367 /* fall through */
368
369 default:
370 dm_pciauto_setup_device(dev, 6, pci_mem, pci_prefetch, pci_io);
371 break;
372 }
373
374 return sub_bus;
375 }
376