1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef _CORE_TYPES_H_ 27 #define _CORE_TYPES_H_ 28 29 #include "dc.h" 30 #include "dce_calcs.h" 31 #include "dcn_calcs.h" 32 #include "ddc_service_types.h" 33 #include "dc_bios_types.h" 34 #include "mem_input.h" 35 #include "hubp.h" 36 #if defined(CONFIG_DRM_AMD_DC_DCN) 37 #include "mpc.h" 38 #endif 39 #include "dwb.h" 40 #include "mcif_wb.h" 41 #include "panel_cntl.h" 42 43 #define MAX_CLOCK_SOURCES 7 44 45 void enable_surface_flip_reporting(struct dc_plane_state *plane_state, 46 uint32_t controller_id); 47 48 #include "grph_object_id.h" 49 #include "link_encoder.h" 50 #include "stream_encoder.h" 51 #include "clock_source.h" 52 #include "audio.h" 53 #include "dm_pp_smu.h" 54 #ifdef CONFIG_DRM_AMD_DC_HDCP 55 #include "dm_cp_psp.h" 56 #endif 57 58 /************ link *****************/ 59 struct link_init_data { 60 const struct dc *dc; 61 struct dc_context *ctx; /* TODO: remove 'dal' when DC is complete. */ 62 uint32_t connector_index; /* this will be mapped to the HPD pins */ 63 uint32_t link_index; /* this is mapped to DAL display_index 64 TODO: remove it when DC is complete. */ 65 bool is_dpia_link; 66 }; 67 68 struct dc_link *link_create(const struct link_init_data *init_params); 69 void link_destroy(struct dc_link **link); 70 71 enum dc_status dc_link_validate_mode_timing( 72 const struct dc_stream_state *stream, 73 struct dc_link *link, 74 const struct dc_crtc_timing *timing); 75 76 void core_link_resume(struct dc_link *link); 77 78 void core_link_enable_stream( 79 struct dc_state *state, 80 struct pipe_ctx *pipe_ctx); 81 82 void core_link_disable_stream(struct pipe_ctx *pipe_ctx); 83 84 void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable); 85 /********** DAL Core*********************/ 86 #include "transform.h" 87 #include "dpp.h" 88 89 struct resource_pool; 90 struct dc_state; 91 struct resource_context; 92 struct clk_bw_params; 93 94 struct resource_funcs { 95 void (*destroy)(struct resource_pool **pool); 96 void (*link_init)(struct dc_link *link); 97 struct panel_cntl*(*panel_cntl_create)( 98 const struct panel_cntl_init_data *panel_cntl_init_data); 99 struct link_encoder *(*link_enc_create)( 100 const struct encoder_init_data *init); 101 /* Create a minimal link encoder object with no dc_link object 102 * associated with it. */ 103 struct link_encoder *(*link_enc_create_minimal)(struct dc_context *ctx, enum engine_id eng_id); 104 105 bool (*validate_bandwidth)( 106 struct dc *dc, 107 struct dc_state *context, 108 bool fast_validate); 109 void (*calculate_wm_and_dlg)( 110 struct dc *dc, struct dc_state *context, 111 display_e2e_pipe_params_st *pipes, 112 int pipe_cnt, 113 int vlevel); 114 void (*update_soc_for_wm_a)( 115 struct dc *dc, struct dc_state *context); 116 int (*populate_dml_pipes)( 117 struct dc *dc, 118 struct dc_state *context, 119 display_e2e_pipe_params_st *pipes, 120 bool fast_validate); 121 122 /* 123 * Algorithm for assigning available link encoders to links. 124 * 125 * Update link_enc_assignments table and link_enc_avail list accordingly in 126 * struct resource_context. 127 */ 128 void (*link_encs_assign)( 129 struct dc *dc, 130 struct dc_state *state, 131 struct dc_stream_state *streams[], 132 uint8_t stream_count); 133 /* 134 * Unassign a link encoder from a stream. 135 * 136 * Update link_enc_assignments table and link_enc_avail list accordingly in 137 * struct resource_context. 138 */ 139 void (*link_enc_unassign)( 140 struct dc_state *state, 141 struct dc_stream_state *stream); 142 143 enum dc_status (*validate_global)( 144 struct dc *dc, 145 struct dc_state *context); 146 147 struct pipe_ctx *(*acquire_idle_pipe_for_layer)( 148 struct dc_state *context, 149 const struct resource_pool *pool, 150 struct dc_stream_state *stream); 151 152 enum dc_status (*validate_plane)(const struct dc_plane_state *plane_state, struct dc_caps *caps); 153 154 enum dc_status (*add_stream_to_ctx)( 155 struct dc *dc, 156 struct dc_state *new_ctx, 157 struct dc_stream_state *dc_stream); 158 159 enum dc_status (*remove_stream_from_ctx)( 160 struct dc *dc, 161 struct dc_state *new_ctx, 162 struct dc_stream_state *stream); 163 enum dc_status (*patch_unknown_plane_state)( 164 struct dc_plane_state *plane_state); 165 166 struct stream_encoder *(*find_first_free_match_stream_enc_for_link)( 167 struct resource_context *res_ctx, 168 const struct resource_pool *pool, 169 struct dc_stream_state *stream); 170 void (*populate_dml_writeback_from_context)( 171 struct dc *dc, 172 struct resource_context *res_ctx, 173 display_e2e_pipe_params_st *pipes); 174 175 void (*set_mcif_arb_params)( 176 struct dc *dc, 177 struct dc_state *context, 178 display_e2e_pipe_params_st *pipes, 179 int pipe_cnt); 180 void (*update_bw_bounding_box)( 181 struct dc *dc, 182 struct clk_bw_params *bw_params); 183 #if defined(CONFIG_DRM_AMD_DC_DCN) 184 bool (*acquire_post_bldn_3dlut)( 185 struct resource_context *res_ctx, 186 const struct resource_pool *pool, 187 int mpcc_id, 188 struct dc_3dlut **lut, 189 struct dc_transfer_func **shaper); 190 191 bool (*release_post_bldn_3dlut)( 192 struct resource_context *res_ctx, 193 const struct resource_pool *pool, 194 struct dc_3dlut **lut, 195 struct dc_transfer_func **shaper); 196 #endif 197 enum dc_status (*add_dsc_to_stream_resource)( 198 struct dc *dc, struct dc_state *state, 199 struct dc_stream_state *stream); 200 }; 201 202 struct audio_support{ 203 bool dp_audio; 204 bool hdmi_audio_on_dongle; 205 bool hdmi_audio_native; 206 }; 207 208 #define NO_UNDERLAY_PIPE -1 209 210 struct resource_pool { 211 struct mem_input *mis[MAX_PIPES]; 212 struct hubp *hubps[MAX_PIPES]; 213 struct input_pixel_processor *ipps[MAX_PIPES]; 214 struct transform *transforms[MAX_PIPES]; 215 struct dpp *dpps[MAX_PIPES]; 216 struct output_pixel_processor *opps[MAX_PIPES]; 217 struct timing_generator *timing_generators[MAX_PIPES]; 218 struct stream_encoder *stream_enc[MAX_PIPES * 2]; 219 struct hubbub *hubbub; 220 struct mpc *mpc; 221 struct pp_smu_funcs *pp_smu; 222 struct dce_aux *engines[MAX_PIPES]; 223 struct dce_i2c_hw *hw_i2cs[MAX_PIPES]; 224 struct dce_i2c_sw *sw_i2cs[MAX_PIPES]; 225 bool i2c_hw_buffer_in_use; 226 227 struct dwbc *dwbc[MAX_DWB_PIPES]; 228 struct mcif_wb *mcif_wb[MAX_DWB_PIPES]; 229 struct { 230 unsigned int gsl_0:1; 231 unsigned int gsl_1:1; 232 unsigned int gsl_2:1; 233 } gsl_groups; 234 235 struct display_stream_compressor *dscs[MAX_PIPES]; 236 237 unsigned int pipe_count; 238 unsigned int underlay_pipe_index; 239 unsigned int stream_enc_count; 240 241 /* An array for accessing the link encoder objects that have been created. 242 * Index in array corresponds to engine ID - viz. 0: ENGINE_ID_DIGA 243 */ 244 struct link_encoder *link_encoders[MAX_DIG_LINK_ENCODERS]; 245 /* Number of DIG link encoder objects created - i.e. number of valid 246 * entries in link_encoders array. 247 */ 248 unsigned int dig_link_enc_count; 249 /* Number of USB4 DPIA (DisplayPort Input Adapter) link objects created.*/ 250 unsigned int usb4_dpia_count; 251 252 #if defined(CONFIG_DRM_AMD_DC_DCN) 253 unsigned int hpo_dp_stream_enc_count; 254 struct hpo_dp_stream_encoder *hpo_dp_stream_enc[MAX_HPO_DP2_ENCODERS]; 255 unsigned int hpo_dp_link_enc_count; 256 struct hpo_dp_link_encoder *hpo_dp_link_enc[MAX_HPO_DP2_LINK_ENCODERS]; 257 #endif 258 #if defined(CONFIG_DRM_AMD_DC_DCN) 259 struct dc_3dlut *mpc_lut[MAX_PIPES]; 260 struct dc_transfer_func *mpc_shaper[MAX_PIPES]; 261 #endif 262 struct { 263 unsigned int xtalin_clock_inKhz; 264 unsigned int dccg_ref_clock_inKhz; 265 unsigned int dchub_ref_clock_inKhz; 266 } ref_clocks; 267 unsigned int timing_generator_count; 268 unsigned int mpcc_count; 269 270 unsigned int writeback_pipe_count; 271 /* 272 * reserved clock source for DP 273 */ 274 struct clock_source *dp_clock_source; 275 276 struct clock_source *clock_sources[MAX_CLOCK_SOURCES]; 277 unsigned int clk_src_count; 278 279 struct audio *audios[MAX_AUDIOS]; 280 unsigned int audio_count; 281 struct audio_support audio_support; 282 283 struct dccg *dccg; 284 struct irq_service *irqs; 285 286 struct abm *abm; 287 struct dmcu *dmcu; 288 struct dmub_psr *psr; 289 290 #if defined(CONFIG_DRM_AMD_DC_DCN) 291 struct abm *multiple_abms[MAX_PIPES]; 292 #endif 293 294 const struct resource_funcs *funcs; 295 const struct resource_caps *res_cap; 296 297 struct ddc_service *oem_device; 298 }; 299 300 struct dcn_fe_bandwidth { 301 int dppclk_khz; 302 303 }; 304 305 struct stream_resource { 306 struct output_pixel_processor *opp; 307 struct display_stream_compressor *dsc; 308 struct timing_generator *tg; 309 struct stream_encoder *stream_enc; 310 #if defined(CONFIG_DRM_AMD_DC_DCN) 311 struct hpo_dp_stream_encoder *hpo_dp_stream_enc; 312 #endif 313 struct audio *audio; 314 315 struct pixel_clk_params pix_clk_params; 316 struct encoder_info_frame encoder_info_frame; 317 318 struct abm *abm; 319 /* There are only (num_pipes+1)/2 groups. 0 means unassigned, 320 * otherwise it's using group number 'gsl_group-1' 321 */ 322 uint8_t gsl_group; 323 }; 324 325 struct plane_resource { 326 struct scaler_data scl_data; 327 struct hubp *hubp; 328 struct mem_input *mi; 329 struct input_pixel_processor *ipp; 330 struct transform *xfm; 331 struct dpp *dpp; 332 uint8_t mpcc_inst; 333 334 struct dcn_fe_bandwidth bw; 335 }; 336 337 union pipe_update_flags { 338 struct { 339 uint32_t enable : 1; 340 uint32_t disable : 1; 341 uint32_t odm : 1; 342 uint32_t global_sync : 1; 343 uint32_t opp_changed : 1; 344 uint32_t tg_changed : 1; 345 uint32_t mpcc : 1; 346 uint32_t dppclk : 1; 347 uint32_t hubp_interdependent : 1; 348 uint32_t hubp_rq_dlg_ttu : 1; 349 uint32_t gamut_remap : 1; 350 uint32_t scaler : 1; 351 uint32_t viewport : 1; 352 uint32_t plane_changed : 1; 353 uint32_t det_size : 1; 354 } bits; 355 uint32_t raw; 356 }; 357 358 struct pipe_ctx { 359 struct dc_plane_state *plane_state; 360 struct dc_stream_state *stream; 361 362 struct plane_resource plane_res; 363 struct stream_resource stream_res; 364 365 struct clock_source *clock_source; 366 367 struct pll_settings pll_settings; 368 369 uint8_t pipe_idx; 370 371 struct pipe_ctx *top_pipe; 372 struct pipe_ctx *bottom_pipe; 373 struct pipe_ctx *next_odm_pipe; 374 struct pipe_ctx *prev_odm_pipe; 375 376 #ifdef CONFIG_DRM_AMD_DC_DCN 377 struct _vcs_dpi_display_dlg_regs_st dlg_regs; 378 struct _vcs_dpi_display_ttu_regs_st ttu_regs; 379 struct _vcs_dpi_display_rq_regs_st rq_regs; 380 struct _vcs_dpi_display_pipe_dest_params_st pipe_dlg_param; 381 struct _vcs_dpi_display_rq_params_st dml_rq_param; 382 struct _vcs_dpi_display_dlg_sys_params_st dml_dlg_sys_param; 383 struct _vcs_dpi_display_e2e_pipe_params_st dml_input; 384 int det_buffer_size_kb; 385 bool unbounded_req; 386 #endif 387 union pipe_update_flags update_flags; 388 struct dwbc *dwbc; 389 struct mcif_wb *mcif_wb; 390 bool vtp_locked; 391 }; 392 393 /* Data used for dynamic link encoder assignment. 394 * Tracks current and future assignments; available link encoders; 395 * and mode of operation (whether to use current or future assignments). 396 */ 397 struct link_enc_cfg_context { 398 enum link_enc_cfg_mode mode; 399 struct link_enc_assignment link_enc_assignments[MAX_PIPES]; 400 enum engine_id link_enc_avail[MAX_DIG_LINK_ENCODERS]; 401 struct link_enc_assignment transient_assignments[MAX_PIPES]; 402 }; 403 404 struct resource_context { 405 struct pipe_ctx pipe_ctx[MAX_PIPES]; 406 bool is_stream_enc_acquired[MAX_PIPES * 2]; 407 bool is_audio_acquired[MAX_PIPES]; 408 uint8_t clock_source_ref_count[MAX_CLOCK_SOURCES]; 409 uint8_t dp_clock_source_ref_count; 410 bool is_dsc_acquired[MAX_PIPES]; 411 struct link_enc_cfg_context link_enc_cfg_ctx; 412 #if defined(CONFIG_DRM_AMD_DC_DCN) 413 bool is_hpo_dp_stream_enc_acquired[MAX_HPO_DP2_ENCODERS]; 414 #endif 415 #if defined(CONFIG_DRM_AMD_DC_DCN) 416 bool is_mpc_3dlut_acquired[MAX_PIPES]; 417 #endif 418 }; 419 420 struct dce_bw_output { 421 bool cpuc_state_change_enable; 422 bool cpup_state_change_enable; 423 bool stutter_mode_enable; 424 bool nbp_state_change_enable; 425 bool all_displays_in_sync; 426 struct dce_watermarks urgent_wm_ns[MAX_PIPES]; 427 struct dce_watermarks stutter_exit_wm_ns[MAX_PIPES]; 428 struct dce_watermarks stutter_entry_wm_ns[MAX_PIPES]; 429 struct dce_watermarks nbp_state_change_wm_ns[MAX_PIPES]; 430 int sclk_khz; 431 int sclk_deep_sleep_khz; 432 int yclk_khz; 433 int dispclk_khz; 434 int blackout_recovery_time_us; 435 }; 436 437 struct dcn_bw_writeback { 438 struct mcif_arb_params mcif_wb_arb[MAX_DWB_PIPES]; 439 }; 440 441 struct dcn_bw_output { 442 struct dc_clocks clk; 443 struct dcn_watermark_set watermarks; 444 struct dcn_bw_writeback bw_writeback; 445 int compbuf_size_kb; 446 }; 447 448 union bw_output { 449 struct dcn_bw_output dcn; 450 struct dce_bw_output dce; 451 }; 452 453 struct bw_context { 454 union bw_output bw; 455 struct display_mode_lib dml; 456 }; 457 /** 458 * struct dc_state - The full description of a state requested by a user 459 * 460 * @streams: Stream properties 461 * @stream_status: The planes on a given stream 462 * @res_ctx: Persistent state of resources 463 * @bw_ctx: The output from bandwidth and watermark calculations and the DML 464 * @pp_display_cfg: PowerPlay clocks and settings 465 * @dcn_bw_vars: non-stack memory to support bandwidth calculations 466 * 467 */ 468 struct dc_state { 469 struct dc_stream_state *streams[MAX_PIPES]; 470 struct dc_stream_status stream_status[MAX_PIPES]; 471 uint8_t stream_count; 472 uint8_t stream_mask; 473 474 struct resource_context res_ctx; 475 476 struct bw_context bw_ctx; 477 478 /* Note: these are big structures, do *not* put on stack! */ 479 struct dm_pp_display_configuration pp_display_cfg; 480 #ifdef CONFIG_DRM_AMD_DC_DCN 481 struct dcn_bw_internal_vars dcn_bw_vars; 482 #endif 483 484 struct clk_mgr *clk_mgr; 485 486 struct kref refcount; 487 488 struct { 489 unsigned int stutter_period_us; 490 } perf_params; 491 }; 492 493 #endif /* _CORE_TYPES_H_ */ 494