1 /*
2  * Copyright 2017 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 #ifndef __DAL_DSC_H__
26 #define __DAL_DSC_H__
27 
28 #include "dc_dsc.h"
29 #include "dc_hw_types.h"
30 #include "dc_types.h"
31 /* do not include any other headers
32  * or else it might break Edid Utility functionality.
33  */
34 
35 
36 /* Input parameters for configuring DSC from the outside of DSC */
37 struct dsc_config {
38 	uint32_t pic_width;
39 	uint32_t pic_height;
40 	enum dc_pixel_encoding pixel_encoding;
41 	enum dc_color_depth color_depth;  /* Bits per component */
42 	bool is_odm;
43 	struct dc_dsc_config dc_dsc_cfg;
44 };
45 
46 
47 /* Output parameters for configuring DSC-related part of OPTC */
48 struct dsc_optc_config {
49 	uint32_t slice_width; /* Slice width in pixels */
50 	uint32_t bytes_per_pixel; /* Bytes per pixel in u3.28 format */
51 	bool is_pixel_format_444; /* 'true' if pixel format is 'RGB 444' or 'Simple YCbCr 4:2:2' (4:2:2 upsampled to 4:4:4)' */
52 };
53 
54 
55 struct dcn_dsc_state {
56 	uint32_t dsc_clock_en;
57 	uint32_t dsc_slice_width;
58 	uint32_t dsc_bits_per_pixel;
59 	uint32_t dsc_slice_height;
60 	uint32_t dsc_pic_width;
61 	uint32_t dsc_pic_height;
62 	uint32_t dsc_slice_bpg_offset;
63 	uint32_t dsc_chunk_size;
64 };
65 
66 
67 /* DSC encoder capabilities
68  * They differ from the DPCD DSC caps because they are based on AMD DSC encoder caps.
69  */
70 union dsc_enc_slice_caps {
71 	struct {
72 		uint8_t NUM_SLICES_1 : 1;
73 		uint8_t NUM_SLICES_2 : 1;
74 		uint8_t NUM_SLICES_3 : 1; /* This one is not per DSC spec, but our encoder supports it */
75 		uint8_t NUM_SLICES_4 : 1;
76 		uint8_t NUM_SLICES_8 : 1;
77 	} bits;
78 	uint8_t raw;
79 };
80 
81 struct dsc_enc_caps {
82 	uint8_t dsc_version;
83 	union dsc_enc_slice_caps slice_caps;
84 	int32_t lb_bit_depth;
85 	bool is_block_pred_supported;
86 	union dsc_color_formats color_formats;
87 	union dsc_color_depth color_depth;
88 	int32_t max_total_throughput_mps; /* Maximum total throughput with all the slices combined */
89 	int32_t max_slice_width;
90 	uint32_t bpp_increment_div; /* bpp increment divisor, e.g. if 16, it's 1/16th of a bit */
91 	bool is_dp;
92 };
93 
94 struct dsc_funcs {
95 	void (*dsc_get_enc_caps)(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz);
96 	void (*dsc_read_state)(struct display_stream_compressor *dsc, struct dcn_dsc_state *s);
97 	bool (*dsc_validate_stream)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg);
98 	void (*dsc_set_config)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
99 			struct dsc_optc_config *dsc_optc_cfg);
100 	bool (*dsc_get_packed_pps)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
101 			uint8_t *dsc_packed_pps);
102 	void (*dsc_enable)(struct display_stream_compressor *dsc, int opp_pipe);
103 	void (*dsc_disable)(struct display_stream_compressor *dsc);
104 };
105 
106 #endif
107