1/*
2 * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6#ifndef ASM_MACROS_S
7#define ASM_MACROS_S
8
9#include <arch.h>
10#include <common/asm_macros_common.S>
11#include <lib/spinlock.h>
12
13/*
14 * TLBI instruction with type specifier that implements the workaround for
15 * errata 813419 of Cortex-A57 or errata 1286807 of Cortex-A76.
16 */
17#if ERRATA_A57_813419 || ERRATA_A76_1286807
18#define TLB_INVALIDATE(_type) \
19	tlbi	_type; \
20	dsb	ish; \
21	tlbi	_type
22#else
23#define TLB_INVALIDATE(_type) \
24	tlbi	_type
25#endif
26
27
28	.macro	func_prologue
29	stp	x29, x30, [sp, #-0x10]!
30	mov	x29,sp
31	.endm
32
33	.macro	func_epilogue
34	ldp	x29, x30, [sp], #0x10
35	.endm
36
37
38	.macro	dcache_line_size  reg, tmp
39	mrs	\tmp, ctr_el0
40	ubfx	\tmp, \tmp, #16, #4
41	mov	\reg, #4
42	lsl	\reg, \reg, \tmp
43	.endm
44
45
46	.macro	icache_line_size  reg, tmp
47	mrs	\tmp, ctr_el0
48	and	\tmp, \tmp, #0xf
49	mov	\reg, #4
50	lsl	\reg, \reg, \tmp
51	.endm
52
53
54	.macro	smc_check  label
55	mrs	x0, esr_el3
56	ubfx	x0, x0, #ESR_EC_SHIFT, #ESR_EC_LENGTH
57	cmp	x0, #EC_AARCH64_SMC
58	b.ne	$label
59	.endm
60
61	/*
62	 * Declare the exception vector table, enforcing it is aligned on a
63	 * 2KB boundary, as required by the ARMv8 architecture.
64	 * Use zero bytes as the fill value to be stored in the padding bytes
65	 * so that it inserts illegal AArch64 instructions. This increases
66	 * security, robustness and potentially facilitates debugging.
67	 */
68	.macro vector_base  label, section_name=.vectors
69	.section \section_name, "ax"
70	.align 11, 0
71	\label:
72	.endm
73
74	/*
75	 * Create an entry in the exception vector table, enforcing it is
76	 * aligned on a 128-byte boundary, as required by the ARMv8 architecture.
77	 * Use zero bytes as the fill value to be stored in the padding bytes
78	 * so that it inserts illegal AArch64 instructions. This increases
79	 * security, robustness and potentially facilitates debugging.
80	 */
81	.macro vector_entry  label, section_name=.vectors
82	.cfi_sections .debug_frame
83	.section \section_name, "ax"
84	.align 7, 0
85	.type \label, %function
86	.cfi_startproc
87	\label:
88	.endm
89
90	/*
91	 * Add the bytes until fill the full exception vector, whose size is always
92	 * 32 instructions. If there are more than 32 instructions in the
93	 * exception vector then an error is emitted.
94	 */
95	.macro end_vector_entry label
96	.cfi_endproc
97	.fill	\label + (32 * 4) - .
98	.endm
99
100	/*
101	 * This macro calculates the base address of the current CPU's MP stack
102	 * using the plat_my_core_pos() index, the name of the stack storage
103	 * and the size of each stack
104	 * Out: X0 = physical address of stack base
105	 * Clobber: X30, X1, X2
106	 */
107	.macro get_my_mp_stack _name, _size
108	bl	plat_my_core_pos
109	adrp	x2, (\_name + \_size)
110	add	x2, x2, :lo12:(\_name + \_size)
111	mov x1, #\_size
112	madd x0, x0, x1, x2
113	.endm
114
115	/*
116	 * This macro calculates the base address of a UP stack using the
117	 * name of the stack storage and the size of the stack
118	 * Out: X0 = physical address of stack base
119	 */
120	.macro get_up_stack _name, _size
121	adrp	x0, (\_name + \_size)
122	add	x0, x0, :lo12:(\_name + \_size)
123	.endm
124
125	/*
126	 * Helper macro to generate the best mov/movk combinations according
127	 * the value to be moved. The 16 bits from '_shift' are tested and
128	 * if not zero, they are moved into '_reg' without affecting
129	 * other bits.
130	 */
131	.macro _mov_imm16 _reg, _val, _shift
132		.if (\_val >> \_shift) & 0xffff
133			.if (\_val & (1 << \_shift - 1))
134				movk	\_reg, (\_val >> \_shift) & 0xffff, LSL \_shift
135			.else
136				mov	\_reg, \_val & (0xffff << \_shift)
137			.endif
138		.endif
139	.endm
140
141	/*
142	 * Helper macro to load arbitrary values into 32 or 64-bit registers
143	 * which generates the best mov/movk combinations. Many base addresses
144	 * are 64KB aligned the macro will eliminate updating bits 15:0 in
145	 * that case
146	 */
147	.macro mov_imm _reg, _val
148		.if (\_val) == 0
149			mov	\_reg, #0
150		.else
151			_mov_imm16	\_reg, (\_val), 0
152			_mov_imm16	\_reg, (\_val), 16
153			_mov_imm16	\_reg, (\_val), 32
154			_mov_imm16	\_reg, (\_val), 48
155		.endif
156	.endm
157
158	/*
159	 * Macro to mark instances where we're jumping to a function and don't
160	 * expect a return. To provide the function being jumped to with
161	 * additional information, we use 'bl' instruction to jump rather than
162	 * 'b'.
163         *
164	 * Debuggers infer the location of a call from where LR points to, which
165	 * is usually the instruction after 'bl'. If this macro expansion
166	 * happens to be the last location in a function, that'll cause the LR
167	 * to point a location beyond the function, thereby misleading debugger
168	 * back trace. We therefore insert a 'nop' after the function call for
169	 * debug builds, unless 'skip_nop' parameter is non-zero.
170	 */
171	.macro no_ret _func:req, skip_nop=0
172	bl	\_func
173#if DEBUG
174	.ifeq \skip_nop
175	nop
176	.endif
177#endif
178	.endm
179
180	/*
181	 * Reserve space for a spin lock in assembly file.
182	 */
183	.macro define_asm_spinlock _name:req
184	.align	SPINLOCK_ASM_ALIGN
185	\_name:
186	.space	SPINLOCK_ASM_SIZE
187	.endm
188
189#if RAS_EXTENSION
190	.macro esb
191	.inst	0xd503221f
192	.endm
193#endif
194
195	/*
196	 * Helper macro to read system register value into x0
197	 */
198	.macro	read reg:req
199#if ENABLE_BTI
200	bti	j
201#endif
202	mrs	x0, \reg
203	ret
204	.endm
205
206	/*
207	 * Helper macro to write value from x1 to system register
208	 */
209	.macro	write reg:req
210#if ENABLE_BTI
211	bti	j
212#endif
213	msr	\reg, x1
214	ret
215	.endm
216
217	/*
218	 * Macro for mitigating against speculative execution beyond ERET. Uses the
219	 * speculation barrier instruction introduced by FEAT_SB, if it's enabled.
220	 */
221	.macro exception_return
222	eret
223#if ENABLE_FEAT_SB
224	sb
225#else
226	dsb	nsh
227	isb
228#endif
229	.endm
230
231#endif /* ASM_MACROS_S */
232