1 /* SPDX-License-Identifier: GPL-2.0+ or BSD-3-Clause */ 2 /* 3 * include/linux/clk/at91_pmc.h 4 * 5 * Copyright (C) 2005 Ivan Kokshaysky 6 * Copyright (C) SAN People 7 * Copyright (C) 2021 Microchip 8 * 9 * Power Management Controller (PMC) - System peripherals registers. 10 * Based on AT91RM9200 datasheet revision E. 11 */ 12 13 #ifndef AT91_CLK_H 14 #define AT91_CLK_H 15 16 #include <drivers/clk.h> 17 #include <drivers/clk_dt.h> 18 19 #include "at91_pmc.h" 20 21 #define ffs(x) __builtin_ffs(x) 22 23 #define field_get(_mask, _reg) \ 24 ({ \ 25 typeof(_mask) __mask = _mask; \ 26 \ 27 (((_reg) & (__mask)) >> (ffs(__mask) - 1)); \ 28 }) 29 #define field_prep(_mask, _val) \ 30 ({ \ 31 typeof(_mask) __mask = _mask; \ 32 \ 33 (((_val) << (ffs(__mask) - 1)) & (__mask)); \ 34 }) 35 36 struct clk_range { 37 unsigned long min; 38 unsigned long max; 39 }; 40 41 #define CLK_RANGE(MIN, MAX) {.min = MIN, .max = MAX,} 42 43 struct pmc_clk { 44 struct clk *clk; 45 uint8_t id; 46 }; 47 48 struct pmc_data { 49 vaddr_t base; 50 unsigned int ncore; 51 struct pmc_clk *chws; 52 unsigned int nsystem; 53 struct pmc_clk *shws; 54 unsigned int nperiph; 55 struct pmc_clk *phws; 56 unsigned int ngck; 57 struct pmc_clk *ghws; 58 unsigned int npck; 59 struct pmc_clk *pchws; 60 61 struct pmc_clk hwtable[]; 62 }; 63 64 /* PLL */ 65 struct clk_pll_layout { 66 uint32_t pllr_mask; 67 uint32_t mul_mask; 68 uint32_t frac_mask; 69 uint32_t div_mask; 70 uint32_t endiv_mask; 71 uint8_t mul_shift; 72 uint8_t frac_shift; 73 uint8_t div_shift; 74 uint8_t endiv_shift; 75 }; 76 77 struct clk_pcr_layout { 78 uint32_t offset; 79 uint32_t cmd; 80 uint32_t div_mask; 81 uint32_t gckcss_mask; 82 uint32_t pid_mask; 83 }; 84 85 struct clk_pll_charac { 86 struct clk_range input; 87 int num_output; 88 const struct clk_range *output; 89 uint16_t *icpll; 90 uint8_t *out; 91 uint8_t upll : 1; 92 }; 93 94 extern const struct clk_pll_layout sama5d3_pll_layout; 95 96 /* Master */ 97 struct clk_master_charac { 98 struct clk_range output; 99 uint32_t divisors[5]; 100 uint8_t have_div3_pres; 101 }; 102 103 struct clk_master_layout { 104 uint32_t offset; 105 uint32_t mask; 106 uint8_t pres_shift; 107 }; 108 109 struct clk_programmable_layout { 110 uint8_t pres_mask; 111 uint8_t pres_shift; 112 uint8_t css_mask; 113 uint8_t have_slck_mck; 114 uint8_t is_pres_direct; 115 }; 116 117 extern const struct clk_master_layout at91sam9x5_master_layout; 118 119 vaddr_t at91_pmc_get_base(void); 120 121 struct pmc_data *pmc_data_allocate(unsigned int ncore, unsigned int nsystem, 122 unsigned int nperiph, unsigned int ngck, 123 unsigned int npck); 124 125 struct clk *clk_dt_pmc_get(struct dt_driver_phandle_args *args, void *data, 126 TEE_Result *res); 127 128 struct clk *pmc_clk_get_by_name(struct pmc_clk *clks, unsigned int nclk, 129 const char *name); 130 131 /* Main clock */ 132 struct clk *pmc_register_main_rc_osc(struct pmc_data *pmc, const char *name, 133 unsigned long freq); 134 135 struct clk *pmc_register_main_osc(struct pmc_data *pmc, const char *name, 136 struct clk *parent, bool bypass); 137 138 struct clk *at91_clk_register_sam9x5_main(struct pmc_data *pmc, 139 const char *name, 140 struct clk **parent_clocks, 141 unsigned int num_parents); 142 143 /* PLL */ 144 struct clk * 145 at91_clk_register_pll(struct pmc_data *pmc, const char *name, 146 struct clk *parent, uint8_t id, 147 const struct clk_pll_layout *layout, 148 const struct clk_pll_charac *charac); 149 150 struct clk * 151 at91_clk_register_plldiv(struct pmc_data *pmc, const char *name, 152 struct clk *parent); 153 154 /* UTMI */ 155 struct clk * 156 at91_clk_register_utmi(struct pmc_data *pmc, const char *name, 157 struct clk *parent); 158 159 /* Master */ 160 struct clk * 161 at91_clk_register_master_pres(struct pmc_data *pmc, 162 const char *name, int num_parents, 163 struct clk **parents, 164 const struct clk_master_layout *layout, 165 const struct clk_master_charac *charac, 166 int chg_pid); 167 168 struct clk * 169 at91_clk_register_master_div(struct pmc_data *pmc, 170 const char *name, struct clk *parent, 171 const struct clk_master_layout *layout, 172 const struct clk_master_charac *charac); 173 174 /* H32MX */ 175 struct clk * 176 at91_clk_register_h32mx(struct pmc_data *pmc, const char *name, 177 struct clk *parent); 178 179 /* USB */ 180 struct clk * 181 at91sam9x5_clk_register_usb(struct pmc_data *pmc, const char *name, 182 struct clk **parents, uint8_t num_parents); 183 184 /* Programmable */ 185 struct clk * 186 at91_clk_register_programmable(struct pmc_data *pmc, 187 const char *name, struct clk **parents, 188 uint8_t num_parents, uint8_t id, 189 const struct clk_programmable_layout *layout); 190 191 struct clk * 192 at91_clk_register_system(struct pmc_data *pmc, const char *name, 193 struct clk *parent, uint8_t id); 194 195 struct clk * 196 at91_clk_register_sam9x5_periph(struct pmc_data *pmc, 197 const struct clk_pcr_layout *layout, 198 const char *name, struct clk *parent, 199 uint32_t id, const struct clk_range *range); 200 201 struct clk * 202 at91_clk_register_generated(struct pmc_data *pmc, 203 const struct clk_pcr_layout *layout, 204 const char *name, struct clk **parents, 205 uint8_t num_parents, uint8_t id, 206 const struct clk_range *range, 207 int chg_pid); 208 209 struct clk * 210 at91_clk_i2s_mux_register(const char *name, struct clk **parents, 211 unsigned int num_parents, uint8_t bus_id); 212 213 /* Audio PLL */ 214 struct clk * 215 at91_clk_register_audio_pll_frac(struct pmc_data *pmc, const char *name, 216 struct clk *parent); 217 218 struct clk * 219 at91_clk_register_audio_pll_pad(struct pmc_data *pmc, const char *name, 220 struct clk *parent); 221 222 struct clk * 223 at91_clk_register_audio_pll_pmc(struct pmc_data *pmc, const char *name, 224 struct clk *parent); 225 226 #endif 227